The present invention generally relates to optical computing and data processing systems and, in particular, to multistage lensless optical analog data processors capable of processing bipolar and complex data.

From Applied Optics, Vol. 23, No. 6, 15 March, 1984, pages 817 - 821, a pipelined polynomial processor implemented with integrated optical components is disclosed. This arrangement can be used to evaluate polynomials with positive coeffitients.

Optical processing of vector and matrix data is known for its potentially highly effective computational performance capabilities and its natural adaptability to computationally intensive image processing. Images, or other spatially relatable data, may be treated as matrices composed of raster or vector scans of data elements that, at their real or effective resolution limit, are generally referred to as pixels. An ordinary image is typified by an analog picture frame taken as a cross section of an optical beam formed of a continuous series of such images. Each analog image frame typically contains an effectively continuous spatially distributed array of pixel data. Alternatively, discrete matrix data may be impressed onto a data beam by spatially modulating the cross section of a data beam in terms of, for example, either its localized intensity or polarization vector.

In any case, optical processing is of great potential value due to its fundamentally parallel processing nature. The parallelism, of course, arises due to the processing of complete images at a time. As each pixel is a separate datum, the volume of data processed in parallel is generally equivalent to the effective resolution of the image. Additionally, optical processing has the virtue of processing data in the same format that it is conventionally obtained. Typically, and for such applications as image enhancement and recognition, the data to be processed is generally obtained as a single image or as a raster scan of an image frame. Potentially then, an optical processor may receive data directly without conventional or other intermediate processing. Since the informative value of image data increases with the effective resolution of the image and the number of images considered, the particular and unique attributes of optical processing become quite desireable.

Conventionally, optical processing is performed by projecting an image to be processed through a selected spatial mask onto an appropriate optical detector. A temporally variable mask for optical processors has been realized as a one-dimensional spatial light modulator (SLM) that, through electronic activation, effects selective alteration of the spatially distributed data impressed on a data beam by the mask. A typical SLM is in the form of a solid electro-optical element activated by a spatially distributed array of electrodes. The modulating image is effectively formed by separately establishing the voltage potential of each of the electrodes at an analog voltage corresponding to the respective intended data values.

Optical data processors of the type described above are disclosed in United States Patent US-A-4,747,069 entitled Programmable Multistage Lensless Optical Data Processing System, invented by Jan Grinberg and Bernard H. Soffer, and United States Patent Application US-A-4,764,891 entitled Programmable Methods of Performing Complex Optical Computations Using Data Processing System, invented by Jan Grinberg, Graham R. Nudd, and Bernard H. Soffer.

A limitation in the use of these optical data processors is that they are designed to handle analog positive numbers only. This is so because these numbers are represented by light intensities which are nonnegative quantities. The prior art mechanizations are, for the most part, limited to the handling of real numbers.

Accordingly, it is an object of the present invention to provide new and improved optical data processing systems capable of handling both positive and negative numbers.

It is another object of the present invention to provide optical data processing systems capable of handling both real and complex numbers.

The foregoing and other objects of the invention are accomplished in a first aspect of the invention, according to claim 1, by providing an optical data processor for processing both positive and negative numbers using space multiplexing. The processor includes a first modulator for spatially modulating an optical beam in response to a first number and having first and second modulation areas.

A second modulator is provided for spatially modulating the optical beam exiting the first modular in response to a second number. This modulator has third and fourth modulation areas where the third and fourth modulation areas each intercept light modulated by both the first and second modulation areas.

A light detector is included having four light detection areas. The first detection area is responsive to light modulated by the first and third modulation areas. The second detection area is responsive to light modulated by the second and third modulation areas. The third detection area is responsive to light modulated by the first and fourth modulation areas, and the fourth detection area is responsive to light modulated by the second and fourth modulation areas.

Control circuitry enables the first number to modulate the beam at the first modulation area if the first number is positive and to modulate the beam at the second modulation area if the first number is negative, where the degree of modulation at the first and second modulation areas is proportional to the magnitude of the first number. The control circuitry also enables the second number to modulate the beam at the third modulation area if the second number is positive and to modulate the beam at the fourth modulation area if the second number is negative, where the degree of modulation at the third and fourth modulation areas is proportional to the magnitude of the second number.

A second aspect of the invention, according to claim 3, includes an optical processor for multiplying both positive and negative numbers using both space and time multiplexing, and eliminates most of the nonlinearities associated with the previous embodiment. This processor includes a first modulator for spatially modulating an optical beam in response to a first number and a first position bias signal and has first and second modulation areas.

A second modulator spatially modulates the optical beam in response to a second number and a second bias signal and is positioned so that the beam is modulated both by the first and second modulators. This modulator has a third modulation area which modulates the same portion of the beam modulated by both the first and second modulation areas. A light detector is included having two light detection areas. The first detection area provides a first detector signal in response to light modulated by the first and third modulation areas, and the second detection area provides a second detector signal in response to light modulated by the second and third modulation areas.

A first control signal is generated which is the sum of the first number and the first bias signal, a second control signal is generated which is the difference between the first bias signal and the first number, a third control signal is generated which is the sum of the second number and the second bias signal, and a fourth control signal is generated which is the difference between the second bias signal and the second number.

Control circuitry controls the optical processing of the first and second numbers in a first interval of time by enabling the first control signal to modulate the beam at the first modulation area, enabling the second control signal to modulate the beam at the second modulation area, and enabling the third control signal to modulate the beam at the third modulation area.

The optical processing of the first and second numbers in a second interval of time is controlled by enabling the second control signal to modulate the beam at the first modulation area, enabling the first control signal to modulate the beam at the second modulation area, and enabling the fourth control signal to modulate the beam at the third modulation area. The degree of modulation of the modulation areas is proportional to the magnitude of the control signal applied to the respective area.

An accumulator, preferably incorporated as part of the light detector, sums the first detector signal over the first and second intervals of time and provides this sum to the positive input terminal of a differential amplifier. The accumulator also sums the second detector signal over the first and second intervals of time and provides this sum to the negative input terminal of the differential amplifier. The output signal from the amplifier is proportional to the desired product of the first and second numbers.

A third aspect of the invention, according to claim 6, includes an optical processor for processing complex numbers using space multiplexing. A first complex number is decomposed into three real positive-valued components, α&sub1;, β&sub1;, γ&sub1;, respectively, and a second complex number is decomposed into three real positive-valued components α&sub2;, β&sub2;, γ&sub2; respectively.

A first modulator is provided for spatially modulating an optical beam in response to the components α&sub1;, β&sub1;, γ&sub1;, and includes first, second and third modulation areas. A second modulator spatially modulates the optical beam exiting the first modulator in response to the components α&sub2;, β&sub2;, γ&sub2; and includes fourth, fifth and sixth modulation areas.

A light detector is provided having nine light detection areas. The first detection area is responsive to light modulated by the first and fourth modulation areas, the second detection area is responsive to light modulated by the first and fifth modulation areas, the third detection area is responsive to light modulated by the first and sixth modulation areas, the fourth detection area is responsive to light modulated by the second and fourth modulation areas, the fifth detection area is responsive to light modulated by the second and fifth modulation areas, the sixth detection area is responsive to light modulated by the second and sixth modulation areas, the seventh detection area is responsive to light modulated by the third and fourth modulation areas, the eighth detection area is responsive to light modulated by the third and fifth modulation areas, and the ninth detection area is responsive to light modulated by the third and sixth modulation areas. As will be explained below, the responses of certain prescribed detection areas must be summed to obtain the components α, β, γ of the product.

Control circuitry enables the components α&sub1;, β&sub1;, γ&sub1; to modulate the beam at the first, second and third modulation areas, respectively, and enables the components α&sub2;, β&sub2;, γ&sub2; to modulate the beam at the fourth, fifth and sixth modulation ares, respectively. The degree of modulation at each modulation area is proportional to the magnitude of the respective component.

A fourth aspect of the invention, according to claim 11, includes an optical processor for processing complex numbers using both space and time multiplexing. As in the previous embodiment, a first complex number is decomposed into three real positive-valued vectors α&sub1;, β&sub1;, γ&sub1;, respectively, and a second complex number is decomposed into three real positive-valued vectors α&sub2;, β&sub2;, γ&sub2;, respectively.

A first modulator spatially modulates an optical beam in response to the vectors α&sub1;, β&sub1;, γ&sub1; and has first, second and third modulation areas. A second modulator spatially modulates an optical beam in response to the vectors α&sub2;, β&sub2;, γ&sub2;, and has a fourth modulation area.

A light detector is provided having three light detection areas. The first detection area is responsive to light modulated by the first and fourth modulation areas, the second light detection area is responsive to light modulated by the second and fourth modulation areas, and the third detection area is responsive to light modulated by the third and fourth modulation areas.

Control circuitry controls the optical processing of the complex numbers in a first interval of time by enabling the vectors α&sub1;, β&sub1;, and γ&sub1; to modulate the beam at the first, second, and third modulation areas, respectively, and to enable the vector α&sub2; to modulate the beam at the fourth modulation area. The circuitry controls the optical processing of the complex numbers in a second interval of time by enabling the vectors α&sub1;, β&sub1;, γ&sub1; to modulate the beam at the second, third and first modulation areas, respectively, and to enable the vector β&sub2; to modulate the fourth modulation areas. The circuitry also controls the optical processing of the complex numbers in a third interval of time by enabling the vectors α&sub1;, β&sub1;, and γ&sub1; to modulate the beam at the third, first and second modulation areas, respectively, and to enable the vector γ&sub2; to modulate the fourth modulation area. The degree of modulation of the first through fourth modulation areas is proportional to the magnitude of the respective vector modulating that area.

A fifth aspect of the invention, according to claim 8, includes an optical processor for multiplying complex numbers using both space and time multiplexing in conjunction with bias signals. Unlike the previous embodiment, the complex numbers need not be decomposed into components α, β, γ. Further, this embodiment eliminates most of the nonlinearities associated with the previous embodiment.

A first modulator spatially modulates an optical beam in response to the real and imaginary parts of a first complex number and a first bias signal and has first and second modulation areas. A second modulator spatially modulates an optical beam in response to the real and imaginary parts of a second complex number and a second bias signal and has third and fourth modulation areas.

A light detector is provided having four light detection areas. The first detection area provides a first detector signal in response to light modulated by the first and third modulation areas, the second light detection area provides a second detector signal in response to light modulated by the first and fourth modulation areas, the third detection area provides a third detector signal in response to light modulated by the second and third modulation areas, and the fourth detection area provides a fourth detector signal in response to light modulated by the second and fourth modulation areas.

A first control signal Is generated which is the sum of the real part of the first complex number and the first bias signal. A second control signal is generated which is the difference between the first bias signal and the real part of the first complex number. A third control signal is generated which is the sum of the imaginary part of the first complex number and the first bias signal. A fourth control signal is generated which is the difference between the first bias signal and the imaginary part of the first complex number.

A fifth control signal is generated which is the sum of the real part of the second complex number and the second bias signal. A sixth control signal is generated which is the difference between the second bias signal and the real part of the second complex number. A seventh control signal is generated which is the sum of the imaginary part of the second complex number and the second bias signal, and an eighth control signal is generated which is the difference between the second bias signal and the imaginary part of the second complex number.

Control circuitry controls the optical processing of the complex numbers in a first interval of time by enabling the first, second, eighth and seventh control signals to modulate the beam at the first, second, third and fourth modulation areas, respectively. The circuitry controls the optical processing of the complex numbers in a second interval of time by enabling the second, first, seventh and eighth control signals to modulate the beam at the first, second, third and fourth modulation areas, respectively. The circuitry controls the optical processing of the complex numbers in a third interval of time by enabling the third, fourth, sixth and fifth control signals to modulate the beam at the first, second, third and fourth modulation areas, respectively. Finally, the circuitry controls the optical processing of the complex numbers in a fourth interval of time by enabling the fourth, third, fifth and sixth control signals to modulate the beam at the first, second, third and fourth modulation areas, respectively. The degree of modulation of the modulation areas is proportional to the magnitude of the control signal appplied to the respective area.

An accumulator, preferrably incorporated as part of the light detector, sums over the four intervals of time and for each of the four detection areas, the detector signals generated over the four intervals at each of these areas. Analog data shifting circuitry, also preferrably incorporated as part of the light detector, provides during a fifth interval of time, the summed signals from the first detector area to the positive input terminal of a differential amplifier, and the summed signal from the third detection area to the negative input terminal of the amplifier. The output signal from the amplifier during this fifth interval of time is proportional to the real part of the product of the first and second complex numbers.

During a sixth interval of time the summed signals from the second and fourth detection areas are provided, respectively, to the positive and negative input terminals of the differential amplifier. During the sixth interval of time, the output signal from the amplifier is proportional to the imaginary part of the product of the first and second complex numbers.

Other objects, features and advantages of the invention will become apparent from a reading of the specification when taken in conjunction with the drawings in which like reference numerals refer to like elements throughout the several views.

• Figure 1 is a block diagram of an optical data processing system in accordance with the present invention;
• Figure 2 is a side view of an optical data processor constructed in accordance with the present invention;
• Figure 3 is a perspective view of an electro-optical spatial light modulator for use in the present invention;
• Figure 4 is a perspective view of another electro-optical spatial light modulator for use in the present invention;
• Figure 5 is an exploded perspective representation of a prior art optical data processing system for processing matrices comprising unipolar real numbers;
• Figure 6 is an exploded perspective view of an optical processor constructed in accordance with a first embodiment of the invention for processing bipolar data using space multiplexing;
• Figure 7 is an exploded perspective view of a unit cell portion of an optical processor constructed in accordance with a second embodiment of the invention for processing bipolar data using space and time multiplexing;
• Figure 8 is an exploded perspective view of a unit cell portion of an optical processor constructed in accordance with a third embodiment of the invention for processing complex data using space multiplexing;
• Figure 9 is an exploded view of a unit cell portion of an optical processor constructed in accordance with a fourth embodiment of the invention for processing complex data using space and time multiplexing;
• Figure 10 is an exploded view of a unit cell portion of an optical processor similar to that shown in Figure 9 but employing an additional electro-optical spatial light modulator; and
• Figure 11 is an exploded view of a unit cell portion of an optical processor constructed in accordance with a fourth embodiment of the invention for processing complex data using space and time multiplexing in conjunction with bias signals.

The preferred system embodiment for use with the present invention, generally indicated by the reference numeral 10, is shown in Figure 1. In particular, the preferred multistage optical data processor (ODP), generally indicated by the reference numeral 20, is operatively supported by a microcontroller 12 and interface registers 18, 22, 24, 26, 30, 32 and 34. The priciple operative components of the ODP are shown in Figure 1 as including a flat panel or LED light source 14, matrix array accumulator (also referred to as a detector array) 16 and a plurality of spatial light modulators (SLMs) 36, 38, 40, 42, 44 and 46. Preferably, the light source 14, accumulator 16 and the SLMs 36, 38, 40, 42, 44, 46 are provided in closely adjacent parallel planes with respect to one another such that a relatively uniform beam sourced by the light source 14 travels through each of the spatial light modulators in succession and is ultimately received by the accumulator 16.

The light beam is effectively used as a data transport mechanism acquiring data provided by each of the spatial light modulators that is subsequently delivered to the accumulator 16. The operation of each of the spatial light modulators can be explained in terms of their spatial transmissivity variation with respect to corresponding spatially distributed activating voltage potentials. To a first approximation at least, the light amplitude transmissivity of a spatial light modulator is directly proportional to the applied voltage potential. Thus, the combined transmissivity (T0) of two serially coupled spatial light modulators is proportional to the product of the respective transmissivities T1, T2 of the spatial light modulators. The combined transmissivity T0 can thus be written as:



T0 = T1 x T2   (1)



T0 = C x D x V1 x V2   (2)



   V1 and V2 are the respectively applied voltage potentials, and C and D are the transmissivity to applied voltage coefficients for the respective spatial light modulators. Where an extended series of spatial light modulators are serially coupled, in accordance with the present invention, the combined transmissivity T0 of the multistage spatial light modulator stack is proportional to the product of the respective transmissivities of the individual spatial light modulators. A light beam sourced by the flat panel 14 can thus be directed to acquire spatially distributed data corresponding to the spatially distributed relative transmissivities of each of the spatial light modulators 36, 38, 40, 42, 44 and 46.

In accordance with the preferred embodiment of the optical processor used in accordance with the present invention, spatially relatable data is provided to the spatial light modulators 36, 38, 40, 42, 44 and 46 via the interface registers 22, 24, 26, 30, 32 and 34. These registers preferably operate as high speed digital data storage registers, buffers and digital-to-analog data converters. As will be discussed in greater detail below, the stack of spatial light modulators preferably includes a plurality of one-dimensional spatial light modulators. As shown in Figure 1, one-dimensional spatial light modulators 36, 38, 40, 42, 44 and 46 are coupled to respective registers 22, 30, 24, 32 and 26 via interface data lines 60, 78, 62, 80, 64 and 82.

The interface registers 22, 24, 26, 30, 32 and 34 in turn preferably receive data in a parallel form provided by external sources. The microcontroller 12 via the processor control buses 50, 70 provides the control signals. While the processor control buses 50, 70 are shown as separate and respectively connected to the registers by the register control lines 52, 54, 56, 72, 74 and 76, the interface registers may alternately be coupled via control multiplexers to a single, common control bus driven by the microcontroller 12. In either case, however, it is essential only that the microcontroller 12 possess sufficient control over the registers 22, 24, 26, 30, 32 and 34 to selectively provide its predetermined data thereto.

The optical data processor system 10 is completed with the provision of the output register 18 coupled between the accumulator 16 and the processor output. The accumulator 16 itself is a matrix array of photosensitive devices capable of converting incident light intensity into a corresponding voltage potential representative of the data beam at an array resolution at least matching that of the spatial light modulators 36, 38, 40, 42, 44 and 46. As will be described in greater detail below, the accumulator 16 accumulates light beam data that can then be shifted by means of a clock signal supplied by a clock generator 83 to the data output register 18 via the output interface bus 88. The accumulator 16 also includes circular shift bus 86 and lateral shift bus 84 to permit a wide variety of shift and sum operations to be performed within the accumulator 16 during the operation of the optical data processor 20.

The data output register 18 is preferably a high speed analog-to-digital converter, shift register and buffer that channels the shifted output data from the accumulator 16 to the processor output via the processor data output bus 90.

As should be well apparent from the foregoing, the microcontroller 12 possesses full control over the optical data processor 20. Any desired data can be provided to any specific combination of spatial light modulators to implement a desired data processing algorithm. Of particular facility is that only those spatial light modulators required for the performance of any particular optical data processing algorithm need be actively utilized in the optical data processor 20 in accordance with the present invention. Spatial light modulators within the optical data processor 20 may be provided with appropriate data via their respective data registers to uniformly maintain the spatial light modulators at their maxium transmissivity. Consequently, selected spatial light modulators may be effectively removed from the optical data processor by their appropriate data programming. Thus, the optical data processing system 10 provides an extremely flexible environment for the performance of optical data processing computations.

The structure of an optical data processor 20 fabricated in accordance with the preferred optical processor embodiment of the present invention is shown in Figure 2. The embodiment shown is expemplary as including substantially all of the principle components that may be incorporated into any preferred embodiment of the optical processor.

The components of the optical data processor include the light source 14, SLM stages 36 through 46 and detector array 16. The flat panel light source 14 is preferably an electroluminescent display panel or, alternately, a gas plasma display panel or LED or LED array or laser diode or laser diode array. A diffuser (not shown) may be utilzed to grade the light produced by the flat display panel into a spatially uniform optical beam.

The bulk of the optical data processor 20 is formed by a serial stack of SLM stages, of which SLM stage 46 is representative. Preferably, the SLM is a rigid structure requiring no additional support. in such embodiments, the SLMs may be placed immediately adjacent one another, separated only by a thin insulating optically transparent layer, yielding an optimally compact multistage stack of spatial light modulators. In embodiments where the operation of the spatial light modulator is accomplished through the polarization modulation of the light beam, polarizers 64 are preferably interposed between the SLMs. The polarizer 64 further permits the utilization of an unpolarized optical data beam source 14 in local polarization vector data representation embodiments of the present invention. If the principle of operation of the spatial light modulators is light absorption (instead of polarization rotation), then there is no need for the polarizers.

The accumulator 16 is preferably a solid state matrix array of optical detectors. In particular, the optical detector array is preferably a shift register array of conventional charge couple devices (CCDs) provided at an array density equivalent to the effective resolution Of the optical data processor 20. The use of a CCD array is preferred both for its charge accumulation, i.e., data summing, capability as well as for the ease of fabricating CCD shift register circuitry that can be directly controlled by the microcontroller 12. Further, the use of the CCD array permits substantial flexibility in the operation of the accumulator 16 by permitting data shifted out of the accumulator 16 and onto the data return bus 88 to be cycled back into the accumulator 16 via the circular shift data bus 86. Additionally, the accumulator 16 possesses the desirable flexibility through the use of adjacent register propagation path interconnections to permit lateral cycling of the data contained therein via the lateral shift data bus 84 as indicated in Figure 1. Consequently, the accumulator 16 can be effectively utilized in the execution of quite complex optical data processing algorithms involving shift and sum operations under the direct control of the microcontroller 12.

Two preferred embodiments of one-dimensional spatial light modulators are shown in Figures 3 and 4, respectively. The spatial light modulator 130 shown in Figure 3 includes an electro-optic element 132 preferably having two major parallel opposing surfaces upon which stripe electrodes 136 and potential reference plane 140 are provided, respectively. The electro-optic element 132 may be a transmission mode liquid crystal light valve though preferably it is a solid state electro-optic material, such as KD&sub2;PO&sub4; or BaTiO&sub3;. This latter material polarization modulates light locally in proportion to the longitudinal and transverse voltage potential applied across the portion of the material that the light passes through. This material chacteristically possesses sufficient structural strength to be adequately self-supporting for purposes of the present invention when utilized as electro-optic elements 132 and may be provided at a thickness of approximately 5 to 10 mils for a major surface area of approximately one square inch.

As the active regions of the electro-optical element 132 necessarily lay between each of the stripe electrodes 136 and the reference plane electrode 140, the electrodes 136, 140 are preferably of a high conductivity transparent material such as indium tin oxide. Contact to the electrodes 136, 140 is preferably accomplished throughb the use of separate electrode leads 134, 138, respectively, that are attached using conventional wire bonding or solder bump interconnect technology.

Figure 4 illustrates an alternate one-dimensional spatial light modulator. This spatial light modulator differs from that of Figure 3 by the relative placement of the signal 156 and potential reference 158 electrodes on the two major surfaces of the electro-optic element 152. On each major surface, a reference potential electrode 158 is interposed between pairs of the signal electrodes 156 to form an interdigitated electrode structure that is essentially identical on both major surfaces of the electro-optic element 152. The active portions of the electro-optic element 152 lie between each of the signal electrodes 156 and their surface neighboring reference potential electrodes 158.

Thus, the achievable electro-optic effect is enhanced through the utilization of both surfaces of the electro-optic element 152. Further, as the active portions of the electro-optic element 152 are not shadowed by the signal electrodes 156, all of the electrodes 156, 168 may be of an opaque conductive material, such as aluminum, that may be further advantageously utilized to effectively mask the active regions of the electro-optic element 152. That is, the electrodes 156, 158 may be utilized to block the respective pixel edge portions of the data beam as they diverge while passing through the electro-optic element 152.

Similar to the spatial light modulators 130 of Figure 3, the electro-optic element 152 may be either a liquid crystal light valve or a solid state electro-optic material. For reasons of faster electro-optic response time, greater structural strength, and ease of fabrication, transverse field polarization modulation electro-optic materials, such as represented by LiNbO&sub3;, LiTaO&sub3;, BaTiO&sub3;, Sr_xBa_(1-x)NbO&sub3; and PLZT are preferred.

The operation of an optical data processing system of the type described above is best understood by analyzing its operation in performing matrix multiplication. R.A. Athale and W.C. Collins, in their paper "Optical Matrix-matrix Multiplier Based on Outer Product Decomposition," Applied Optics 21, 2089 (1982) have described the principle of outer product decomposition for optical matrix multiplication.

Thus the product matrix C of two matrices B and A is given by



C = BA   (3)



where the ij-th element of C is given by the inner product between the i-th row vector of B and the j-th column vector of A.

However, C can also be written as a sum of matrices, each of which is the outer product between a column vector of B and the corresponding row vector of A. The principle behind an outer product matrix multiplier is to sequentially provide the rows of matrix B into an SLM such as SLM 38 and the corresponding columns of matrix A into another SLM such as SLM 36 which is orthogonal to the first SLM. The transmission of the two crossed SLMs during the nth clock cycle of clock generator 83 is given by the outer product of the nth row of B and the nth column of A. The transmitted light falls on accumulator detector array 16 and is summed to form the product matrix C. The multiplication of two NxN matrices, which requires N³ multiplications, is performed in N clock cycles.

Figure 5 shows the elements of the two matrices A and B as they are provided by storage registers 30 and 22 to SLMs 38 and 36, one row and column at a time, respectively. (Polarizers which are located between the SLMs have been omitted from Figure 5 for the sake of clarity.) The electrodes on each SLM 36, 38 divide the SLM into strip shaped regions 92, 94, hereinafter referred to as unit cells. Each cell is used to process a matrix element. During the nth clock cycle, light from source 14 is modulated in one direction by the nth row of A and in the orthogonal direction by the nth column of B, forming the nth outer product matrix at the accumulator detector array 16, the sum of which is the product matrix C. Note that only two SLMs are required for the matrix multiplication operation. The array 16 is divided into cells 96, where each cell corresponds to one of the elements c_ij.

While the above described prior art optical processor works well when all elements of the matrices are positive, it is not designed to handle bipolar (negative and positive) or complex numbers. This is so because numerical values are represented by light intensities, which are non-negative quantities.

Figure 6 shows a first embodiment 20' of the invention which is an optical processor capable of processing bipolar numbers. To aid the reader in understanding the various embodiments of the invention, the matrix multiplication example used above, where each matrix is square and contains nine elements, will be used in describing the operation of several of the various embodiments.

The embodiment 20' includes first and second SLMs 38' and 36', respectively, a detector accumulator 16' and a light source 14 arraanged in a manner similar to that previously described. The SLM 36' is divided into three stripe shaped unit cells 92', and the SLM 38' is divided into three stripe shaped unit cells 94'. The cells 92' are orthogonal to the cells 94'.

Each of the cells 92' is in turn partitioned into individually addressable light modulation areas 98 and 100, while each cell 94' is partitioned into individually addressable light modulation areas 102 and 104. The accumulator 16' is divided into nine unit cells 96'. Each cell 96' is partitioned into four light detection areas 106, 108, 110, 112. Portions of the unit cells 92', 94', 96' are shown in detail on the right in Figure 6.

The operation of the processor 20' is as follows. Signals representing the magnitude of each of the column elements of matrix A (one column at a time) are provided to the cells 94' of SLM 38' by register 30. If the polarity of an element is positive, the signal is routed by suitable control circuitry associated with register 30 to the area 102 of the respective cell 94'. If the polarity of the element is negative, the signal representing that element is routed to the area 104 of the respective cell 94'.

In similar fashion, signals representing the magnitude of each of the row elements of matrix B (one row at a time) are provided to the cells 92' of SLM 36 by register 22. If the polarity of a particular element is positive, the signal is routed by suitable control circuitry associated with register 22 to the area 98 of the respective cell 92'. If the polarity of the element is negative, the signal representing that element is routed to the area 100 of the respective cell 92'.

The four detection areas 106, 108, 110, 112 In each cell 96' of detector 16' are positioned so that each area intercepts light modulated by particular modulation areas of the SLMs 36' and 38'. Thus, area 106 detects light modulated by areas 102 and 98, area 108 detects light modulated by areas 102 and 100, area 110 detects light modulated by areas 104 and 98, and area 112 detects light mdulated by areas 104 and 110.

The polarity symbols shown in the unit cell representation in Figure 6 indicate the polarity of the matrix elements in each of the cells 94' and 92', as well as the polarity of the resultant multiplication of these elements, as detected by the various areas of unit cell 96' of detector 16'. For example, area 106 detects the product of two positive numbers, and hence is positive. Likewise, area 112 detects the product of two negative numbers, and hence is also positive. By summing the signals from detector areas 106 and 112, a signal proportional to the square of the positive product of matrix elements is obtained, and by summing the signals from detector areas 108 and 110, a signal proportional to the square of the negative product of matrix element is obtained. By taking the difference between these two signals, a resultant signal is obtained which includes the square of the product of the two bipolar numbers. Read-out of data from the detector 16' may be accomplished in 2N clock cycles for an NxN matrix array, two clock cycles being allocated to each cell. Since different areas of each cell are used to distinguish polarity, the embodiment 20' is referred to as a space-multiplexed configuration.

One of the limitations of the prior described space multiplexed embodiment is that the output signals from the detector/accumulator 16' are not directly proportional to the product of the matrix elements, but are instead proportional to the square of these products. This is so because of the square relationship between light amplitude and intensity. The modulators 38' and 36' modulate the amplitude of the light from source 14 in proportion to the magnitude of the applied signals. However, detector 16' provides signals proportional to light intensity, which is in turn proportional to the square of the light amplitude.

Accordingly, in the prior described embodiment, the detector signals must undergo further signal processing to extract the desired numerical product from the squared value, which is also biased by various arithmetic cross products. In a second embodiment of the invention 20'' shown in Figure 7, a combination of space and time multiplexing is employed along with bias signals to provide a bipolar number optical processor whose output signals are directly proportional to the product of the bipolar numbers.

In the past, time multiplexed configurations have been suggested for optically processing bipolar numbers. For example, D. Casasent, J. Jackson, and C. Neuman propose one such configuaration in their article "Frequency-multiplexed and Pipelined Iterative Optical Systolic Array Processors," Applied Optics, Vol. 22, No. 1, page 115, January 1, 1983. However, these prior art processors do not directly provide output signals which are linearly proportional to the product of the bipolar numbers, as is accomplished in the following embodiment.

Referring to Figure 7, there is shown unit cell portions of first and second SLMs and of a detector/accumulator array which collectively form an optical processor. It is to be understood that, as in the previous embodiment, multiple cells may be employed to process matrix arrays of complex data.

The unit cell 94'' represents one cell of an SLM such as the SLM 38 previously described. Likewise cell 92'' represents one cell of an SLM such as SLM 36, and cell 96'' represents one cell of a detector/accumulator array 16, also previously described.

The cell 94'' is partitioned into two individually addressable light modulation areas 170 and 172, while cell 92'' consists of a single addressable light modulation area. Detector cell 96'' is partitioned into two light detection areas 174 and 176.

The two detection areas 174, 176 are positioned so that each area intercepts light modulated by particular modulation areas. Thus, area 174 detects light modulated by areas 170 and 92'', and area 176 detects light modulated by areas 172 and 92''. Detector signals accumulated in area 174 are applied to a positive input terminal of a differential amplifier 230, while detector signals accumulated in area 176 are applied to a negative input terminal of the amplifier 230. As described below, the desired output signal d from the processor 20'' is provided at output terminal 232 of the amplifier 230.

Signal processing circuitry is provided to generate signals used to control modulators 94'' and 92'' as follows. A signal representing a first bipolar number a&sub1;&sub1;, which may be a matrix element, is provided to the positive input terminal of a summing amplifier 234 and to the negative input terminal of a differential amplifier 236. A positive bias signal Δ&sub1; is applied to the positive input terminals of the amplifiers 234 and 236. Appearing at the output terminal of amplifier 234 is control signal S&sub1;, which is equal to a&sub1;&sub1; + Δ&sub1;. Appearing at the output terminal of amplifier 236 is control signal S&sub2; which is equal to Δ&sub1; - a&sub1;&sub1;.

A second signal representing a bipolar number b&sub1;&sub1;, which may be an element of a second matrix, is provided to the positive input terminal of a summing amplifier 238, and to the negative input terminal of a differential amplifier 240. A second positive bias signal Δ&sub2; is applied to the positive input terminals of the amplifiers 238 and 240. Appearing at the output terminal of amplifier 238 is control signal r&sub1;, which is equal to b&sub1;&sub1; + Δ&sub2;. Appearing at the output terminal of amplifier 240 is control signal r&sub2;, which is equal to Δ&sub2; - b&sub1;&sub1;.

The operation of the processor 20'' is as follows. During a first clock interval τ&sub1; as determined by clock generator 83, control signals are provided to cells 94'' and 92'' as follows. Control signal S&sub1; is applied to modulation area 170, control signal S&sub2; is applied to modulator area 172, and control signal r&sub1; is applied to modulation area 92''. Detection areas 174 and 176 respond to the modulated light and provide detector signals which are accumulated by the accumulator portion of the detector/accumulator 96''.

During a second clock interval τ&sub2;, control signals S&sub2;, S&sub1; and r&sub2; are provided to modulation areas 170, 172, and 92'', respectively, as indicated by the time lines in Figure 7. Detection areas 174 and 176 respond to modulated light and provide detector signals during this interval of time which are added, in each of the cells 174, 176 to the detector signals accumulated in these cells from the prior interval, τ&sub1;.

It should be noted that the amplitude of the positive bias signal Δ&sub1; Is chosen to bias the modulation areas 170, 172 at a point which will maintain these areas in their linear region of light amplitude modulation over the largest anticipated positive and negative magnitude range of the bipolar number a&sub1;&sub1;. Similarly, bias signal Δ&sub2; is chosen to maintain the area 92'' in its linear light amplitude modulation response region over the largest anticipated positive and negative magnitude range of the bipolar number b&sub1;&sub1;. The amplitudes of the bias signals Δ&sub1; and Δ&sub2; may be equal to each other.

As described above, the accumulated signals from detection areas 174 and 176 are provided to the positive and negative input terminals, respectively, of differential amplifier 230. It may be shown that, at the end of the second interval of time τ&sub2;, the output signal d appearing at the output terminal 232 is proportional to



d = 16 Δ&sub1; Δ&sub2; a&sub1;&sub1; b&sub1;&sub1;   (5)



   Accordingly, the processor 20'' provides an output signal directly proportional to the product of bipolar numbers.

A third embodiment of the invention, shown in Figure 8 is an optical processor using space multiplexing to process complex numbers. It is known that complex bipolar data may be decomposed into three real and positive vector components, each representing a vector oriented along the 0°, 120° and 240° polar directions. See for example J.W. Goodman and L.M. Woody, "Method for Performing Complex-valued Linear Operations on Complex-valued Data Using Incoherent Light," Applied Optics, Volume 16, p.2611 (1977). Thus a complex value X may be decomposed into



X = X_α + X_β exp(i2π/3) + X_γ exp(i4π/3).   (6)



where X_α, X_β and X_γ are real positive quantities.

Figure 8 shows an optical processor 20''' capable of multiplying two complex numbers which have been decomposed by a suitable arithmetic processor (not shown) into their α, β and γ components. The figure shows only the unit cell portions of the first and second SLMs and the detector array of the processor. It is to be understood that, as in the previous embodiments, multiple cells may be employed to process matrix arrays of complex data.

The unit cell 94''' represents one cell of an SLM such as the SLM 38 described in previous embodiments. Likewise cell 92''' represents one cell of an SLM such as SLM 36 previously described, and cell 96''' represents one cell of a detector such as 16, also previously described.

The cell 94''' is partitioned into three individually addressable light modulation areas 178, 180, 182, while cell 92''' is partitioned into three individually addressable light modulation areas 184, 186, 188 which are orthogonal to the areas of the cell 94'''. The detector cell 96''' is divided into nine light detection areas 190, 192, 194, 196, 198, 200, 202, 204, 206.

The operation of the processor 20''' is as follows. Signals representing the magnitude of the α, β and γ components of a complex number "a" are provided to the modulation areas 178, 180 and 182, respectively of cell 94'''. Signals representing the magnitude of the α, β and γ components of a second complex number "b" are provided to the modulation areas 184, 186 and 188 of cell 92'''.

The nine detection areas in each cell 96''' of the detector are positioned so that each area intercepts light modulated by particular ones of the modulation areas in cells 94''' and 92'''. Thus, area 190 intercepts light modulated by areas 178 and 184, area 192 intercepts light modulated by areas 178 and 186, area 194 intercepts light modulated by areas 178 and 188, area 196 intercepts light modulated by areas 180 and 184, area 198 intercepts light modulated by areas 180 and 186, area 200 intercepts light modulated by areas 180 and 188, area 202 intercepts light modulated by areas 182 and 184, area 204 intercepts light modulated by areas 182 and 186, and area 206 intercepts light modulated by areas 182 and 188.

The α, β and γ symbols shown in each of the nine detector areas in Figure 8 indicate the cyclic association of the various component products, which can be readily derived using the definition of products in the polar representation of complex numbers. The various α, β and γ component products may be read-out from cell 96''' in three clock intervals and arithmetically combined in a well known fashion to obtain in Cartesion coordinates signals including the squares of the real and imaginary parts of the product of complex numbers "a" and "b."

A fourth embodiment of the invention 20'''' shown in Figure 9 uses a combination of space and time multiplexing to process complex numbers, where the numbers have been decomposed into three real, positive components as described in the previous embodiment.

Figure 9 shows the unit cell construction of the first and second SLMs and the detector array of the processor 20''''. As in the previous embodiments, multiple cells may be employed to process arrays of complex data.

The unit cell 94'''' represents one cell of an SLM such as the SLM 38 described above. Likewise the cell 92'''' represents one cell of an SLM such as SLM 36, and cell 96'''' represents one cell of a detector such as 16, also previously described.

The cell 94'''' is partitioned into three individually addressable light modulation areas 208, 210, 212 which are orthogonal to the modulation area defined by cell 92''''. Detector cell 96'''' is partitioned into three light detection areas 214, 216, 218.

The operation of the processor 20'''' is as follows. During a first clock interval τ&sub1; as determined by clock generator 83, signals representing the magnitude of the α, β and γ components of a complex number "a" are provided to the modulation areas 208, 210 and 212, respectively, of cell 94''''. A signal representing the magnitude of only the α component of a second complex number "b" is provided to the modulation area 92''''.

During a second clock interval τ&sub2;, signals representing the γ, α, and β components of "a" are provided to the areas 208, 210, and 212, respectively, while only the β component of "b" is provided to area 92''''.

During a third clock interval τ&sub3;, signals representing the β, γ, and α components of "a" are provided to the areas 208, 210 and 212, respectively, while only the γ component of "b" is provided to area 92''''.

The three detection areas 214, 216, 218 in each cell 96'''' are positioned so that each area intercepts light modulated by particular combinations of the modulation areas. Thus, area 214 intercepts light modulated by areas 208 and 92'''', area 216 intercepts light modulated by areas 210 and 92'''', and area 218 intercepts light modulated by areas 212 and 92''''.

The α, β and γ symbols and time lines shown in Figure 9 indicate for each of the intervals τ&sub1;, τ&sub2;, τ&sub3;, the components provided to each of the modulation areas, as well as the association of the various component products as derived using the definition of products in the polar representation of complex numbers. It will be appreciated by those skilled in the art that the particular cyclic pattern of α, β and γ components provided to the modulation areas is chosen to provide a single component association in the detector areas over the three clock intervals. Accordingly, the detection areas 214, 216, and 218 are always associated with α, β and γ product values, respectively. This mechanization greatly simplifies read-out of data from cells 96'''', which may be accomplished in one clock interval, the data associated with each vector being read in parallel.

Note that while the third and fourth embodiments described above employ tri-vector decomposition of complex numbers, other decomposition schemes may be employed which are within the scope of the invention. For example, complex numbers may be decomposed into two or four components, with the resultant components being processed using the principles described above.

It is also to be noted that while the above examples of the invention describe the multiplication of two matrices, the invention is by no means limited thereto. An expansion of the optical processor architecture to handle more matrices simply requires additional layers of SLMs.

By way of example, Figure 10 shows the unit cell representation of an optical processor 224 employing space and time multiplexing for processing three matrices containing complex elements. By comparing Figure 10 with Figure 9 it will be apparent that the construction of the processor 224 is substantially identical to that of processor 20'''' with the addition of a third SLM represented by unit cell 226. This third SLM may be seen to correspond to SLM 40 in Figures 1 and 2.

The processor 224 operates over nine clock intervals, and the details of operation can be readily derived from the α, β and γ designators and time lines in Figure 10 in view of the previous description of the processor 20''''.

As in the case of the first embodiment of the invention, the third and fourth embodiments just described provide output signals from the detector/accumulator which are not directly proportional to the product of the complex numbers. In a fifth embodiment of the invention 20''''' shown in Figure 11, a unique combination of space and time multiplexing is employed along with bias signals to provide a complex number optical processor which does not require vector decomposition and which generates output signals which are directly proportional to the product of complex numbers.

Referring to Figure 11, there is shown the unit cell construction of the processor 20''''' used to multiply a first complex number "a" having real and imaginary parts a_r and a_i, respectively, with a second complex number "b" having real and imaginary parts b_r and b_i, respectively. As in the previous embodiments, multiple cells may be employed to parallel process arrays of complex data.

The unit cell 94''''' represents one cell of an SLM such as the SLM 38 described above. Likewise the cell 92''''' represents one cell of an SLM such as SLM 36, and cell 96''''' represents one cell of a detector such as 16, also previously described.

The cell 94''''' is partitioned into two individually addressable light modulation areas 209, 211 which are orthogonal to two individually addressable light modulation areas 213, 215 defined by cell 92'''''. Detector cell 96''''' is partitioned into four light detection areas 217, 219, 221, 223.

The four detection areas 217, 219, 221, 223 in each cell 96''''' are positioned so that each area intercepts light modulated by particular combinations of the modulation areas. Thus, area 217 intercepts light modulated by areas 209 and 213, area 219 intercepts light modulated by areas 211 and 213, area 221 intercepts light modulated by areas 209 and 215 and area 223 intercepts light modulated by areas 211 and 215.

Detector signals accumulated from areas 217 and 219 are applied to positive and negative input terminals, respectively, of a differential amplifier 242. As described earlier with reference to Figure 1, clock signals from generator 83 may be used to shift data in the detector/accumulator represented by cell 96'''''. In the present embodiment, as described below, data accumulated in areas 217 and 219 provide at amplifier output terminal 244 a signal d_r directly proportional to the real part of the product of complex numbers "a" and "b." Clock signals cause the detector signals accumulated from areas 221 and 223 to be shifted to the positive and negative terminals, respectively, of the amplifier 242, at which time a signal d_i directly proportional to the imaginary part of the product of the complex numbers "a" and "b" is provided at the terminal 244.

Signal processing circuitry is provided to generate signals to control modulators 94''''' and 92'''' as follows. A signal representing the real part a_r of a first complex number "a" is provided to the positive input of a summing amplifier 246 and to a negative input terminal of a differential amplifier 248. A positive bias signal Δ&sub3; is applied to the positive input terminals of the amplifiers 246, 248. Appearing at the output terminal of amplifier 246 is control signal t&sub1; which is equal to a_r + Δ&sub3;. Appearing at the output terminal of amplifier 248 is control signal t&sub2; which is equal to Δ&sub3; + a_r.

A signal representing the imaginary part a_i of the number "a" is provided to a positive input terminal of summing amplifier 250 and to a negative input terminal of differfential amplifier 252. Bias signal Δ&sub3; is provided to the positive input terminals of the amplifiers 250 and 252. Appearing at the output terminal of amplifier 250 is control signal u&sub1; which is equal to a_i + Δ&sub3;. Appearing at the output terminal of amplifier 252 is control signal u&sub2; which is equal to Δ&sub3; - a_i.

A signal representing the real part b_r of a second complex number "b" is provided to the positive input of a summing amplifier 254 and to a negative input terminal of a differential amplifier 256. A positive bias signal Δ&sub4; is applied to the positive input terminals of the amplifiers 254, 256. Appearing at the output terminal, of amplifier 254 is control signal v&sub1; which is equal to b_r + Δ&sub4;. Appearing at the output terminal of amplifier 256 is control signal v&sub2; which is equal to Δ&sub4; + b_r.

A signal representing the imaginary part b_i of the number "b" is provided to a positive input terminal of summing amplifier 258 and to a negative input terminal of differfential amplifier 260. Bias signal Δ&sub4; is provided to the positive input terminals of the amplifiers 258 and 260. Appearing at the output terminal of amplifier 258 is control signal ω&sub1; which is equal to b_i + Δ&sub4;. Appearing at the output terminal of amplifier 260 is control signal ω&sub2; which is equal to Δ&sub4; - b_i.

The operation of the processor 20''''' is as follows. During a first clock interval τ&sub1;, as determined by clock generator 83, control signals are provided to cells 94''''' and 92''''' as follows. Control signals t&sub2;, t&sub1;, ω&sub1; and ω&sub2; are applied to modulate areas 209, 211, 215 and 213, respectively. Detector areas 217, 219, 221, and 223 respond to the modulated light and provide detector signals which are accumulated by the accumulator portion of the element 96'''''.

During a second clock interval τ&sub2;, control signals t&sub2;, t&sub1;, ω&sub2; and ω&sub1; are provided to areas 209, 211, 215, and 213, respectively. During a third clock interval τ&sub3;, control signals u&sub1;, u&sub2;, v&sub1;, and v&sub2; are provided to modulate areas 209, 211, 215, and 213, respectively. During a fourth clock interval τ&sub4;, control signals u&sub2;, ω&sub1;, v&sub2; and v&sub1; are provided to the areas 209, 211, 215 and 213, respectively. For each of the detector cells 217, 219, 221, and 223, accumulators sum the detector signals generated over the four clock intervals τ&sub1; - τ&sub4;.

It should be noted that the amplitude of the positive bias signal Δ&sub3; is chosen to bias the modulator areas 209, 211 at a point which will maintain these areas in their linear light amplitude modulation region over the largest anticipated positive and negative magnitude range of the numbers a_r and a_i. Similarly, bias signal Δ&sub4; is chosen to maintain the areas 213, 215 in their linear light amplitude modulation response region over the largest anticipated positive and negative magnitude range of the numbers b_r and b_i. The amplitudes of the bias signals Δ&sub3; and Δ&sub4; may be equal to each other.

At the completion of the fourth clock interval τ&sub4;, the accumulated data from detector areas 217, 219 are provided to the amplifier 242 as described above. It may be shown that the output signal d_r appearing at the output terminal 244 is proportional to



d_r = 16 Δ&sub3; Δ&sub4; (a_rb_r - a_ib_i)   (7)



   Suitable clock signals may be applied to the detector/accumulator, using well known techniques, to shift data accumulated from detector areas 221 and 223 so that this data is now provided as input signals to the amplifier 242. When this occurs, it may be shown that the output signal d_i appearing at the output terminal 244 is proportional to



d_i = 16 Δ&sub3; Δ&sub4;(a_rb_r + a_ib_i)   (8)



   Accordingly, the processor 20''''' provides output signals directly proportional to the real and imaginary portions of the product of the complex numbers "a" and "b."

While the above embodiment of the invention describes the multiplication of two numbers, which may be elements of two matrices, the embodiment is by no means limited thereto. An expansion of the optical processor architecture to handle more matrices simply requires additional layers of SLMs, as described previously.

In the instance where it is desirable to multiply two matrices together with a positive number, this may be accomplished with an optical processor having only two SLMs, by making use of the modulation properties of the light source. For example, the second embodiment of the invention, Figure 7, may be modified to obtain the product of the two matrix elements a&sub1;&sub1;, b&sub1;&sub1; and a third positive number c by modulating the intensity of the light source 14 in proportion to the magnitude of the number c. Thus, if the light source 14 is in the form of an LED, the current through the LED can be modulated by a signal proportional to the number c. In this instance, it may be shown that the signal d appearing at the output terminal 232 is modified from that shown in equation 5 to the following:



d = 16 Δ&sub1; Δ&sub2; c a&sub1;&sub1;b&sub1;&sub1;   (9)



   It will be appreciated that the modulation of the light source may be extended to use in any of the invention embodiments.