The present invention relates to a trigonometric function arithmetic
processor, and more specifically to a trigonometric function arithmetic processor
for use in computers.

Description of related art

Trigonometric functions such as sin ϑ and cos ϑ are
function having a period of 2π namely 360 degrees. An ability of calculating
the trigonometric functions is one function indispensable to computers processing
scientific and technical computations.

Hitherto, as a means for obtaining the value of the trigonometric
function, there have been known to use rational function approximations such as
Taylor expansion which can be expressed as
sin ϑ = ϑ - ϑ³/3! + ϑ&sup5;/5! -
ϑ&sup7;/7!

series fraction expansion, and Chebyshev expansion. However, these
methods need a number of multiplication operations and division operations and
therefore, require a long operation time. In addition, the satisfied degree of
precision cannot be obtained.

Further, a so-called "CORDIC" (coordinate rotation digital computer)
arithmetic is known as a trigonometric function arithmetic operation method suitable
to microprogram controlled computers. This method can be executed by using addition,
subtraction and right shift, and therefore, can be efficiently executed in computers
which do not have a high speed multiplication unit.

Here, an arithmetic principle of the CORDIC will be described below
with reference to a case in which the values of sin ϑ and cos ϑ are
obtained with the precision of n-digits in a binary notation

An angle ϑ can be expressed as follows, by using a constant
"rk" and a sequence of numbers {ak}:
ϑ = a&sub0; x r&sub0; + a&sub1; x r&sub1; + a&sub2; x r&sub2;
.....
..... a_{n-1} x r_{n-1} + ε

where
rk = arctan (2^{-k}) ak = {+1, -1}

The sequence of numbers {ak} can be spontaneously determined in accordance
with a method similar to the division of a non-restoring method. therefore, the
process for determining the sequence of numbers {ak} will be called a "pseudo-division"
hereinafter.

Here, according to the theorem of addition, in the case of ak = +1
ψk + 1 = ψk + rk cos (ψk + 1) =Rk(cos ψk - 2^{-k} x sin ψk) sin (ψk + 1) = Rk(sin ψk - 2^{-k} x cos ψk)

in the case of ak = -1
ψk + 1 = ψk - rk cos (ψk + 1) =Rk(cos ψk + 2^{-k} x sin ψk) sin (ψk + 1) =Rk(sin ψk + 2^{-k} x cos ψk)

where
Rk = 1/ sqrt((1+2^{-2k}))

Thus, the values of sin ϑ and cos ϑ are obtained by
repeatedly executing the above operation so that ψk gradually approach ϑ.
This process will be called a ``pseudo-multiplication".

The final sin (ψk) and cos (ψk) is multiplied by K, and therefore,
it is necessary to correct them.

Now, explanation will be made on the algorithm of the CORDIC.

(1) It is initialized to x&sub0; = 1/K, y&sub0; = 0, v&sub0; = ϑ (0 ≦
ϑ < π/2). Here, K is a constant which fulfils the equation (10).

(2) The following step (3) is repeated for k = 0, 1, 2, . . . . . , (n-1).

(3) If vk ≧ 0, it is assumed that ak = +1, and

if vk < 0, it is assumed that ak = -1,
xk + 1 = xk - ak x 2^{-k} x yk yk + 1 = yk + ak x 2^{-k} x xk vk + 1 = vk - ak x rk
where rk is a constant fulfilling the equation (3))

(4) cos ϑ =xn and sin ϑ =yn can be simultaneously obtained.

Referring to Figure 1, there is shown one example of a pipeline arithmetic
processor embodying the algorithm of the CORDIC. The shown processor comprises
a cascaded operational units 41, 42, . . . . . , 49 which have the same construction,
and constructs n stages of pipeline.

The operational unit 41 has n-bit registers 411, 412 and 413 which
respectively store three kinds of variables xk, yk and vk in a binary notation.
A pair of shifters 414 and 415 are connected to outputs of the registers 412 and
411, respectively. These shifters function to rightwardly shift the received data
of n-bits by k bits. In addition, there is provided a constant generator 416 for
generating a n-bit constant rk defined in the above mentioned equation (3). The
outputs of the three registers 411, 412 and 413 and the outputs of the shifters
414 and 415 and the constant generator 416 are applied to three n-bit adder/subtracters
417, 418 and 419 , as shown.

In the shown processor, the operational units 41, 42, . . . . . ,
49 execute the operation the above mentioned algorithm step (3) for k= 0, 1, .
. . . . , (n-1).

Thus, in a first step [A], 1/K, 0 and ϑ are set as initial
values to the registers 411, 412 and 413.

In a second step [B], the variable is made to k=0 in the operational
unit 41. Therefore, the variable xk of the equation (11) is stored in the register
411, the variable yk of the equation (12) is stored in the register 412, and the
variable vk of the equation (13) is stored in the register 413.

The shifters 414 and 415 operate to rightwardly shift the output
data from the registers 412 and 411 by k bits. namely, the output data from the
register 412 and 411 are respectively multiplied by 2^{-k}. At this time,
if the sign bit of the register 413 is positive, ak=+1, and therefore, the adder/subtracters
417 and 419 are controlled to execute the subtraction, and the adder/subtracter
418 is controlled to execute the addition. On the other hand, if the sign bit
of the register 413 is negative, since ak=-1, the adder/subtracters 417 and 419
are controlled to execute the addition, and the adder/subtracter 418 is controlled
to execute the subtraction.

Thus, the outputs of the three adder/subtracters 417, 418 and 419
are outputted as the variables (xk + 1), (yk + 1) and (vk + 1) to three registers
421, 422 and 423 of the next stage operational unit 42 which respectively correspond
to the registers 411, 412 and 413 of the first stage operational unit 41.

Thereafter, in a third step [C], the above mentioned operation (B)
are sequentially executed for k = 1, 2, , . . . . . , (n-1) in the operational
units 42, . . . . . , 49.

In a fourth step [D], the final stage operational unit 49 respectively
outputs xn = cos ϑ and yn = sin ϑ from adder/subtracters (not shown)
corresponding to the adder/subtracters 417 and 418 of the first stage operational
unit 41.

If an angle ϑ is inputted to the register 413 for each clock,
the values of cos ϑ and sin ϑ are outputted from the final stage
operational unit 49 for every clock. But, assuming that the operation of each of
the operational units 41 to 49 needs one clock and the stage number of the operational
units 41 to 49 is "n", n clocks are required from the input of the angle ϑ
to the output of the values of cos ϑ and sin ϑ.

The above mentioned trigonometric function arithmetic processor is
disadvantageous in the followings:

First, the conventional trigonometric function arithmetic processor
requires a large amount of hardware. For example, the above mentioned trigonometric
function arithmetic processor needs 2n shifters which can shift data of n-bits
by k bits and 3n adder/subtracters. If these circuit elements are assembled on
an large scale integrated circuit, since the shifter having a large shift bit number
requires a large area, the trigonometric function arithmetic processor will be
inevitably of a large size.

Particularly, in order to realize the operation at a high degree
of precision, an area for barrel shifters and adder/subtracters is significantly
increased. For example, in order to obtain the precision of 32 bits in binary
notation, there are required 96 adder/subtracters of 32 bits and a pair of 32-bit
shifters which can rightwardly shift by 0, 1, 2, . . . . . , 31 bits, respectively(
64 in total).

Secondly, the conventional trigonometric function arithmetic processor
can obtain a sufficient degree of precision in the result of the operation. The
larger the value "k" is, the value "rk" in the equation (6) will become small,
and therefore, the digit number of the significant figures will be decreased. As
a result, an rounding error is accumulated at the LSB of the data.

Summary of the Invention

Accordingly, it is an object of the present invention to provide
an trigonometric function arithmetic processor which has overcome the above mentioned
defect of the conventional one.

Another object of the present invention is to provide a trigonometric
function arithmetic processor which can be constructed of a relatively small number
of circuit elements and which can have a high precision in the result of the operation.

Still another object of the present invention is to provide a trigonometric
function arithmetic processor which can be constructed of unitary operational units
composed of one barrel shifter and two adder/subtracters and which can output
an operation result of a high precision at a speed comparable with that of the
conventional trigonometric function arithmetic processor.

The above and other objects of the present invention are achieved
in accordance with the present invention by a trigonometric function arithmetic
processor for use in computers for computing the value of at least trigonometric
function sin ϑ and cos ϑ, comprising:

a first arithmetic unit for executing, in m steps, a pseudo-division
operation for obtaining from an initial value ϑ a sequence of numbers {ak}
and a pseudo-remainder ε which fulfil the following equation

where ak = +1 or -1, and

a second arithmetic unit for executing the following pseudo-multiplication
operation in m steps from initial values Xm = P and Ym = ε x P (where P =
constant) and the sequence of numbers {ak}, for k = m-1, m-2, ..... 1 and 0,
Xk - 1 = Xk - ak x 2^{-2k} x Yk Yk - 1 = (Yk + ak x Xk)/2^{k}

so that X0 = Q x cos ϑ and Y&sub0; = Q x sin ϑ (Q =
constant) are simultaneously obtained.

In a preferred embodiment, the first arithmetic unit includes a first
memory, a first constant generator for generating a constant 2^{k} x arctan
(2^{-k}) or arctan (2^{-k}) (where k = 0, 1, ....., . m-1) and
a first adder/subtracter means for selectively executing addition or subtraction
between the content of the first memory and the just above mentioned constant.
On the other hand, the second arithmetic unit includes second and third memories,
a shifter for rightwardly shifting the content of the third memory by 2k digits
(where k = m-1, m-2, ..... 1 and 0), a second adder/subtracter means for selectively
executing addition or subtraction between the content of the second memory and
the output of the shifter, and a third adder/subtracter means for selectively
executing addition or subtraction between the content of the second memory and
the content of the third memory.

The above mentioned trigonometric function arithmetic processor operates
in the following principle: The basic algorithm of the present trigonometric function
arithmetic processor is similar to CORDIC, but not completely identical. Therefore,
the algorithm of the present trigonometric function arithmetic processor can be
called a modification of CORDIC. In the CORDIC process, the pseudo-division and
the pseudo-multiplication are simultaneously executed. However, in the present
invention, the pseudo-division is first executed, and then, the pseudo-multiplication
is executed.

In the CORDIC process, the pseudo-multiplication has been executed
by ignoring the value ε in the equation (2) and by initializing to x&sub0;
= 1/K, y&sub0; = 0. Therefore, n steps of operations have been needed for obtaining
the degree of precision of n bits in binary notation. However, since ε <
2^{n} in the equation (2), if the degree of precision of 2n bits in a
binary notation is required, approximations sin ε ≅ ε and cos ε
≅ 1 can be obtained from the equation (1). This is utilized in the present
invention. In addition, the pseudo-division process is stopped at m steps (m =
n/2) and then the pseudo-multiplication process is executed with the initial values
of x&sub0; = 1/K, y&sub0; = vm/K. As a result, the total number of steps including
the pseudo-division process and the pseudo-multiplication process is made equal
to that of the CORDIC process.

In order to utilize the remainder Vm of the pseudo-division as the
initial value of the pseudo-multiplication with a high degree of precision, the
pseudo-division is executed by shifting the data to a lower place by one digit
for each increment of steps, in the sequence opposite to that of the CORDIC. Therefore,
the equations (11) and (12) of the CORDIC algorithm is modified to:
xk - 1 = xk + ak x 2^{-k} x yk yk - 1 = yk - ak x 2^{-k} x xk

Further, with substitution of
Xk = xk and Yk = 2^{-k} x yk,

these equations are also modified to:
Xk - 1 = Xk + ak x 2^{-2k} x Yk Yk - 1 = (Yk + ak x Xk)/2^{k}

When the value of k is large, the value of yk is small, and therefore,
the substitution of (17) is very effective in preventing the accumulation of rounding
errors. In addition, since the equation (19) does not require the shift of a large
digit number so that the required number of large digit number shifts.

The trigonometric function arithmetic processor in accordance with
the present invention and based on the above mentioned principle operates as follows
in the case that the result of operation has the degree of precision of n digits
(n=2m) in the binary notation.

(1) An angle ϑ (0 ≦ ϑ < π/2) is inputted.

(2) The following step (3) is repeated for k = 0, 1, 2, ..... , (m-1).

(3) If vk ≧ 0, it is assumed that ak = +1 and

if vk < 0, it is assumed that ak = -1,
Vk + 1 = 2(Vk - ak x Γk)
where
Γk = 2^{k} x arctan (2^{-k})

(4)
Xm=(1/K) and Ym=Vm x (1/K/2)
are set as the initial values, where 1/K is a constant fulfilling
the equation (10)

(5) The following step (6) is repeated for k = m, m-1, ..... , 2, 1, 0

(6)
Xk - 1 = Xk -(ak x 2&supmin;² x Yk) yk - 1 = (Yk + ak x Xk)/2²
cos ϑ =xn and sin ϑ =yn can be simultaneously obtained.

(7) cos ϑ = X&sub0; and sin ϑ =2 x Y&sub0; are simultaneously
obtained.

However, if only the ration of sin ϑ to cos ϑ should
be obtained, the step (4) may be executing by putting
Xm = 1 or 0 and Ym = Vm/2

Therefore, the multiplication is not necessary.

The above and other objects, features and advantages of the present
invention will be apparent from the following description of preferred embodiments
of the invention with reference to the accompanying drawings.

Brief Description of the Drawings

Figure 1 a block diagram of one typical example of the conventional trigonometric
function arithmetic processor;

Figure 2 a block diagram of one embodiment of the trigonometric function arithmetic
processor in accordance with the present invention;

Figure 3 a block diagram of another embodiment of the trigonometric function
arithmetic processor in accordance with the present invention; and

Figure 4 a block diagram of still another embodiment of the trigonometric function
arithmetic processor in accordance with the present invention.

Description of the Preferred embodiments

Referring to Figure 2, there is shown a block diagram of a first
embodiment of the trigonometric function arithmetic processor in accordance with
the present invention for computing the trigonometric functions sin ϑ and
cos ϑ.

The shown processor comprises a pair of data buses 101 and 102 and
a pair of registers 111 and 121 coupled to the data bus 101 for storing two kinds
of variables X and Y, respectively. Further, the processor includes a pair of
adder/subtracters 112 and 122 having a pair of inputs A and B and C and D respectively
coupled to the data buses 101 and 102 for executing the addition/subtraction of
the equations (18), (19) and (20). One input B of the adder/subtracter 112 coupled
to the data bus 102 is also coupled to receive an output of a barrel shifter 113
which rightwardly shifts the content of the register 121 by any selected even
number bits. An output of the adder/subtracter 112 is connected to the register
111 directly and through a shifter 114 for doubling the output of the adder/subtracter
112. An output of the register 111 is coupled to the data bus 102 so that the content
of the register is inputted to the one inputs A and C of the adder/subtracters
112 and 122. An output of the adder/subtracter 122 is coupled to another shifter
124 which halves the output of the adder/subtracter 122 and outputs the halved
data to the register 121.

To the data bus 101 is connected a ROM 104 storing the constant Γk
and the constant 1/K fulfilling the equation (10). This ROM 104 has a capacity
of (2m+1) words. In addition, an exponent part processing unit 105 is coupled
to the data bus 101. This exponent part processing unit 105 controls the amount
of shift of the barrel shifter 113 and the an address of the ROM 104, and also,
calculates the arithmetic operation of the exponent part. A stack 106 is coupled
to a sign part of the register 111 so as to store the sequence of numbers {ak}
in the first-in first-out manner. A multiplication circuit 107 is coupled to the
bus 101 so as to receive a multiplier and a multiplicand from the bus 101 and
outputs the result of the multiplication to the bus 101.

Now, operation of the above mentioned trigonometric function arithmetic
processor will be described with reference to the arithmetic algorithm of the present
invention.

(1) The value of ϑ =2&supmin;¹ x Θ (1≦ Θ <2, i=integer)
expressed in a binary floating point representation is inputted from the bus 101
and the complement of the exponent part is inputted to the exponent part arithmetic
processing unit 105.

(2) The mantissa part Θ of ϑ is inputted to the register 111.

(3), The following operation (4) is repeated while incrementing the output
value of the exponent part arithmetic processing unit 105 in the order of i, i+1,
i+2, . . . . . , m-1.

(4) The value Vk of the register 111 is transferred through the bus 102 to
the input A of the adder/subtracter 112, and at the same time the constant Γk
is transferred from the ROM 104 through the bus 101 to the input B of the adder/subtracter
112. Further, the value of the sign bit of the register 111 is simultaneously
inputted or pushed to the stack 106. If the sign bit of the register 111 indicates
the positive, the adder/subtracter 112 will subtract the input B from the input
A. On the other hand, if the sign bit of the register 111 indicates the negative,
the adder/subtracter 112 will add the input B to the input A. The result of the
arithmetic operation is outputted to the shifter 114 and the data doubled by the
shifter 114 is written into the register 111.

(5) The value of Vm is read out from the register 111 through the bus 101 and
is transferred to the register 121 and the multiplication circuit 107. In addition,
the constant 1/K is supplied from the ROM 104 to the multiplication circuit 107,
so that the result Vm/K of the multiplication is outputted through the bus 101
to the register 111.

(6) The following operation (7) is repeated while decrementing the output value
of the exponent part arithmetic processing unit 105 in the order of m, m-1, m-2,
. . . . . , i+1.

(7) The value Xk of the register 111 is transferred through the bus 102 to
the input A of the adder/subtracter 112 and the input C of the adder/subtracter
122, and at the same time, the value Yk is transferred from the register 121 through
the bus 101 to the input D of the adder/subtracter 122. Furthermore, the content
Yk of the register 121 is rightwardly shifted in the barrel shifter 113 by the
digit number corresponding to the doubled value of the content of the exponent
part arithmetic processing unit 105 (multiplication of 2^{-2k}), and the
output of the barrel shifter thus obtained is inputted to the input B of the adder/subtracter
112. If the sign bit popped out from stack 106 indicates the positive, the adder/subtracter
112 will subtract the input B from the input A. On the other hand, if it is negative,
the adder/subtracter 112 will add the input B to the input A. The result of the
arithmetic operation is written into the register 111. At the same time, if the
sign bit popped out from stack 106 indicates the positive, the adder/subtracter
122 will add the input D to the input C. On the other hand, if the popped out sign
bit is negative, the adder/subtracter 122 will subtract the input C from the input
D. The result of the arithmetic operation is outputted to the shifter 124 and the
data halved by the shifter 124 is written into the register 121.

(8) Thus, the cos ϑ is obtained in the register 111 and the mantissa
of sin ϑ is obtained in the register 121. The exponent part of sin ϑ
is the same of the value ϑ.

Now, assuming that the operation of the steps (4) and (7) executed
with only one clock and the multiplication of the step (5) is executed with α
clocks, a total processing time needs about (2m+α) = (n+α). Namely,
the operation is delayed than that of the CORDIC by the processing time of the
multiplication circuit.

As seen from the above, the above mentioned processor can compute
cos ϑ and sin ϑ at a high speed and at high precision by using one
barrel shifter and two adder/subtracters.

The above mentioned processor have processed the floating point data,
but can a fixed point data in the following steps:

(1) Vi = ϑ (0 ≦ ϑ < π/4) is inputted as an initial data.

(2) The variable "i" is set to i=0.

(3) to (7) The same operation as that in the above mentioned case of the floating
point representation.

(8) cos ϑ = Xi and sin ϑ = Yi are simultaneously obtained.

Turning to Figure 3, there is shown a block diagram of another embodiment
of the trigonometric function arithmetic processor in accordance with the present
invention.

The shown processor includes arithmetic operational units 51, 52,
. . . . , 59 which form a m-stage pseudo-division pipeline processor, an arithmetic
operational unit 61 for computing an initial value for a pseudo-multiplication
and arithmetic operational units 71, 72, . . . . , 79 which form a m-stage pseudo-multiplication
pipeline processor.

The arithmetic operational units 51, 52, . . . . , 59 have the same
structure of hardware but are different in the variable "k" held therein. Namely,
the arithmetic operational units 51, 52, . . . . , 59 retain, as the variable
"k", 0, 1, . . . . , m-1, respectively. The arithmetic operational unit 51 comprises
a n-bit register 511 for storing the variable Vk and a constant generator 512
for generating the constant Γk of n bits. The register 511 and the constant
generator 512 is coupled to a pair of inputs of an adder/subtracter 513 of n bits,
whose output is connected to a n-bit shifter 514 for leftwardly shifting the received
data by one bit. An output of the shifter 514 is connected to a register 521 of
the next arithmetic operational unit 52. Further, a k-bit register 518 is provided
to receive a sequence of numbers {a0, a1, . . . . , ak-2, ak-1}, and connected
to a register 528 of the next arithmetic operational unit 52. In addition, an
sign part of the register 511 is connected as a control input to the adder/subtracter
513 and also is connected to the register 528 of the next arithmetic operational
unit 52.

The arithmetic operational unit 61 comprises a n-bit register 611
for storing the variable Vm from the arithmetic operational unit 59 and a constant
generator 512 for generating the constant 1/K of n bits which fulfils the equation
(10). The register 611 and the constant generator 612 is coupled to a pair of inputs
of a multiplication circuit 613 of n bits, which multiplies the content of the
register 611 by the constant of the generator 612 and outputs a halved data of
the result of the multiplication. Further, there is provided a (m+1)-bit register
618 for storing a sequence of numbers {a0, a1, . . . . , am}.

The arithmetic operational units 71, 72, . . . . , 79 have the same
structure of hardware but are different in the variable "k" held therein. Namely,
the arithmetic operational units 71, 72, . . . . , 79 retain, as the variable
"k", m-1, m-2, . . . . , 0, respectively. The arithmetic operational unit 71 comprises
a pair of n-bit registers 711 and 712 for storing the variables Xk and Yk. The
register 712 is coupled to a n-bit shifter 713 for rightwardly shift the received
data by 2k bits. An output of the shifter 713 and an output of the register 711
are coupled to a pair of inputs of an n-bit adder/subtracter 714, respectively.
Further, the outputs of the registers 711 and 712 are coupled to a pair of inputs
of an n-bit adder/subtracter 715, respectively. An output of the adder/subtracter
715 is coupled to a n-bit shifter 716 for rightwardly the received data by one
bit . In addition, a (k+1)-bit register 718 is provided to receive a sequence of
numbers {a0, a1, . . . . , ak-2, ak-1}.

The processor shown in Figure 3 will operate as follows on the basis
of the arithmetic algorithm of the present invention:

(1) The value of ϑ (ϑ < π/2) expressed in a binary fixed
point representation is inputted

(2) In the arithmetic operational unit 51, the variable k is set as k=0. If
the sign of value Vk in the register 511 is positive, the adder/subtracter 513
is controlled to subtract the constant Γk of the generator 512 from the
content of the register 511. If the sign of value Vk is negative, the adder/subtracter
513 is controlled to add the constant Γk of the generator 512 to the content
of the register 511. The shifter 514 operates to double the output of the adder/subtracter
513 and outputs the doubled data to the register 521 of the next arithmetic operational
unit 62. On the other hand, the register 518 stores the sequence of numbers {a0,
a1, . . . . , ak-2, ak-1}, and and receives the sign bit of the register 511 as
the value "ak". Therefore, the register 518 outputs the sequence of numbers {a0,
a1, . . . . , ak-2, ak-1, ak} to the register 528 of the next stage.

(3) The same operation as the step (2) is sequentially executed in the arithmetic
operational units, 52, . . . . , 59 in the named order by putting the variable
"k" as k = 1, 2, . . . . , m-1. An output of the arithmetic operational unit 59
is outputted to the arithmetic operational unit 61.

(4) In the arithmetic operational unit 61, the value Vm held in the register
611 is multiplied by the constant 1/K outputted from the generator 612 so that
the value Ym of the equation (22) is generated. The respective outputs of the
register 618, the constant generator 612 and the multiplication circuit 613 are
supplied to the registers 718, 711 and 712.

(5) In the arithmetic operational unit 71, the variable "k" is set to k = m-1.

The value Yk of the register 712 is rightwardly shifted by k bits
in the shifter 713, namely multiplied by 2^{-2k}. Then, the value "ak"
is extracted from the sequence of numbers {a0, a1, . . . . , ak-2, ak-1, ak} held
in the register 718. If "ak" is positive, the adder/subtracter 714 is controlled
to subtract the output of the shifter 713 from the content of the register 711,
and the adder/subtracter 715 is controlled to add the output of the register 711
to the output of the register 712. If "ak" is negative, the adder/subtracter 714
is controlled to add the output of the shifter 713 to the content of the register
711, and the adder/subtracter 715 is controlled to subtract the output of the
register 711 from the output of the register 712. The shifter 716 operates to halve
the output of the adder/subtracter 715. Thus, the sequence of numbers {a0, a1,
. . . . , ak-2, ak-1} held in the register 718 and the outputs of the adder/subtracter
714 and the shifter 716 are supplied to the registers of the next stage arithmetic
operational unit 72.

(6) The same operation as the step (5) is sequentially executed in the arithmetic
operational units, 72, . . . . , 79 in the named order by putting the variable
"k" as k = m-2, m-3, . . . . , 0.

(7) Thus, an adder/subtracter 794 of the last stage arithmetic operational
unit 79 outputs cos ϑ , and at the same time, an adder/subtracter 795 of
the last stage arithmetic operational unit 79 outputs sin ϑ.

Assuming that the angle ϑ is inputted for every clock, cos
ϑ and sin ϑ are outputted from the adder/subtracters 794 and 795
of the last stage arithmetic operational unit 79, respectively, for every clock.
Therefore, assuming that each of the arithmetic operational units 51, 52, . . .
. , 59, 61, 71, 72, . . . . , 79 executes its operation for one clock, the time
from the moment the angle ϑ is inputted to the moment cos ϑ and sin
ϑ are outputted will need a time corresponding (n+1) clocks.

Referring to Figure 4, there is shown a block diagram of still another
embodiment of the trigonometric function arithmetic processor in accordance with
the present invention. This processor is based on the equation (23), not the equation
(22), and therefore, there are outputted K x sin ϑ and K x cos ϑ,
where K is a constant fulfilling the equation (10). In addition, this processor
can be said to a modification of the processor shown in Figure 3, and therefore,
elements similar to those shown in Figure 3 are given the same Reference Numerals,
and a detailed explanation thereof will be omitted.

Similarly to the processor shown in Figure 3, the processor shown
in Figure 4 includes the arithmetic operational units 51, 52, . . . . , 59 for
the m-stage pseudo-division, and the arithmetic operational units 71, 72, . .
. . , 79 for the m-stage pseudo-multiplication. But, in place of the arithmetic
operational unit 61 for computing an initial value for a pseudo-multiplication,
there are provided a shifter 821 for rightwardly shifting the output of the shifter
594 by one bit and outputting the one-bit shifted data to the register 712 and
a constant generator 822 for outputting a constant "1" or "0" to the register
311.

If the angle ϑ is inputted to the register 711 for every clock,
K x sin ϑ and K x cos ϑ are outputted from the adder/subtracters
794 and 795 of the last stage arithmetic operational unit 79, respectively, for
every clock. Therefore, assuming that each of the arithmetic operational units
51, 52, , . . . . , 61, 71, 72, . . . . , 79 executes its operation for one clock,
the time from the moment the angle ϑ is inputted to the moment K x sin ϑ
and K x cos ϑ are outputted will need a time corresponding "n" clocks.

Particularly, the embodiment shown in Figure 4 can be assembled of
a smaller amount of hardware than that required in the embodiment shown in Figure
3 by an amount corresponding to the multiplication circuit.

The preferred embodiments of the trigonometric function arithmetic
processor in accordance with the present invention thus described have the following
advantages:

First, the trigonometric function arithmetic processor in accordance
with the present invention can be constructed of a reduced amount of hardware.
Particularly, the embodiment shown in Figure 2 is composed of one barrel shifter
and two adder/subtracters, which is reduced in the amount of hardware by one barrel
shifter and one adder/subtracter as compared with the conventional one. The elements
newly added as compared with the conventional one are the stack and the multiplication
circuit. The stack can be formed of a m-bit shift register, and the multiplication
circuit can be realized by adding a simple circuit to one of the adder/subtracters
provided in the embodiment of Figure 2. The amount of hardware increased by these
elements is smaller than the decreased amount of hardware.

In addition, in the case that the trigonometric function arithmetic
processor is composed as a general purpose floating point arithmetic operation
units, the two barrel shifters and the three adder/subtracters used in the conventional
one have no use other than to computation of trigonometric functions and reverse
trigonometric functions.

Turning to the embodiment shown in Figure 3, the trigonometric function
arithmetic processor is composed of (n/2) n-bit shifter having the shift amount
of 2k bits, (3n/2) n-bit adder/subtracters and one n-bit multiplication circuit
capable of multiplying n-bit data by n-bit data. The n-bit multiplication circuit
can be formed by (n/2) adder/subtracters of n bits in accordance with Booth's
algorithm. Therefore, this embodiment can be composed of 2n adder/subtracters.

For example, in order to the degree of precision of 32 digits in
the binary notation, this embodiment can be composed of 64 adder/subtracters of
32 bits and 16 shifters of 32 bits which give a rightward shift of 30 bits, 28
bits, . . . . , 0 bit, respectively. Namely, the required amount of shift is doubled,
but the number of the required shifters is reduced to 1/4. Further, the number
of adder/subtracters is reduced to 2/3.

In addition, the trigonometric function arithmetic processor in accordance
with the present invention can give the result of arithmetic operation with a high
degree of precision. The algorithm of the present invention will execute the operation
while adjusting the digits of the data so as to have a maximum significant figures.
Therefore, a high degree of precision can be obtained. Moreover, in the case of
ϑ, sin ϑ and cos ϑ in the floating point representation, even
if the value of ϑ is very small, the significant figures are not decreased,
and since the rounding errors are not accumulated, the result of the operation
will have a high degree of precision.

The invention has thus been shown and described with reference to
the specific embodiments. However, it should be noted that the present invention
is in no way limited to the details of the illustrated structures but changes
and modifications may be made within the scope of the appended claims.

Anspruch[de]

Arithmetischer Prozessor für trigonometrische Funktionen für die Benutzung
in Computern zum Berechnen des Wertes mindestens der trigonometrischen Funktionen
Sinus ϑ und Kosinus ϑ mit:

einer ersten arithmetischen Einheit (112) für die Durchführung einer Pseudodivisionsoperation
in m-Schritten, um aus einem Initialwert ϑ eine Sequenz von Nummern {ak}
und einen Pseudorest ε zu erhalten, welche die folgende Gleichung erfüllen
wobei ak = +1 oder -1 ist, und

einer zweiten arithmetischen Einheit (122) zum Durchführung der folgenden Pseudomuliplikationsoperation
in m-Schritten aus Anfangswerten Xm = P und Ym = ε x P (wobei P = konstant)
und der Sequenz von Nummern {ak} für k = m-1, m-2, ... 1 und 0,
Xk - 1 = Xk - ak x 2^{-2k} x Yk Yk - 1 = (Yk + ak x Xk)/2^{k}
so daß simultan X0 = Q x Kosinus ϑ und Y0 = Q x Sinus ϑ (Q = konstant)
erhalten werden.

Arithmetischer Prozessor nach Anspruch 1, wobei die erste arithmetische Einheit
einen ersten Speicher (111), einen ersten Konstanten-Generator (104) zum Erzeugen
einer Konstante 2^{k} x Arctan (2^{-k}) oder Arctan (2^{-k})
(wobei k = 0, 1, ..., m-1 ist) und eine erste Addier/Subtrahiervorrichtung (112)
aufweist zum selektiven Durchführen einer Addition und Subtraktion zwischen dem
Inhalt des ersten Speichers und der oben erwähnten Konstante.

Arithmetischer Prozessor nach Anspruch 2, wobei die zweite arithmetische Einheit
zweite und dritte Speicher (711, 712), einen Schieber (713) zum Rechtsschieben
des Inhalts des dritten Speichers um 2k Bits (wobei k = m-1, m-2, ... 1 und 0
ist), eine zweite Addier/Subtrahiervorrichtung (714) zum wahlweisen Durchführen
einer Addition oder Subtraktion zwischen den Inhalten des zweiten Speichers (711)
und dem Ausgang des Schiebers, und eine dritte Addier/Subtrahiervorrichtung (715)
aufweist zum wahlweisen Durchführen einer Addition oder Subtraktion zwischem dem
Inhalt des zweiten Speichers (711) und dem Inhalt des dritten Speichers (712).

Anspruch[en]

A trigonometric function arithmetic processor for use in computers for computing
the value of at least trigonometric function sin ϑ and cos ϑ, comprising:

a first arithmetic unit (112) for executing, in m steps, a
pseudo-division operation for obtaining from an initial value ϑ a sequence
of numbers {ak} and a pseudo-remainder ε which fulfil the following equation
where ak = +1 or -1, and

a second arithmetic unit (122) for executing the following
pseudo-multiplication operation in m steps from initial values Xm = P and Ym =
ε x P (where P = constant) and the sequence of numbers {ak}, for k = m-1,
m-2, ..... 1 and 0,
Xk - 1 = Xk - ak x 2^{-2k} x Yk Yk - 1 = (Yk + ak x Xk)/2^{k}
so that X0 = Q x cos ϑ and Y0 = Q x sin ϑ (Q = constant) are simultaneously
obtained.

A trigonometric function arithmetic processor claimed in Claim 1 wherein the
first arithmetic unit includes a first memory (111), a first constant generator
(104) for generating a constant 2^{k} x arctan (2^{-k}) or arctan
(2^{-k}) (where k = 0, 1, ....., m-1) and a first adder/subtracter means
(112) for selectively executing addition or subtraction between the content of
the first memory and the just above mentioned constant.

A trigonometric function arithmetic processor claimed in Claim 2 wherein the
second arithmetic unit includes second and third memories (711,712), a shifter
(713) for rightwardly shifting the content of the third memory by 2k digits (where
k = m-1, m-2, ..... 1 and 0), a second adder/subtracter means (714) for selectively
executing addition or subtraction between the content of the second memory (711)
and the output of the shifter, and a third adder/subtracter means (715) for selectively
executing addition or subtraction between the content of the second memory (711)
and the content of the third memory (712).

Anspruch[fr]

Processeur arithmétique de fonctions trigonométriques destiné à être utilisé
dans des calculateurs pour calculer la valeur au moins des fonctions trigonométriques
sin ϑ et cos ϑ, comprenant :

- une première unité arithmétique (112) pour exécuter, en
m étapes, une opération de pseudo-division pour obtenir, à partir d'une valeur
initiale ϑ, une suite de nombres {a_{k}} et un pseudo-reste ε
qui satisfont à l'équation suivante :
où a_{k} = +1 ou -1, et

- une deuxième unité arithmétique (122) pour exécuter l'opération
suivante de pseudo-multiplication en m étapes, à partir des valeurs initiales X_{m}
= P et Y_{m} = ε &peseta; P (où P = constante), et de la suite de
nombres {a_{k}}, pour k = m-1, m-2, ..., 1 et 0,
X_{k-1} = X_{k} - a_{k} &peseta; 2^{-2k} &peseta;
Y_{k}Y_{k-1} = (Y_{k} + a_{k} &peseta; X_{k})/2^{k}
de telle sorte que X&sub0; = Q &peseta; cos ϑ et Y&sub0; = Q &peseta; sin
ϑ (Q = constante) sont obtenus simultanément.

Processeur arithmétique de fonctions trigonométriques selon la revendication
1, dans lequel la première unité arithmétique comporte une première mémoire (111),
un premier générateur de constante (104) pour générer une constante 2^{k}
&peseta; arctan (2^{-k}) ou arctan (2^{-k}) (où k = 0, 1, ..., m-1)
et des premiers moyens d'addition/soustraction (112) pour exécuter sélectivement
une addition ou une soustraction entre le contenu de la première mémoire et la
constante mentionnée juste ci-dessus.

Processeur arithmétique de fonctions trigonométriques selon la revendication
2, dans lequel la deuxième unité arithmétique comporte une deuxième et une troisième
mémoires (711, 712), un registre à décalage (713) pour décaler de 2K bits (où
k = m-1, m-2, ..., 1 et 0) vers la droite le contenu de la troisième mémoire, des
deuxièmes moyens d'addition/ soustraction (714) pour exécuter sélectivement une
addition ou une soustraction entre le contenu de la deuxième mémoire (711) et
la sortie du registre à décalage, et des troisièmes moyens d'addition/soustraction
(715) pour exécuter sélectivement une addition ou une soustraction entre le contenu
de la deuxième mémoire (711) et le contenu de la troisième mémoire (712).