This invention generally relates to integrated circuit devices and
more particularly to multivalued logic circuits comprising resonant tunneling devices.
BACKGROUND OF THE INVENTION
Without limiting the scope of the invention, its background is described
in connection with resonant tunneling devices and methods for implementing multivalued
Resonant Tunneling Devices
Within the last decade, heteroepitaxial technology has allowed researchers
to explore the electrical properties of a variety of superlattice, quantum well,
and resonant tunneling structures. The first proposals and investigations of the
resonant tunneling diode were reported by Chang, Esaki, and Tsu (Applied Physics
Letters, 24, p. 592) and subsequently given impetus by Sollner et al. (Applied
Physics Letters, 43, p.588) who observed large negative differential resistance
(hereinafter referred to as NDR) in these structures. Because only discrete energy
states are available for charge transport through quantum wells, the current-voltage
relationship of a resonant tunneling diode may exhibit a peak, i.e., for applied
voltages increasing from zero, the diode current increases, then decreases for a
range of larger applied voltages. Multiple peak resonant tunneling devices (hereinafter
referred to as M-RTD) consisting of series combinations of RTDs in epitaxial stacks
have also been demonstrated. Fifteen resonant peaks were achieved in a single heterostructure
at room temperature recently fabricated at Texas Instruments.
Since the initial investigations of the RTD, many three-terminal resonant
tunneling devices have been proposed and demonstrated (see, for example, F. Capasso,
S. Sen and F. Beltram, High Speed Semiconductor Devices (S.M. Sze, ed.),
p. 465, John Wiley & Sons, New York). Integration of RTDs into one or another
of the terminals of conventional transistors has led to a large family of resonant
tunneling transistors. Among the most promising of these transistors are: the resonant
tunneling bipolar transistor (RTBT) (see, for example, F. Capasso, S. Sen, and A.Y.
Cho, Applied Physics Letters, 51, p. 526); the resonant tunneling hot electron
transistor (RHET) (see, for example, N. Yokoyama et al., Solid State Electronics,
31, p. 577); and the resonant tunneling field effect transistor (RTFET). These devices
are fabricated by placing RTDs in the emitter terminals of heterojunction bipolar
transistors, hot electron transistors or field effect transistors, respectively.
Nanoelectronic devices, such as resonant tunneling diodes and transistors,
are under investigation in many laboratories for their potential to operate at dimensions
much smaller than conventional transistors can function. The goal of these device
designs is to harness the quantum effects themselves to allow scaling to dimensions
on a nanometer scale. Examples of such nanoelectronic devices are described, for
U.S. Patent No. 4,581,621, "Quantum Device Output Switch",
issued April 8, 1986, to Reed;
U.S. Patent No. 4,704,622, "Negative Transconductance Device",
issued November 3, 1987, to Capasso et al.;
U.S. Patent No. 4,721,983, "Three Terminal Tunneling Device",
issued January 26, 1988, to Frazier;
U.S. Patent No. 4,849,799, "Resonant Tunneling Transistor",
issued July 18, 1989, to Capasso et al.;
U.S. Patent No. 4,851,886, "Binary Superlattice Tunneling Device
and Method", issued July 25, 1989, to Lee et al.;
U.S. Patent No. 4,853,753, "Resonant-Tunneling Device, and
Mode of Device Operation", issued August 1, 1989, to Capasso et al.;
U.S. Patent No. 4,912,531, "Three-Terminal Quantum Device",
issued March 27, 1990, to Reed et al.;
U.S. Patent No. 4,959,696, "Three Terminal Tunneling Device
and Method", issued September 25, 1990, to Frensley et al.; and
U.S. Patent No. 4,999,697, "Sequential-Quenching Resonant-Tunneling
Transistor", issued March 12, 1991, to Capasso et al.
Binary arithmetic integrated circuits (ICs) have enabled a revolution
in the performance of embedded coprocessors and high-performance computers, but
scaling limits will ultimately prevent further increases in the speed and density
of conventional ICs. Soon after the year 2000, quantum mechanical effects will set
fundamental limits on the scalability of conventional transistors (see, for example,
R.T. Bate, Nanotechnology, 1, p. 1, 1990). Feature sizes less than approximately
0.1 µm will cause leakage in conventional devices that will prevent scaling from
increasing IC performance.
In the future, ultra-high performance digital systems will require
clock rates in excess of 10 GHz with minimum data latency. Current systems, using
binary computation based on silicon VLSI technology, can achieve reasonably good
performance by using complex carry-ripple reduction schemes; however, data latency
and ultra-fast computing requirements will make this approach unsuitable for certain
classes of systems.
Multivalued Logic (hereinafter referred to as MVL) circuits have the
potential for increased speed and density (for the same minimum feature geometry)
since multiple binary bits may be simultaneously processed in a single MVL circuit.
For examples of multivalued logic adders and multipliers which offer ripple-carry
free operation through the use of redundant number systems, see, for example: L.
J. Micheel, Proceedings of the International Symposium on MVL, 1992; J. Goto
et al., International Solid State Circuits Conference, 1991; and M. Kameyama,
M. Nomura and T. Higuchi, Proceedings of the International Symposium on MVL,
1990. To date, implementation of these approaches has been proposed based on conventional
integrated circuit families (e.g. CMOS and heterojunction ECL).
SUMMARY OF THE INVENTION
It has been discovered that multiple resonant tunneling devices offer
significant advantages for realizing ultra-dense, ultra-high performance multivalued
logic arithmetic integrated circuits. Conventional technologies (e.g. CMOS and heterojunction
ECL) seem an unnatural choice for MVL ICs due to the complex circuits and high component
counts required. Resonant tunneling devices have novel characteristics that will
enable ultra-high speed and ultra-high density circuits even before the quantum
scaling limits are reached. Multivalued logic circuits implemented with resonant
tunneling devices will achieve increased speed and density over binary circuits
and multiple-valued circuits implemented in conventional IC technologies since multiple
binary bits are very efficiently processed by architectures which make use of devices
with multiple negative transconductance regions.
Generally, and in one form of the invention, an adder for calculating
the sum of two numbers represented by signed digit range-3 base-4 words is constructed
from summation circuits which add corresponding digits of each input word to form
digit sums, converter circuits which use multi-level folding circuits connected
by voltage dividers to decompose the digit sums into an interim sum and a carry
digit, and a second set of summation circuits which add interim sums and carry digits
to produce the digits of the result. Preferably, the sum is likewise represented
by a signed digit range-3 base-4 word. Preferably, the multi-level folding circuits
contain resonant tunneling transistors constructed from bipolar transistors and
multiple-peak resonant tunneling diodes.
The adder of the present invention provides several technical advantages
over prior art adders. For example, the novel adders described herein are faster
and denser than conventional adders. Ripple carries are eliminated by the preferred
embodiments described herein. The speed of the circuit is independent of input word
width. Other technical advantages will be readily apparent to one skilled in the
art from the following descriptions, figures and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set
forth in the appended claims. The invention itself, however, as well as other features
and advantages thereof, will be best understood by reference to the detailed description
which follows, read in conjunction with the accompanying drawings.
In the drawings:
FIGURE 1 is the block diagram of the preferred embodiment of a redundant signed
digit range-3 base-4 adder;
FIGURE 2 is a block diagram of the preferred embodiment of a signed range-5
to signed range-3 converter.
FIGURES 3A and 3B are schematics of the preferred embodiment of the interim
FIGURE 4 is a graph of the current-voltage characteristic of a typical resonant
FIGURES 5a - 5c are conduction band energy diagrams of a typical resonant tunneling
diode with increasing applied voltages.
FIGURE 6 is a graph of the current-voltage characteristic of an eight-peak resonant
FIGURE 7 is a schematic of a resonant tunneling multi-level folding circuit.
FIGURE 8 is the transfer function of the circuit of Figure 8.
FIGURE 9 shows the transfer functions of the intermediate values Mi
Ni versus Si when the control signal is high.
FIGURE 10 is a graph of the transfer function of the interim sum subcircuit
when the control signal is high.
FIGURE 11 shows the transfer functions of the intermediate values Mi
Ni versus Si when the control signal is low.
FIGURE 12 is a graph of the transfer function of the interim sum subcircuit
when the control signal is low.
FIGURE 13a-13b are is a schematics of the preferred embodiment of the carry
FIGURE 14 shows the transfer functions of the intermediate values Ki
Li versus Si when the control signal is low.
FIGURE 15 is a graph of the transfer function of the carry digit subcircuit
when the control signal is low.
FIGURE 16 shows the transfer functions of the intermediate values Ki
Li versus Si when the control signal is high.
FIGURE 17 is a graph of the transfer function of the carry digit subcircuit
when the control signal is high.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The advantages of multivalued logic arithmetic are illustrated in
the following example. In most conventional digital processors, number are represented
in a base-2 range-2 numeration system. That is, the unit value of each digit increases
in base-2 progression (1, 2, 4, 8, etc.), and each digit may take on one of only
two values (0 or 1). Conventional digital processor architectures can add pairs
of N-bit numbers in a single processor cycle. However, time delays occur during
binary addition because carry bits must propagate through the adder circuitry. Carry
propagation delays set an upper limit on processor performance. For example, adding
the following numbers in base-2 range-2 representation using simple binary arithmetic
requires the long-distance propagation of a carry bit across the entire addition
The carry propagation problem can be eliminated if data operands
are encoded and processed using a multivalued representation. This approach uses
a higher range to represent information so that ripple carries are never produced,
and carry propagation delays are eliminated. The numbers from the previous example
can be added without the need for carry generation when represented in base-2 range-3,
where each column of bits is separately added using numerical rather than binary
addition. The range-3 representation of the result makes carry ripple unnecessary:
It is important to note that, even though the range of the
result is higher, the base of the number system used to represent the result has
not changed. That is, the unit value of each digit position still increases in the
base-2 progression of 1, 2, 4, 8, and so on. The use of range-N numeration to encode
information in base-M progression is called redundant digit M,N coding. If the digits
may take on only positive values, then the numeration system is referred to as redundant
positive digit M,N coding. The numeration system of the example above is therefore
redundant positive digit 2,3 coding. A numeration system which allows positive and
negative digit values is referred to as redundant signed digit M,N coding.
It has been discovered that the scaling and speed advantages of the
redundant digit arithmetic concept described above can be realized very efficiently
by circuits which make use of multiple resonant tunneling devices.
The block diagram of the preferred embodiment of an adder of numbers
represented by redundant signed digit 4,3 coding is shown in Figure 1. Digits may
take on the values -2, -1, 0, 1 and 2 (i.e. signed range-3 numeration). The progression
of the numeration system is base-4. The block diagram of Figure 1 is for input words
of up to three digits in word width, although the technique may obviously be extended
to arbitrary word widths.
Signed redundant digit 4,3 coding is used to represent base-4 information
in a redundantly encoded (signed range-3) representation so that ripple carries
are never produced. This means that any output digit, e.g. R&sub2;, is completely
determined by the first four input digits of equal or lower significance, e.g. X&sub2;,
Y&sub2;, X&sub1; and Y&sub1;. Addition is performed in three steps:
Step 1: Si = Xi + Yi Step 2: 4Ci+1 + Wi = Si Step 3: Ri = Wi + Ci
where the base-10 value of the result is given by
n-1 Σ 4iRi i=0
where n is the number of digits in the output word.
With reference to Figure 1, Pairs of input digits (Xi,
Yi) are first summed using summation circuits 40 to produce outputs
digit sums Si=Xi + Yi (Step 1, above). Si
may take on states -4,-3, -2,-1, 0, 1, 2, 3 and 4 and is therefore signed range-5.
Each digit sum is then converted into a carry digit Ci+1, an interim-sum
Wi, and a control signal Ei+1 by a signed range-5 to signed
range-3 converter (hereinafter referred to as a SR5-SR3 converter) 42. The
SR5-SR3 converter performs the decomposition function of Step 2, above. Finally,
outputs from the adjoining SR5-SR3 converters are shared and summed by additional
summation circuits 40 to produce a signed range-3 output result (Step 3,
above). The control signal Ei+1 is used by the next more significant
converter and insures that the resulting digits are signed range-3. The adder shown
can be extended to compute the sum of two numbers of arbitrary word width. The speed
of the circuit is independent of the number of input digits because only local intermediate
results are shared within the circuit.
In the following discussion of the operation of the preferred circuit
embodiments, the inputs and outputs will be referred to as states rather than voltages.
The voltage corresponding to each state is a design choice and the correspondence
between voltage and state will be obvious to one of ordinary skill in the art. In
a particular circuit design, for example, each state might differ from the next
state by 0.3 volts. In the preferred embodiment of the adder, circuit voltages are
generally proportional to the states they represent. It is contemplated that in
some alternate embodiments the relationship between voltage and state need not be
strictly linear nor strictly proportional.
The function of the summation circuit 40 may be accomplished
by any circuit which produces an output signal which is proportional to the sum
of its inputs. Such circuits are well known in the art.
The block diagram of the preferred embodiment of the SR5-SR3 converter
is shown in Figure 2. The comparator 58 generates the control signal Ei+1,
which is an input to the next more-significant converter, by comparing the digit
sum Si with 0.5. If Si is greater than 0.5, Ei+1
= 1, otherwise Ei+1 = 0.
The interim sum subcircuit 60 has two inputs, Si
and Ei, the control signal from the next less-significant converter.
The interim sum subcircuit produces the output Wi. Figures 3A and 3B
are schematics of the preferred embodiment of the interim sum subcircuit
60. The circuit of Figure 3A produces intermediate signals Mi
and Ni, which depend on inputs Si and Ei. The circuit
of Figure 3B then produces Wi = Ni - Mi for Ei
high, or, when Ei
is low, Wi = Mi - Ni.
The operation of these circuits is explained and discussed hereinbelow.
A resonant tunneling device (RTD) is a device which exhibits negative
differential resistance due to resonant tunneling of charge carriers through one
or more quantum wells. As shown in Figure 4 and Figures 5a-5c, a peak in the I-V
curve of an RTD occurs when the applied bias aligns a quantum conduction state within
the device with the Fermi level in one electrical contact. Figures 5a, 5b and 5c
show the conduction band energy diagrams of the RTD under the applied voltages at
points A, B and C in Figure 4, respectively. The position of the I-V peak in bias
voltage is adjustable by controlling the heterostructure composition and layer thicknesses
used to fabricate the device. RTDs can be integrated in series to produce a multiple
peak RTD (M-RTD) with I-V characteristics such as the example I-V characteristic
shown in Figure 6. In this example, the eight-peak I-V characteristic was obtained
by fabricating a stack of RTDs within the same heterostructure. Again, both the
number and bias separation of peaks are controlled parameters in the fabrication
The operation of the interim sum subcircuit 60 can be explained
with reference to Figure 7, which shows a schematic of a portion of the interim
sum subcircuit. The preferred embodiment of the multi-level folding circuit
64 comprises a resonant tunneling transistor 54, a load resistor RL
between VCC and the collector, and an input voltage source VIN.
The preferred embodiment of the resonant tunneling transistor 54, as shown,
is the combination of a bipolar transistor and a multiple-peak resonant tunneling
diode integrated into the transistor emitter, or, alternatively, a discrete transistor
with an M-RTD or multiple single peak RTDs connected to the emitter. As the input
voltage VIN is increased from zero, the collector current begins to increase
and VOUT begins to decrease from VCC. VOUT
to decrease until the potential across the M-RTD 52 reaches the first peak
voltage. As the input voltage continues to increase, the M-RTD 52
restrict the current and VOUT increases. For further increases in VIN,
this cycle repeats and the input/output relation shown in Figure 8 results. The
circuit can be seen to produce an approximate 'square wave' transfer function. The
voltage excursion between levels is determined by the product of the load resistance
and the difference between the peak and valley currents of the M-RTD 52 and
the load device (shown here as the resistor RL, although active loads
are also contemplated). Similarly, the abruptness of the transition between levels
is determined primarily by the I-V characteristics of the M-RTD 52 and the
load device. The preferred embodiment of the interim sum subcircuit (Figure 3A)
contains two of these resonant tunneling transistor multi-level folding circuits
64 connected by a voltage divider, as shown.
With reference to Figure 3A, when the control signal Ei
is high, no current flows through transistor Q&sub3;. VREF is chosen
such that, for MRTDs with similar I-V characteristics, the base voltage of Q&sub2;
relative to the voltage reference, VREF, is nominally one-half of the
base voltage of Q&sub1; relative to the same voltage reference. The relationship
between Mi and Ni versus Si is then given by Figure
9. As shown, Ni changes state only once for every two changes of state
of Mi, due to the Q&sub1; to Q&sub2; base voltage division. With reference
to Figure 3B, and again when control signal Ei is high, transistor Q&sub8;
is on and transistor Q&sub9; is off. The output Wi depends only on the
inputs to transistors Q&sub4; and Q&sub5;, and as is clearly shown, Wi
= Ni - Mi. Figure 11 shows the transfer function of the interim
sum subcircuit when the control signal input is high.
When the control signal Ei is low, and again with reference
to Figure 3A, a voltage equal to two times the base-emitter junction on-voltage
is applied at the base of Q&sub3;. Given that the base-to-emitter voltage of conducting
transistor Q&sub3; is essentially the same as the forward biased diode voltage across
D&sub1; or D&sub2;, one base-emitter junction on-voltage appears across the resistor
R&sub4; at the emitter of Q&sub3;, and therefore the current that flows in Q&sub3;
is VBE/R&sub4;. This causes the Ni versus Si characteristic
to shift one state (VBE R&sub3;/R&sub4;), as shown in Figure 11. The
Mi transfer function is unchanged. With reference to Figure 3B, and again
when control signal Ei is low, transistor Q&sub9; is on and transistor
Q&sub8; is off. The output Wi depends only on the inputs to transistors
Q&sub6; and Q&sub7;, and as is clearly shown, Wi = Mi - Ni.
Figure 12 shows the transfer function of the interim sum subcircuit when the control
signal input is low.
The final subcircuit of the SR5-SR3 converter is the carry digit subcircuit
62. The carry digit subcircuit 62 has inputs Si and Ei,
and produces the carry digit Ci+1, as defined in Step 2, above. The preferred
embodiment of the carry digit subcircuit is shown in Figures 13A and 13B. As shown,
the carry digit subcircuit comprises two resonant tunneling multi-level folding
circuits 64 connected by a voltage divider made up of resistors R&sub7; and
reference voltage VREFC. In addition, shifting circuitry similar to that
in the interim sum subcircuit is shown. The operation of the carry digit subcircuit
62 is explained and discussed below.
With control signal Ei=0, no current flows in either Q&sub1;&sub0;
or Q&sub1;&sub1;. The transistor Q&sub1;&sub2;, resistor R&sub5; and the current
source cause the first upward transition of the Ki folding circuit to
occur at state -2.5 (i.e. the Si input is 'level shifted'), as shown
in the Ki transfer function of Figure 14. The voltage divider circuitry
applies one-fourth of the input state Si to the base of Q&sub1;&sub3;
and one-eighth of Si to the base of Q&sub1;&sub4;, causing the Ki
folding circuit to exhibit twice the number of state transitions as the Li
circuit for the same Si
input voltage range. The transfer function is
shown in Figure 15. The output levels of the Ki and Li folding
circuits are determined by the peak and valley currents of multiple resonant tunneling
device 52 and the value of R&sub8;. Outputs Ki and Li
are applied to the circuit of Figure 13B, which produces output Ci+1
= Li - Ki. The resulting Ci+1 transfer function
is shown in Figure 15.
With control signal Ei=1, current flows in Q&sub1;&sub0;
and Q&sub1;&sub1;, causing an additional level shift to be applied to the input
Si. By the proper choice of R&sub6;, the input state at which the first
upward transition of the Ki folding circuit is shifted to state -1.5,
as shown in the Ki transfer function of Figure 16. The Li
transition is similarly shifted, and the two-to-one base voltage relationship is
unchanged. The Li transfer function is shown in Figure 16. Again, the
circuit of Figure 13B produces Ci+1 = Li - Ki.
The resulting Ci+1
transfer function is shown in Figure 17.
Preferred Resonant Tunneling Device Parameters
In order to produce the Mi, Ni, Ki
and Li versus Si transfer functions described above, the multiple-peak
resonant tunneling devices 52 should generally exhibit at least four resonant
peaks occurring at approximately equally spaced potentials. Multiple-peak resonant
tunneling diodes can be obtained either by a series combination of RTDs or by use
of a single coupled quantum well heterostructure. When RTDs are combined in series,
the off-resonance RTDs in the chain may introduce an undesirable internal series
resistance, RS. This series resistance can cause a voltage hysteresis
equal in magnitude to the product of the difference between the peak and valley
currents and the difference between the negative differential resistance and the
positive series resistance RS. The onset of this hysteresis effect occurs
when the accumulated series resistance exceeds the RTD negative differential resistance.
The total number of RTDs that can be combined in series, therefore, is generally
limited by the accumulated series resistance of the specific device implementation.
The electrical properties of a resonant tunneling device are determined,
in part, by the thicknesses of its constituent layers. An example of a resonant
tunneling diode structure which exhibits a three-peak characteristic is given in
Table 1. The structure is a stack of epitaxially formed layers, layer 1 formed on
the substrate, layer 2 formed on layer 1, etc.
The measured hysteresis for this example M-RTD is less than 3 mV.
To achieve sufficient noise margins in MVL circuitry, M-RTDs should
generally have relatively equal peak currents, relatively equal valley currents,
relatively equally spaced peak voltages, modest peak-to-valley ratio, and low hysteresis.
Table 2 shows preferred values for some M-RTD parameters.
M-RTD ParameterPreferred ValuesPeak current variation≦ 10%Valley current variation≦ 20%Peak voltage spacing deviation from linearity≦ 5%Peak-to-valley ratio (PVR)≧ 4Hysteresis≦ 10 mV
Similarly, preferred values can be given for the bipolar switching
transistor parameters. Table 3 shows preferred values for some transistor parameters.
Transistor ParameterPreferred ValuesCommon Emitter Current Gain≧ 20Base-Emitter On-Voltage Mismatch≦ 5 mVEmitter Specific Resistivity≦ 1µΩcm²
In alternate embodiments of the invention, the control signal and
related circuitry may be deleted from the preferred embodiment. In the resulting
alternate embodiments, output word R will still represent the sum X+Y but will not
necessarily be signed digit range-3 base-4.
Many alternate embodiments are possible for the circuits given above.
The resonant tunneling multi-level folding circuits may generally be built from
any current switching device in conjunction with a M-RTD. A diode may be replaced
with a bipolar transistor with its base shorted to its collector.
Table 4, below, provides an overview of some embodiments and the figures.
A few preferred embodiments have been described in detail hereinabove.
It is to be understood that the scope of the invention also comprehends embodiments
different from those described, yet within the scope of the claims.
Internal and external connections can be ohmic, capacitive, direct
or indirect, via intervening circuits or otherwise. Implementation is contemplated
in discrete components or fully integrated circuits in silicon, gallium arsenide,
or other electronic materials families.
While this invention has been described with reference to illustrative
embodiments, this description is not intended to be construed in a limiting sense.
Various modifications and combinations of the illustrative embodiments, as well
as other embodiments of the invention, will be apparent to persons skilled in the
art upon reference to the description. It is therefore intended that the appended
claims encompass any such modifications or embodiments.
An apparatus for calculating the sum of two numbers represented by signed digit
range-3 base-4 words, said apparatus comprising at least one device which exhibits
negative differential resistance.
The apparatus of claim 1, wherein said device is a resonant tunneling device.
The apparatus of claim 1 or claim 2, wherein said sum is represented by a signed
digit range-3 base-4 word.
The apparatus of any preceding claim, further comprising:
summation circuits A(0), A(1), ... A(L) with the output of A(i) proportional to
the sum of its two inputs;
converters K(0), K(1), ... K(L) with an input of converter K(i) connected to said
output of A(i) and with a first output W(i) and a second output C(i+1) for an input
of 4C(i+1)+W(i), said converters comprising a resonant tunneling device; and
summation circuits T(1), T(2),... T(L) with a first input of T(i) connected to said
first output of K(i) and a second input connected to said second output of K(i-1)
and an output R(i) proportional to the sum of its two inputs;
whereby the value of the base-4 word having L+2 digits determined by R(0) through
R(L+1), where R(0)=W(0) and R(L+1)=C(L+1), is the sum of said two numbers.
The apparatus of claim 4, wherein said converters comprise two resonant tunneling
multi-level folding circuits connected by a voltage divider.
The apparatus of claim 5, wherein said resonant tunneling multi-level folding
circuits comprise a bipolar transistor with one or more resonant tunneling devices
integrated into its emitter.
An apparatus for adding numbers A and B, A and B represented by signed digit
range-3 base-4 words X and Y, respectively, X having digit states X(0) through X(L)
and Y having digit states Y(0) through Y(L), said apparatus comprising:
L+1 input summation circuits numbered 0 through L, the i'th input summation circuit
having an X input connected to X(i) and a Y input connected to Y(i) and an output
S(i) proportional to X(i)+Y(i);
L+1 signed range-5 to signed range-3 converter circuits numbered 0 through L, the
i'th converter circuit having an input connected to S(i) and outputs W(i) and C(i+1)
where 4C(i+1)+W(i)=S(i), said i'th converter circuit comprising at least one resonant
tunneling diode; and
L output summation circuits numbered 1 through L, each having a first input connected
to W(i) and a second input connected to C(i) and an output R(i) proportional to
whereby the sum of said numbers A and B is calculated and is represented by the
signed digit base-4 word R, R having digit states R(0) through R(L+1), R(0)=W(0),
R(L+1)=C(L+1), and the base-10 value of said sum given by
n-1 Σ4iRi i=0
The apparatus of claim 7, wherein said i'th signed range-5 to signed range-3
converter further comprises:
output E(i+1) having a first output state when S(i) is less than or equal to 0.5
and having a second output state when S(i) is greater than 0.5; and
input E(i) connected to said output E(i+1) of the (i-1)'th converter, W(i) restricted
to states -1, 0, 1 and 2 and C(i+1) restricted to states -1 and 0 when E(i) is equal
to said first output state, W(i) restricted to states -2, -1, 0 and 1 and C(i+1)
restricted to states 0 and 1 when E(i) is equal to said second output state;
whereby the sum of said numbers A and B is calculated and is represented by the
signed digit range-3 base-4 word R, R having digit states R(0) through R(L+1), R(0)=W(0),
R(L+1)=C(L+1), and the base-10 value of said sum given by
n-1 Σ4iRi i=0
An apparatus for the conversion of a signed range-5 digit into a two digit signed
base-4 word, said apparatus comprising two resonant tunneling multi-level folding
circuits connected by voltage divider circuitry.
A method of calculating the sum of two numbers comprising inputting two words
x and y;
forming a digit sum Si from the two words;
decomposing the digit sum into an interim sum and a carry digit; and
adding the interim sum and the carry digit to produce the digits of the sum.