The invention relates to a frequency synthesiser for generating a
sinusoidal analogue signal, and in particular direct digital synthesisers (DDS)
or numerically controlled oscillators.
JP-A-61-269405 illustrates a frequency synthesiser in which an arithmetic
circuit adds a preset prescribed level value to the preceding level value negatively
or positively. When the absolute value of the added result exceeds a preset maximum
setting value, the level value is added in opposite direction and then the polarity
of the addition is made inverse after that point of time. The time series digital
data group obtained as the result of operation is converted into an analogue quantity
by a digital-analogue converter in real time, the result passes through a proper
filter system such as a band-pass filter to decrease or reject the odd number order
harmonics and an object sinusoidal wave is obtained at an output terminal.
US-A-3763414 illustrates a reversible counter used in conjunction
with a number of gates and an impedance network to develop a staircase output having
a phase corresponding to the count initially registered. This output is then converted
into an AC signal.
US-A-4524326 describes an electrical circuit and method for multiplying
an analogue input signal by a sinusoidal function having an instantaneous phase
specified by a number signalled in binary format.
A problem which can arise in conventional DDS systems is that since
the output signal is quantised (it can only change amplitude at integer multiples
of the clock period) it effectively comprises a true sinewave plus an error signal.
For practical reasons, the DAC resolution of DDS systems is limited and the digital
sinewave (which can be very finely quantised and so have very little error) is
truncated. The conventional truncation process completely loses the electrical
information present in the least significant bits (LSB) and introduces errors in
the form of non-harmonic, spurious tones which limit the dynamic range.
In accordance with the present invention, a frequency synthesiser
for generating a sinusoidal analogue signal comprises means for generating a triangular
digital signal, each value of which has M bits; an adder to one input of which
is fed the digital signal from the digital signal generating means; and a digital-to-analogue
converter which receives the N most significant bits output by the adder and generates
in response an analogue sinewave signal, wherein M-N least significant bits from
the adder are fed back to be added by the adder to the next succeeding value of
the digital signal.
In this new approach, the information normally lost in truncation
when the digital value is fed to the DAC is retained by adding that information
to the next data sample before truncation. A significant benefit is obtained from
the extra information available in the LSBs and it has been found that this changes
the type of error to a more acceptable form.
Preferably, the digital-to-analogue converter has a non-linear transfer
function shaped such that a sinusoidal analogue signal is generated.
In this approach, a DAC with a non-linear transfer function is used.
This has the advantage that a fast PROM required in other approaches is no longer
needed so saving chip area and cost.
Preferably, the non-linear transfer function generates a piece-wise
linear approximation to a sinewave. The piece-wise linear approximation can be
analysed as the sum of triangular pulse trains. For four segments there are four
equations in cos(wt) so harmonics can be cancelled up to ninth order above which
they will be small. Furthermore, as a sinewave moves from the zero crossing to
the peak its slew rate decreases and the accuracy required reduces. This allows
the complexity of the DAC to be reduced compared to a linear DAC improving yield
and reducing chip area.
Preferably, the DAC comprises a number of subsidiary DACs; and control
means responsive to the DAC input signal to activate different groups of the subsidiary
DACs dependent on the segment of the sinewave being generated. This has the advantage
that the individual segments or pieces can be trimmed by adjusting only the reference
resistors of the subsidiary DACs, which is not interactive and should be easy
to do in production. Furthermore, once the segments have been trimmed, monotonicity
is guaranteed. In addition, it is very simple to interconnect DACs of differing
resolution which is what is required for waveform synthesis.
In the preferred example, each subsidiary DAC comprises a conventional
DAC with an additional switch so that the normally dumped current can be utilised.
This is particularly advantageous since only standard, binary DACs are required.
In the preferred example, the components of the frequency synthesiser
according to the invention are fabricated on a single integrated circuit although
this is not essential.
Some examples of frequency synthesisers according to the present
invention will now be described and contrasted with known examples with reference
to the accompanying drawings, in which:-
- Figure 1 is a block diagram of a conventional direct digital synthesiser;
- Figure 2 is a block diagram of a synthesiser according to one example of the
- Figure 3 is a block diagram of a digital triangle wave generator;
- Figure 4 is a block diagram of the DAC shown in Figure 2;
- Figures 5A and 5B illustrate a standard binary DAC and a modified binary DAC
for use in the Figure 4 circuit;
- Figure 6 illustrates part of a sinewave output by the DAC shown in Figure 2;
- Figure 7 is a Fourier transform of the output from a conventional direct digital
- Figure 8 illustrates an adder for insertion into the circuit shown in Figure
- Figure 9 is a Fourier transform of the output from the circuit of Figure 2
including the adder of Figure 8.
Figure 1 illustrates a conventional direct digital synthesiser DDS
which comprises a digital triangle wave generator 1 whose output, digital triangle
wave is fed to a look up table in the form of a PROM 2. The output from the PROM
2 is fed to a DAC 3 having a linear transfer function which generates an analogue
Figure 2 illustrates a DDS according to one example of the invention.
In this example, the digital triangle wave generator 1 is provided as before but
this time the output from the generator feeds directly to a DAC 5 having a non-linear
transfer function. In this context, "directly" means that no pre-shaping of the
output from the generator 1 takes place before feeding to the DAC 5 although this
must be understood in the context of the modification to be described below and
in Figure 8 in accordance with the present invention. The output from the DAC 5
is a piece-wise linear sinewave 6.
The construction of the digital triangle wave generator 1 is conventional
and is shown schematically in Figure 3. The generator essentially comprises a counter
having an adder 7 whose 24 bit output is fed to a latch 8 forming a delay circuit.
The output from the latch 8 is fed back to the adder 7 where it is added to a constant
value. Consequently, the output from the latch 8 regularly increments by an amount
corresponding to the constant value and by switching the sense of the output depending
on the value of the most significant bit, a triangle wave is formed.
The construction of the DAC 5 is shown in Figure 4. This will not
be explained in detail but it can be seen that the DAC 5 comprises five sets of
components 9-13 corresponding to the five segments or pieces of the sinewave which
are generated in a half cycle. Each set of components comprises a latch 14-18 and
a DAC 19-23 respectively. The construction of each DAC 19-23 is shown generally
in Figure 5B. Figure 5A illustrates a conventional binary DAC where it will be
seen that provision is made to dump the so-called "idump" output to
ground. In the modified DAC (Figure 5B) an additional switch is provided to enable
the idump current itself to be switched to the output of the DAC.
The operation of the DAC shown in Figure 4 will now be described
in connection with the first two sets of components 9, 10, the operation of the
remainder of the components 11-13 being self-explanatory.
The seven MSBs from the generator 1 are fed to the DAC 5 and, as
can be seen in Figure 6, since at this point 36 the curve is relatively shallow,
the least significant of these bits is ignored and the next three bits D1-D3
are fed to the latch 14. The remaining three bits are fed to a NOR gate 25.
The output from the NOR gate 25 initially enables the latch 14 so
that the data bits D1-D3 pass through the latch to the DAC
19. The output from the NOR gate 25 is also inverted by an inverter 26 so that
the idump output is non-enabled.
Initially, the databits D1-D3 are all zero with
the result that the output current i0 is zero. As the bits D1-D3
to increment a corresponding increase in current i0 occurs until all
three bits are "1". At the next clock cycle bit D0 will change to a
1 and no different action will take place. At the next clock cycle, however, bit
will change state to a "1" with the result that the output from the
NOR gate 25 changes to a "0" thus deactivating the latch 14 and holding the values
at Q0-Q2 at "1". In addition, the idump current
is activated to flow from the i0
output of the DAC 19. The analogue sinewave
has thus reached the point 27 (Figure 6).
Upon the bit D4 switching to a "1" the component 10 becomes
active. This is because the bit D4 is fed through an inverter 28 to
a NOR gate 29 thus enabling the latch 15 while the bits D5, D6
are fed through an OR gate 30 to the idump input of the DAC 20. These
two bits will remain "0" so that the idump current does not flow. Since
at this part of the sinewave cycle the slope is relatively steep, the effect of
the least significant bit is taken into account so that bits D0-D3
are fed to the latch 15. At the point where D4 switches to a "1" the
bits D0-D3 will all be zero so that the final increment in
current is due to the DAC 19 when idump is output. At the next clock
changes to a 1 and this is passed through the latch 15 to the
DAC 20 causing its i0 output to increase above zero and hence be added
to the output from the DAC 19 and so be output from the DAC 5 at the beginning
of the next segment of the cycle. This then continues as before with the output
current increasing until the output from DAC 20 is latched at the idump
value whereupon the components 11 come into play. This continues until the input
value becomes 1111111 and then the digital values will begin to decrease and the
reverse operation will take place.
Figure 6 illustrates the different portions of the sinewave curve
and the DACs 19-23 involved.
As will be appreciated from the previous discussion, the output from
the generator 1 is truncated and this leads to significant quantisation of the
finally output analogue signal. Furthermore, the digital signal provided by the
generator 1 is itself quantised and if the constant value (Figure 3) is not an
integer factor of the highest count value then the generator will itself exhibit
a degree of jitter which should be minimised.
Figure 7 is a fast Fourier transform of the output signal from a
conventional DDS such as that shown in Figure 1 and it will be seen that there
are significant frequencies present on either side of the primary frequency.
To reduce this problem, it is proposed to insert an adder 31 between
the generator 1 and DAC 5 (Figure 8). The input to the adder 31 is a 24 bit digital
value from the generator 1 as shown at 32 while the eight MSBs shown at 33 are
fed to the DAC 5. The sixteen LSBs output by the adder 31 are fed back through
a delay circuit 34 to the input of the adder 31 where they are added to the corresponding
sixteen LSBs of the next digital value.
Figure 9 illustrates a typical frequency plot of the output from
such a modified synthesiser showing that the nature of the error has been spread
into a densely sloping noise floor, increasing the dynamic range to 70dB for a
similar example to that above.