PatentDe  


Dokumentenidentifikation EP0780963 26.10.2000
EP-Veröffentlichungsnummer 0780963
Titel Geräuscharmer Kommutierungsschaltkreis für einen elektrischen Motor
Anmelder Siliconix Inc., Santa Clara, Calif., US
Erfinder Pham, Giao M., Milpitas, US;
Nguyen, James H., San Jose CA 95148, US
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69610401
Vertragsstaaten DE, FR, GB, IT, NL
Sprache des Dokument EN
EP-Anmeldetag 12.12.1996
EP-Aktenzeichen 961199106
EP-Offenlegungsdatum 25.06.1997
EP date of grant 20.09.2000
Veröffentlichungstag im Patentblatt 26.10.2000
IPC-Hauptklasse H02P 6/00

Beschreibung[en]

This invention relates to a method for commutating an electric motor as well as to a commutation circuit according to the preamble of claim 1 and claim 4 respectively.

Such a method for commuting an electric motor is depicted in EP 0 653 833 A1. With this known method the phases of a direct-current brushless electric motor are energized sequentially in a manner such there is a period of time during both of the two phases being switched are energized. Such phase-to-phase switching from a first phase to a second phase starts by energizing the second phase by the current therein starts to increase without being limited by a control circuit, but only by the electric time constant. Since the first phase is controlled by the control circuit which tries to keep the sum of the currents in the two phases constant, i.e. equal to a reference value Iref, the current in the first phase is reduced at a rate determined by the electric time constant of the first phase. The total current flowing in the phases is detected by a sensor and is subtracted from the reference Iref in a adding nod, which generates an error signal to be supplied to the control circuit.

Further EP 0 653 833 A1 discloses a commutation circuit for said commuting method, whereas each phase is connected to a transistor, which is controlled by a node for generating a control signal for the transistor. Each node is connected with two combination circuits with two inputs respectively. The inputs of one combination circuit is connected with a logic circuit and the power supply respectively and the other combination circuit is connected with the logic circuit and the control circuit. Therefore the logic circuit has six outputs and the three inputs for logic signals H1, H2 and H3 indicating the angular position of the rotor of the motor. A fourth input of the logic circuit is connected with the output of a comporator, whose non-inverting terminal is connected with the output of the control circuit. The inverting terminal of this comparator is connected with a reference value Iref.

With this known commutation circuit is achieved less torque variation and less acoustic noise.

The method disclosed in this document is carried out by using the described commutation circuit by continuous control. But this method may be used also with pulse-width modulated current control (PWM).

Further Figure 1 is a schematic diagram of a conventional commutation sequencer 18 connected to conventional motor and drive circuitry 7, which includes a portion of a three-phase brushless spin motor 10 connected to a motor driver 20. For the example illustrated herein, spin motor 10 is assumed to include three sets of phase windings, each of which is selectively driven at a predetermined phase. In Figure 1, the three sets of windings are represented by phase windings 12, 14 and 16, which are arranged around a rotor shaft (not shown) and have a common connection at a center tap 11. As known to those skilled in the art, sequencer 18 and a motor driver 20 collectively operate to selectively driver pairs of phase windings 12, 14, and 16 to induce rotation of the rotor shaft of motor 10. Diodes D1-D6 protect motor and drive circuitry 7 from extreme voltages on nodes A, B, and C that would otherwise result, as explained below, due to the inductances of windings 12, 14, and 16.

Figure 2 is a set of traces illustrating motor torque with respect to motor electrical degrees. To spin a rotor shaft of a motor continuously in one direction, the motor torque should be either continuously positive or continuously negative. A continuously positive motor torque, for example, can be provided by designing and controlling sequencer 18 and motor driver 20 to transfer current to selected pairs of windings in a predetermined and precisely timed sequence so that the overall torque curve of the motor is defined along the extremum segments connecting points a1-a7 of Figure 2. The act of transferring current from one pair of windings to the next is conventionally called "commutation."

Referring back to Figure 1, transistors 20a, 20c, and 20e are used to connect their respective windings to the positive voltage terminal V+; such transistors are known in motor lexicon as "highside" transistors. Conversely, transistors 20b, 20d, and 20f are used to connect their respective windings to the relatively low ground potential, and so are referred to as "lowside" transistors. Using this labeling convention, the line used to drive the highside transistor 20a for phase A is labeled HSA for "highside A." Similarly, the line used to drive the lowside transistor 20b for phase A is labeled LSA for "lowside A." The highside and lowside drive lines for phases B and C are similarly labeled HSB and LSB, and HSC and LSC, respectively.

Let us assume that highside A transistor 20a and lowside B transistor 20d are on so that windings 12 and 14 are conducting current (i. e., the motor is within phase AB). To commutate motor 10 from phase AB to phase AC, transistor 20d is turned off and transistor 20f is turned on. Because windings are inherently inductive, windings 14 and 1 6 resist changes in current. Thus, when transistor 20d is abruptly turned off, the current through winding 14 (phase B) is forced back toward to power supply V+ through a diode D3, and when transistor 20f is turned on, the current through winding 16 (phase C) will, for an instant, remain zero. If diode D3 were not provided, the voltage level on terminal B would rise to some extreme positive value, likely damaging motor and drive circuitry 7. Diodes D1 and D6 similarly protect nodes A and C from extreme positive voltage levels, while diodes D2, D4, and D5 protect nodes A, B, and C, respectively, from extreme negative voltage levels.

Back electro-motive force (BEMF) induced in winding 14 by the movement of the rotor shaft increases the voltage drop across winding 14, thus speeding the decline of the current through winding 14. Conversely, BEMF induced in winding 16 decreases the voltage drop across winding 16, thus slowing the rate of increase in current through winding 16. Because the current through winding 14 diminishes more quickly than the current through winding 16 increases, the current from the power supply V+ through winding 12 (i. e., IB + IC) is not constant during the period of transition from winding 14 to winding 16. Furthermore, the resultant periodic fluctuations in power supply and winding currents can cause electro-acoustic effects in power supply and motor structures, as evidenced by an annoying audible hum. The power-supply-current fluctuations may be diminished through the use of high-performance power supplies, but upgraded power supplies add considerable weight and expense. Moreover, high-performance power supplies do little to solve the problem of fluctuations in winding currents.

The method of commutating as disclosed by the above mentioned EP 0 653 833 A1 diminishes this undesirable noise without a need of a robust power supply.

But the commutation circuit used for this known method is very complex in structure and therefore leads to high production costs.

The object of the invention is to provide an improved method of commutating, which can be used by a simple constructed commutation circuit.

This object is achieved in accordance with the invention by the features in the characterising part of claim 1 and claim 4 respectively.

According to claim 1 the method is carried out by repeatedly turning the first switch off for a fixed period of time whenever the sum of the first and second current exceeds a predominant threshold level.

This improved method is carried out according to claim 4 with a one-shot which generates a pulse-with-modulated (PWM) signal with a fixed pulse duration which is a fixed off-time for the second switch whenever the sum of the first and second current exceeds the threshold level by means of a comparator.

These and other features, aspects, and advantages of the present invention will become understood with regard to the following description, appended claims, and accompanying drawings, where:

  • Figure 1 is a schematic diagram of a conventional commutation sequencer 18 connected to conventional motor and drive circuitry 7;
  • Figure 2 is a set of traces illustrating motor torque with respect to motor electrical degrees;
  • Figure 3 shows conventional motor and drive circuit 7 connected to a quiet commutation circuit 31 in accordance with an embodiment of the invention;
  • Figure 4 shows various waveforms corresponding to like-named terminals depicted in Figure 3;
  • Figure 5 shows conventional motor and drive circuit 7 connected to a quiet commutation circuit 31 in accordance with an embodiment of the invention;
  • Figure 6 shows various waveforms corresponding to like-named terminals depicted in Figure 5;
  • Figure 7 is a decode table that describes the outputs of commutation sequencer 41 with respect to the various possible phases and inputs; and
  • Figure 8 is a motor and drive circuit 70 coupled to quiet commutation circuit 31 in accordance with another embodiment of the invention.

Figure 3 shows conventional motor and drive circuit 7 connected to a quiet commutation circuit 31 in accordance with an embodiment of the invention. Motor and drive circuit 7 is the same as that described above in connection with Figure 1; however, various of the components have been rearranged or omitted to simplify the following description.

Quiet commutation circuit 31 includes a commutation sequencer 41, a sense resistor RS, a comparator 51, a one-shot 53, and a make-before-break circuit 54. Make-before-break circuit 54 in turn includes a blanking generator 55, an AND gate 57, and a make-before-break generator 59. Sequencer 41, like sequencer 18 of Figure 1, operates to selectively drive pairs of phase windings 12, 14, and 16 using high- and lowside drive lines HSA, LSA, HSB, LSB, HSC, and LSC.

Figure 3, in conjunction with Figure 4, is used to explain the concept of "lowside commutation," so called because current is switched from one lowside transistor to the next. For simplicity, Figure 3 includes only those components necessary to explain a lowside commutation from phase AB to phase AC. For example, transistors 20a, 20d, and 20f are the highside A, lowside B, and lowside C transistors, respectively. (The concept of "highside commutation," in which current is switched from one highside transistor to the next, is explained below in connection with Figure 5.)

Current passing through any of the lowside transistors, including the illustrated lowside transistors 20d or 20f of Figure 3, must also pass through sense resistor RS. Thus, sense resistor RS develops a voltage on terminal VRS that is proportional to the total lowside current ILS through the lowside of motor and drive circuit 7.

The voltage developed across sense resistor RS is provided to the non-inverting terminal (+) of comparator 51. The inverting terminal (-) of comparator 51 is connected to a motor-control terminal VMC, upon which is provided an externally-supplied motor control voltage that establishes the level of current through, (and consequently the speed of) spin motor 10 of motor and drive circuit 7.

The output of comparator 51 is connected to the input of one-shot 53 and to one input of AND gate 57. The output of one-shot 53 is provided to input terminals of both sequencer 41 and blanking generator 55 via a line PWM. The output of blanking generator 55 is connected to a second input of AND gate 57. Finally, the output of AND gate 57 is connected to an input of make-before-break generator 59.

The operation of quiet commutation circuit 31 is explained below in connection with Figure 4, which includes various waveforms corresponding to like-named terminals depicted in Figure 3.

Referring to motor and drive circuitry 7, assume that the motor is in phase AB so that windings 12 and 14 are conducting. When transistor 20d is turned on, the current through sense resistor RS increases until the voltage on terminal VRS exceeds the motor control voltage on terminal VMC. At that instant (time t0 of Figure 4) comparator 51 outputs a logic one (e.g., five volts) on terminal VRS>VMC to the input of one-shot 53. In response, one-shot 53 outputs a logic one (e.g., five volts) on line PWM for e.g. 12 microseconds. The logic one on line PWM causes sequencer 41 to output a logic zero on line LSB, shutting off transistor 20d. Transistor 20d remains off until the signal on line PWM (i.e., the output of one-shot 53) returns to a logic zero. In one embodiment, the duration of the "off time" Toff is programmable from 3 to 12 microseconds.

During the time that transistor 20d is off, the voltage on terminal VRS is pulled to ground through sense resistor RS. Because of the inherent inductance of winding 14, the current IB does not cease during the off time Toff. Instead, the current IB gradually decreases as it is forced through diode D3 back toward the power supply. Next, at the end of the off time Toff, the signal on line PWM returns to a logic zero, causing sequencer 41 to change state and again turn on transistor 20d.

Because the current IB will have decreased during the preceding off time Toff, the voltage on terminal VRS will immediately rise to a level less than the motor control voltage on terminal VMC when transistor 20b begins conducting once again. The current IB will then increase once again until the voltage on terminal VRS rises above the control voltage VMC, initiating the next off time Toff. Thus, quiet commutation circuit 31 sequentially provides a pulse-width-modulated (PWM) signal to transistor 20d via line LSB.

The type of PWM used in the present example is conventionally called "fixed off-time" PWM because the off time, which is established by one-shot 53, is the fixed time period Toff. To increase the current IS, and therefore the speed of the motor 10, the voltage on control terminal VMC is adjusted upward. Such an adjustment increases the on-time of e.g. transistor 20d relative to the fixed off time Toff, thus increasing the average current through the active windings.

When motor and drive circuitry 7 receives an FCOM pulse on line FCOM, the motor 10 must be commutated to the next phase. That is, the supply current IS must be re-routed to pass through the next pair of windings to be driven. In the foregoing example, motor and drive circuitry 7 was described in phase AB, in which windings 12 and 14 are the active pair of windings. The following example describes the commutation to phase AC, in which windings 12 and 16 become the active pair; that is, the highside remains highside A while the lowside is switched from lowside B to lowside C.

The lowside commutation from phase AB to phase AC begins at the leading edge of an FCOM pulse, as shown as time tcom in Figure 4. Sequencer 41 responds to the FCOM pulse by providing a logic one on line LSC, thereby turning transistor 20f fully on. Thus, the current IC through lowside C winding 16 begins to increase at time tcom.

As the current IC increases, the voltage drop across sense resistor RS, and consequently the voltage on terminal VRS, will increase due to the additional current. For this reason, the on-time of transistor 20d, as determined by the time required for the voltage on terminal VRS to exceed the motor control voltage on terminal VMC, will decrease as the current IC increases. And, because of the feedback provided by sense resistor RS, the current through lowside B (transistor 20d and winding 14) will be forced to decrease at a rate that is established by the rate of increase of the current IC through lowside C (transistor 20f and winding 16). As explained in more detail below, the commutation from phase AB to phase AC is complete when the current IC, by itself, develops a voltage on terminal VRS that exceeds the voltage on terminal VMC.

The time during which the current IB is decreasing and the current IC is increasing is called the "make-before-break" period because a current path is "made" through phase C winding 16 before the current path is "broken" through phase B winding 14. As indicated above, the make-before-break period begins with the rising edge of an FCOM pulse and ends when the current IC by itself develops a voltage on terminal VRS that exceeds the voltage on terminal VMC.

The purpose of make-before-break circuit 54 (e.g., generator 59, blanking generator 55, and AND gate 57, collectively) is to determine the length of the make-before-break period. Make-before-break generator 59 is a simple logic circuit that outputs a logic one on make-before-break line MBB upon receiving a positive-going transition on line FCOM and then returns to a logic zero upon receiving a positive-going transition on end-make-before-break line END_MBB. If the FCOM pulse returns to a logic zero before the end-make-before-break line END_MBB goes positive, make-before-break circuit 54 is configured to output a logic zero on make-before-break line MBB; thus, the duration of the make-before-break period TMBB is limited to the duration of the FCOM pulse.

To determine when the current IC by itself develops a voltage on terminal VRS that exceeds the voltage on terminal VMC, the voltage on terminal VRS is compared to the voltage on terminal VMC when the pulse-width-modulated transistor 20d is off. To this end, AND gate 57 provides a logic one when the transistor 20d is off (i.e., the voltage on terminal PWM is a logic one) and the voltage on terminal VRS is greater than the control voltage on terminal VMC (as indicated by a logic one on terminal VRS>VMC). A logic one output from AND gate 57 on the end make-before-break line END_MBB triggers make-before-break generator 59 to output a logic zero to sequencer 41 on terminal MBB, indicating an end to the make-before-break period TMBB. Sequencer 41 responds at time tend_mbb by providing a logic zero on line LSB and providing the PWM signal to lowside-C transistor 20f, thereby switching control to transistor 20f.

Blanking generator 55 conventionally provides blanking windows BW within each off time Toff. Each time the voltage on terminal PWM transitions from logic zero to logic one, blanking generator 55 provides a logic one after a delay td1 and returns to a logic zero a time td2 before the end of the off period Toff. The blanking function of blanking generator 55 provides safety margins to ensure that the end of the make-before-break period TMBB is triggered within an off period Toff. In one embodiment, delay td1 and time td2 are programmable, allowing for the optimization of the blanking function.

Figure 5 is a schematic diagram of quiet commutation circuit 31 connected to motor and drive circuit 7. The circuits of Figure 5 are identical to those of Figure 3; however, motor and drive circuitry 7 is shown to include only those components necessary to explain a highside commutation from phase AC to phase BC. For example, transistors 20a, 20c, and 20f are the highside A, highside B, and lowside C transistors, respectively.

Referring to motor and drive circuitry 7, assume that the motor is in phase AC so that current from supply terminal V+ is conducted through windings 12 and 16, in that order. When transistors 20a and 20f are both on, the current through sense resistor RS increases until the voltage on terminal VRS exceeds the control voltage on terminal VMC. At that instant (time t0 of Figure 6) comparator 51 outputs a logic one (e.g., five volts) on terminal VRS>VMC to the input of one-shot 53. In response, one-shot 53 outputs a logic one (e.g., five volts) on line PWM. The logic one on line PWM causes sequencer 41 to output a logic zero on line LSC, shutting off transistor 20f. Transistor 20f remains off until the output of one-shot 53 returns to a logic zero.

During the time that transistor 20f is off, the voltage on terminal VRS is pulled to ground through sense resistor RS. Because of the inherent inductances of windings 12 and 16, the current IC does not cease during the off time Toff. Instead, the current IC gradually decreases as it is forced through diode D6 back toward the power supply. Next, at the end of the off time Toff, the signal on line PWM returns to a logic zero, causing sequencer 41 to change state and again turn on transistor 20f.

Because the current IC decreased during the preceding off time Toff, the voltage on terminal VRS will immediately rise to a level less than the control voltage on terminal VMC when transistor 20f begins conducting once again. The current IC will then increase once again until the voltage on terminal VRS rises above the control voltage on terminal VMC thus initiating the next off time Toff. In this way, quiet commutation circuit 31 sequentially provides a PWM signal to transistor 20f via line LSC.

When motor and drive circuitry 7 receives an FCOM pulse on line FCOM, the motor 10 must be commutated from phase AC to phase BC, in which windings 14 and 16 become the active pair; that is, the highside is switched from highside A to highside B, while the lowside remains lowside C. This process is conventionally known as "highside" commutation.

The highside commutation from phase AC to phase BC begins at the leading edge of an FCOM pulse, as shown as time tcom in Figure 6. Sequencer 41 responds to the FCOM pulse by:

  • 1. providing a logic one on line HSB, thereby turning transistor 20c on;
  • 2. providing a logic one on line LSC, thereby turning transistor 20f fully on; and
  • 3. switching the PWM current control signal from line LSC to line HSA.

With a logic one on line HSB, the current IB through highside B winding 14 will increase. And, as current IB increases, the voltage drop across sense resistor RS, and consequently the voltage on terminal VRS, will increase due to the additional current through winding 16. For this reason, the on-time of transistor 20a, as determined by the time required for the voltage on terminal VRS to exceed the voltage on terminal VMC, will decrease as the current IB increases. Furthermore, because of the feedback provided by sense resistor RS, the current through highside A (transistor 20a and winding 12) will be forced to decrease at a rate that is established by the rate of increase of the current IB through highside B (transistor 20c and winding 14).

The period during which the current IA is decreasing and the current IB is increasing (the make-before-break period) begins with the rising edge of an FCOM pulse and ends when the current IB by itself (through winding 16) develops a voltage on terminal VRS that exceeds the voltage on terminal VMC. To determine when the current IB by itself develops a voltage on terminal VRS that exceeds the voltage on terminal VMC, the voltage on terminal VRS is compared to the voltage on terminal VMC when the modulated transistor 20a is off. At such times, the contribution of phase-A winding 12 to the current IC through winding 16 will be conducted back to node A via diode D2, and therefore will not contribute to the voltage on terminal VRS.

AND gate 57 provides a logic one to make-before-break generator 59 when the transistor 20d is off (i.e., the voltage on terminal PWM is a logic one) and the voltage on terminal VRS is greater than the control voltage on terminal VMC (as indicated by a logic one on terminal VRS>VMC). A logic one output from AND gate 57 on the end-make-before-break line END_MBB triggers make-before-break generator 59 to output a logic zero to sequencer 41 on terminal MBB, indicating an end to the make-before-break period TMBB.

Sequencer 41 responds at time tend_mbb by:

  • 1. providing a logic zero on line HSA, thereby turning transistor 20a off;
  • 2. providing a logic one on line HSB, thereby turning transistor 20c fully on; and
  • 3. switching the PWM current control signal from line HSA back to line LSC.
From time tend_mbb, sequencer 41 continues to control current through phase BC (windings 14 and 16) by modulating the signal on line LSC until the next commutation signal.

Figure 7 is a decode table that describes the output levels of commutation sequencer 41 with respect to the various possible phases, or "states," and the input levels on lines MBB and PWM. The outputs EMFA, EMFB, EMFC, and RE are conventionally used to select the unpowered winding so that the back electro-motive force (BEMF) of that unpowered winding may be used to establish the appropriate FCOM-pulse timing.

The truth table of Figure 7 may be used in conjunction with conventional computer-aided design (CAD) software to provide the necessary circuitry to implement sequencer 41. An example of an appropriate CAD program is AutoLogic™ available from Mentor Graphics of Sunnyvale, California.

Figure 8 is a motor and drive circuit 70 coupled to quiet commutation circuit 31 in accordance with another embodiment of the invention. Motor and drive circuit 70 is similar to motor and drive circuit 7 of Figures 3 and 5, like-numbered elements being the same for all three figures. However, the feedback network for developing the voltage on terminal VRS is modified for improved efficiency.

In addition to the components shown in Figures 3 and 5 for motor and drive circuit 7, motor and drive circuit 70 includes feedback circuits 71 and 81. And, while not shown, a third feedback circuit similar to feedback circuits 71 and 81 is provided for low-side A transistor 20b. Each of the feedback circuits operates in the manner described below in connection with feedback circuit 71.

Feedback circuit 71 includes a transistor 20d', an operational amplifier 73, and a conventional current mirror comprised of transistors 74 and 76. Operational amplifier 73 has its inverting and non-inverting input terminals connected to the drains of transistors 20d and 20d', respectively. By controlling the voltage on the control terminal of transistor 76, operational amplifier 73 maintains the same voltage on the respective drains of transistors 20d and 20d'.

Transistor 20d' is similar to low-side transistor 20d, except that low-side transistor 20d has a multiplication factor M of 1500, while transistor 20d' has a multiplication factor M of one. Thus, as transistors 20d and 20d' have substantially identical gate and drain voltages, the current through transistor 20d' is 1500 times less than the current conducted by low-side transistor 20d (i.e., I20d. = 120d/1500).

The current I20d. through transistor 20d' is conventionally mirrored by transistors 74 and 76 so that a current of I20d/1500 is conducted to sense resistor RS via terminal VRS. Feedback circuit 81 similarly provides current I20f/1500, and the third feedback circuit provides a current I20b/1500, representing the current through low-side transistor 20b. Currents I20b/1500, I20d/1500, and I20f/1500 are summed at terminal VRS so that a current ILS/1500, equal to the total lowside current divided by 1500, passes through sense resistor RS to develop a feedback voltage on terminal VRS.

Importantly, motor and drive circuit 7 of Figures 3 and 5 drives sense resistor RS with a current ILS that is 1500 times greater than the current ILS/1500 provided to sense resistor RS by motor and drive circuit 70. Thus, motor and drive circuit 70 significantly reduces the amount of power dissipated by sense resistor RS, and thereby improves overall efficiency. Because of the reduced current through sense resistor RS, the value of sense resistor RS must be increased by a factor of 1500 if the voltage drop across sense resistor RS is to be maintained.

Commutation circuits in accordance with the present invention are not limited to the particular applications described above. For example, the pulse-width modulation used to control current through motor 10 could be implemented as constant-frequency PWM or constant-on-time PWM.


Anspruch[de]
  1. Verfahren zur Kommutierung eines Elektromotors, der erste und zweite Wicklungen (14, 16) und erste und zweite Schalter (20d, 20f) zur Steuerung des Stromflusses durch die erste und zweite Wicklung (14, 16)aufweist, mit folgenden Verfahrensschritten:
    • Einschalten des ersten Schalters (20d), um einen ersten Strom (IB) durch die erste Wicklung (14) fließen zu lassen;
    • nachdem der erste Strom (IB) in der ersten Wicklung (14) fließt, Einschalten des zweiten Schalters (20f), um einen zweiten Strom (IC) durch die zweite Wicklung (16) fließen zu lassen, wobei der Pegel des zweiten Stroms (IC) wenigstens teilweise aufgrund der Induktivität der zweiten Wicklung (16) nach und nach zunimmt;
    • Erfassen der Summe des Pegels des ersten Stroms (IB) und des Pegels des zweiten Stroms (IC);
    gekennzeichnet durch

    Ausschalten des ersten Schalters (20d) für eine vorbestimmte Zeitperiode (TOFF), wenn die Summe des Pegels des ersten Stroms (IB) und des Pegels des zweiten Stroms (IC) einen vorbestimmten Schwellenwert überschreitet, so daß die Summe des Pegels des ersten Stroms (IB) und des Pegels des zweiten Stroms (IC) auf einen Wert unterhalb des vorbestimmten Schwellenwertes reduziert wird.
  2. Verfahren nach Anspruch 1, bei dem des weiteren das Ausschalten des ersten Schalters (20d) für eine gegenüber der vorbestimmten Zeitperiode längeren Zeitperiode, wenn der zweite Strom (IC) den vorbestimmten Schwellenwert überschreitet, bevor die vorbestimmte Zeitperiode (TOFF) endet.
  3. Verfahren nach Anspruch 1 oder 2, bei dem des weiteren ein Kommutierungssignals (FCOM) empfangen wird, und das Einschalten des zweiten Schalters (20f) in Reaktion auf das Kommutierungssignal (FCOM) erfolgt.
  4. Kommutierungsschaltung (31) für einen Elektromotor, der eine erste Wicklung (14), einen ersten Stromschalter (20d) zur Regelung eines ersten Strompegels (IB) durch die erste Wicklung (14), eine zweite Wicklung (16) und einen zweiten Stromschalter (20f) zur Regelung eines zweiten Strompegels (IC) durch die zweite Wicklung (16) aufweist, wobei die Kommutierungsschaltung (31) umfaßt:
    • einen Eingangspunkt für die Übernahme eines Kommutierungssignals (FCOM);
    • eine Folgesteuerung (41), von der ein erster Eingangsanschluß mit dem Eingangspunkt und erste und zweite Ausgangsanschlüsse (LSB, LSC) mit ersten und zweiten Stromschaltern (20d, 20f) verbunden sind, wobei die Folgesteuerung (41) das Ausschalten des ersten Stromschalters (20d) und das Einschalten des zweiten Stromschalters (20f) in Reaktion auf das Kommutierungssignal (FCOM) bewirkt; und
    • einen Stromfühler (RS) zur Generierung eines Signals (VRS), das für eine Summe des ersten und zweiten Pegels (IB, IC) repräsentativ ist; und gekennzeichnet durch einen Komparator (51), von dem ein erster Eingangsanschluß (+) mit einem Ausgangsanschluß des Stromsensors (RS) und ein zweiter Eingangsanschluß (-) mit einem Steuersignal (VMC) verbunden ist;
    • ein Monoflop (53), von dem ein Eingangsanschluß mit einem Ausgangsanschluß des Komparators (51) und ein Ausgangsanschluß mit einem zweiten Eingangsanschluß der Folgesteuerung (41) verbunden ist, wobei das Monoflop (53) zur Generierung einer Folge von Impulsen (PWM) gleicher Länge dient, und jeder der Impulse (PWM) die Folgesteuerung (41) veranlaßt, ein Signal für das Ausschalten des ersten Stromschalters (20d) zu generieren.
  5. Kommutierungsschaltung (31) nach Anspruch 1, dadurch gekennzeichnet, daß die Anstiegsrate des zweiten Strompegels proportional zur Induktivität der zweiten Wicklung ist.
  6. Kommutierungsschaltung (31) nach einem der Ansprüche 4 oder 5, gekennzeichnet durch eine unterbrechungslose Folgeschaltung (54), von der ein Eingangsanschluß mit dem Ausgangsanschluß des Komparators (51) und ein Ausgangsanschluß mit einem dritten Eingangsanschluß der Folgesteuerung (41) verbunden ist, wobei die unterbrechungslose Folgeschaltung (54) der Folgesteuerung (41) meldet, wenn der zweite Strompegel (IC) einen Schwellenwert überschreitet.
  7. Kommutierungsschaltung (31) nach Anspruch 6, dadurch gekennzeichnet, daß die unterbrechungslose Folgeschaltung (54) die Folgesteuerung (41) veranlaßt, den Stromfluß durch die erste Wicklung (14) in Reaktion auf das Steuersignal (VMC) und das vom Stromfühler (RS) vor dem Überschreiten des Schwellenwertes durch den zweiten Strompegel (IC) generierte Signal (VRS) zu regeln; und daß die unterbrechungslose Folgeschaltung (54) die Folgesteuerung (41) veranlaßt, den Stromfluß durch die zweite Wicklung (16) in Reaktion auf das Steuersignal (VMC) und das vom Stromfühler (RS) nach dem Überschreiten des Schwellenwertes durch den zweiten Strompegel (IC) generierte Signal (VRS) zu regeln.
  8. Kommutierungsschaltung (31) nach Anspruch 6 oder 7, dadurch gekennzeichnet, daß die unterbrechungslose Folgeschaltung (54) des weiteren einen Folgeschaltungsgenerator (59) enthält, der erste und zweite Anschlüsse hat, wobei der erste Anschluß das Kommutierungssignal (FCOM) aufnimmt, und der zweite Anschluß einen Impuls (END-MBB) für das Ende des unterbrechungslosen Übergangs aufnimmt, der erzeugt wird, wenn der zweite Strompegel (IC) den Schwellenwert überschreitet.
  9. Kommutierungsschaltung (31) nach einem der Ansprüche 6 bis 8, dadurch gekennzeichnet, daß die unterbrechungslose Folgeschaltung (54) des weiteren ein UND-Gatter (57) enthält, von dem ein erster Eingangsanschluß mit dem Ausgangsanschluß des Komparators (51) und ein zweiter Eingangsanschluß mit einem Ausgangsanschluß eines Austastgenerators (55) verbunden ist, und daß ein Eingangsanschluß des Austastgenerators (55) mit dem Ausgangsanschluß des Monoflop (53) verbunden ist, wobei der Austastgenerator (55) während eines vom Monoflop (53) erzeugten Impulses eine logische Eins generiert, wobei die Vorderflanke der logischen Eins nach einer Vorderflanke des vom Monoflop (53) generierten Impulses liegt, und die Hinterflanke der logischen Eins vor einer Hinterflanke des vom Monoflop (53) generierten Impulses liegt, und wobei das UND-Gatter (57) den Impuls (END-MBB) für das Ende des unterbrechungslosen Übergangs liefert.
  10. Kommutierungsschaltung (31) nach einem der Ansprüche 4 bis 9, dadurch gekennzeichnet, daß das Steuersignal (VMC) zur Einstellung der Drehzahl des Motors dient.
Anspruch[en]
  1. A method for commutating an electric motor having first and second windings (14,16) and first and second switches (20d, 20f) for controlling the flow of current through the first and second windings (14,16), respectively, the method comprising:
    • turning the first switch (20d) on to allow a first current (IB) to flow through the first winding (14);
    • after the first current (IB) is flowing in the first winding (14), turning the second switch (20f) on to allow a second current (IC) to flow through the second winding (16), a level of the second current (IC) increasing gradually at least in part as a result of the inductance of the second winding (16);
    • detecting a sum of a level of the first current (IB) and a level of the second current (IC); the method being characterized by
    • turning the first switch (20d) off for a predetermined period of time (TOFF) whenever the sum of the level of the first current (IB) and the level of the second current (IC) exceeds a predetermined threshold level, thereby reducing the sum of the level of the first current (IB) and the level of the second current (IC) to a value below the predetermined threshold level.
  2. The method of Claim 1, further comprising turning the first switch (20d) off for a time period greater than the predetermined period of time when the second current (IC) exceeds the predetermined threshold level, before the predetermined period of time (TOFF) ceases.
  3. The method of Claim 1 or 2, further comprising receiving a commutation signal (FCOM) is turning the second switch (20f) on in response to the commutation signal (FCOM).
  4. A commutation circuit (31) for an electric motor, the electric motor including a first winding (14), a first current switch (20d) for controlling a first current level (IB) through the first winding (14), a second winding (16), and a second current switch (20f) for controlling a second current level (IC) through the second winding (16), the commutation circuit (31) comprising:
    • an input node for receiving a commutation signal (FCOM);
    • a sequencer (41) having a first input terminal connected to the input node and having first and second output terminals (LSB, LSC) connected to the first and second current switches (20d, 20f), respectively, the sequencer (41) for turning off the first current switch (20d) and turning on the second current switch (20f) in response to the commutation signal (FCOM); and
    • a current sensor (RS) for generating a signal (VRS) representative of a sum of the first and second levels (IB, IC); and characterized by
    • a comparator (51) having a first input terminal (+) connected to an output terminal of the current sensor (RS) and a second input terminal (-) connected to a control signal (VMC);
    • a one-shot (53) having an input terminal connected to an output terminal of the comparator (51) and an output terminal connected to a second input terminal of the sequencer (41), the one-shot (53) for generating a series of pulses (PWM) of equal duration, each of the pulses (PWM) causing the sequencer (41) to generate a signal to turn off the first current switch (20d).
  5. The commutation circuit (31) of Claim 1, characterized in that the rate of increase of the second current level is proportional to the inductance of the second winding.
  6. The commutation circuit (31) of any of the Claims 4 to 5, characterized by a make-before-break circuit (54) having an input terminal connected to the output terminal of the comparator (51) and an output terminal connected to a third input terminal of the sequencer (41), the make-before-break circuit (54) for signaling the sequencer (41) when the second current level (IC) exceeds a threshold.
  7. The commutation circuit (31) of Claim 6, characterized in that the make-before-break circuit (54) causes the sequencer (41) to control current flow through the first winding (14) in response to the control signal (VMC) and the signal (VRS) generated by the current sensor (RS) before the second current level (IC) exceeds the threshold; and

       the make-before-break circuit (54) causes the sequencer (41) to control current flow through the second winding (16) in response to the control signal (VMC) and the signal (VRS) generated by the current sensor (RS) after the second current level (IC) exceeds the threshold.
  8. The commutation circuit (31) of Claim 6 or 7, characterized in that the make-before-break circuit (54) further comprises a make-before-break generator (59) having first and second terminals, the first terminal for receiving said commutation signal (FCOM), the second terminal for receiving an end-make-before-break pulse (END-MBB) developed when the second current level (IC) exceeds the threshold.
  9. The commutation circuit (31) of any of the Claims 6 to 8, characterized in that the make-before-break circuit (54) further comprises an AND gate (57) having a first input terminal connected to the output terminal of the comparator (51) and a second input terminal connected to an output terminal of a blanking generator (55), an input terminal of the blanking generator (55) being connected to the output terminal of the one-shot (53), the blanking generator (55) being for generating a logical one during a pulse generated by the one-shot (53), a leading edge of the logical one occurring after a leading edge of the pulse generated by the one-shot (53) and a trailing edge of the logical one occurring before a trailing edge of the pulse generated by the one-shot (53), the AND gate (57) providing the end-make-before-break pulse (END-MBB).
  10. The commutation circuit (31) of any of the Claims 4 to 9, characterized in that the control signal (VMC) is for establishing a rotational speed of the motor.
Anspruch[fr]
  1. Procédé de commutation d'un moteur électrique comportant des premier et second enroulements (14, 16) et des premier et second commutateurs (20d, 20f) en vue de commander la circulation du courant au travers des premier et second enroulements (14, 16), respectivement, le procédé comprenant :
    • la fermeture du premier commutateur (20d) afin de permettre qu'un premier courant (IB) circule au travers du premier enroulement (14),
    • après que le premier courant (IB) circule dans le premier enroulement (14), la fermeture du second commutateur (20f) afin de permettre à un second courant (IC) de circuler au travers du second enroulement (16), un niveau du second courant (IC) augmentant progressivement au moins en partie en raison de l'inductance du second enroulement (16),
    • la détection d'une somme d'un niveau du premier courant (IB) et d'un niveau du second courant (IC), le procédé étant caractérisé par
    • l'ouverture du premier commutateur (20d) pendant un intervalle de temps prédéterminé (TOFF) à chaque fois que la somme du niveau du premier courant (IB) et du niveau du second courant (IC) dépasse un niveau de seuil prédéterminé, en réduisant ainsi la somme du niveau du premier courant (IB) et du niveau du second courant (IC) à une valeur en dessous du niveau de seuil prédéterminé.
  2. Procédé selon la revendication 1, comprenant en outre l'ouverture du premier commutateur (20d) pendant un intervalle de temps supérieur à l'intervalle de temps prédéterminé lorsque le second courant (IC) dépasse le niveau de seuil prédéterminé, avant que l'intervalle de temps prédéterminé (TOFF) ne cesse.
  3. Procédé selon la revendication 1 ou 2, comprenant en outre le fait que la réception d'un signal de commutation (FCOM) ferme le second commutateur (20f) en réponse au signal de commutation (FCOM).
  4. Circuit de commutation (31) destiné à un moteur électrique, le moteur électrique comprenant un premier enroulement (14), un premier commutateur de courant (20d) destiné à commander un premier niveau de courant (IB) au travers du premier enroulement (14), un second enroulement (16), et un second commutateur de courant (20f) destiné à commander un second niveau de courant (IC) au travers du second enroulement (16), le circuit de commutation (31) comprenant :
    • un noeud d'entrée destiné à recevoir un signal de commutation (FCOM),
    • un séquenceur (41) comportant une première borne d'entrée reliée au noeud d'entrée et comportant des première et seconde bornes de sortie (LSB, LSC) reliées aux premier et second commutateurs de courant (20d, 20f), respectivement, le séquenceur (41) étant destiné à ouvrir le premier commutateur de courant (20d) et à fermer le second commutateur de courant (20f) en réponse au signal de commutation (FCOM), et
    • un capteur de courant (RS) destiné à générer un signal (VRS) représentatif d'une somme des premier et second niveaux (IB, IC), et caractérisé par
    • un comparateur (51) comportant une première borne d'entrée (+) reliée à une borne de sortie du capteur de courant (RS) et une seconde borne d'entrée (-) reliée à un signal de commande (VMC),
    • un circuit monostable (53) comportant une borne d'entrée reliée à une borne de sortie du comparateur (51) et une borne de sortie reliée à une seconde borne d'entrée du séquenceur (41), le circuit monostable (53) étant destiné à générer une série d'impulsions (PWM) de durée égale, chacune des impulsions (PWM) amenant le séquenceur (41) à générer un signal pour ouvrir le premier commutateur de courant (20d).
  5. Circuit de commutation (31) selon la revendication 1, caractérisé en ce que la vitesse d'augmentation du second niveau de courant est proportionnelle à l'inductance du second enroulement.
  6. Circuit de commutation (31) selon l'une quelconque des revendications 4 à 5, caractérisé par un circuit de commutation avec chevauchement (54) ayant une borne d'entrée reliée à la borne de sortie du comparateur (51) et une borne de sortie reliée à une troisième borne d'entrée du séquenceur (41), le circuit de commutation avec chevauchement (54) étant destiné à signaler au séquenceur (41) lorsque le second niveau de courant (IC) dépasse un seuil.
  7. Circuit de commutation (31) selon la revendication 6, caractérisé en ce que le circuit de commutation avec chevauchement (54) amène le séquenceur (41) à commander la circulation du courant au travers du premier enroulement (14) en réponse au signal de commande (VMC) et au signal (VRS) généré par le capteur de courant (RS) avant que le second niveau de courant (IC) ne dépasse le seuil, et

       le circuit de commutation avec chevauchement (54) amène le séquenceur (41) à commander la circulation du courant au travers du second enroulement (16) en réponse au signal de commande (VMC) et au signal (VRS) généré par le capteur de courant (RS) après que le second niveau de courant (IC) dépasse le seuil.
  8. Circuit de commutation (31) selon la revendication 6 ou 7, caractérisé en ce que le circuit de commutation avec chevauchement (54) comprend en outre un générateur de commutation avec chevauchement (59) comportant des première et seconde bornes, la première borne étant destinée à recevoir ledit signal de commutation (FCOM), la seconde borne étant destinée à recevoir une impulsion de fin de commutation avec chevauchement (END_MBB) développée lorsque le second niveau de courant (IC) dépasse le seuil.
  9. Circuit de commutation (31) selon l'une quelconque des revendications 6 à 8, caractérisé en ce que le circuit de commutation avec chevauchement (54) comprend en outre une porte ET (57) ayant une première borne d'entrée reliée à la borne de sortie du comparateur (51) et une seconde borne d'entrée reliée à une borne de sortie d'un générateur d'impulsions de suppression (55), une borne d'entrée du générateur d'impulsions de suppression (55) étant reliée à la borne de sortie du circuit monostable (53), le générateur d'impulsions de suppression (55) étant destiné à générer un état logique un durant une impulsion générée par le circuit monostable (53), un front avant de l'état logique un apparaissant après un front avant de l'impulsion générée par le circuit monostable (53) et un front arrière de l'état logique un apparaissant avant un front arrière de l'impulsion générée par le circuit monostable (53), la porte ET (57) fournissant l'impulsion de fin de commutation avec chevauchement (END_MBB).
  10. Circuit de commutation (31) selon l'une quelconque des revendications 4 à 9, caractérisé en ce que le signal de commande (VMC) est destiné à établir une vitesse de rotation du moteur.






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