PatentDe  


Dokumentenidentifikation EP0664545 05.07.2001
EP-Veröffentlichungsnummer 0664545
Titel Verfahren und Vorrichtung zur Verwaltung von Meldungen
Anmelder Information Storage Devices, Inc., San Jose, Calif., US
Erfinder Jarrett, Boyce W., Austin, Texas 78736, US;
Khan, Sakhawat M., Santa Clara, California 95051, US;
Nataraj, Bindiganavale S., San Jose, California 95148, US
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69427342
Vertragsstaaten DE, FR, GB, IT, NL
Sprache des Dokument EN
EP-Anmeldetag 01.11.1994
EP-Aktenzeichen 943080275
EP-Offenlegungsdatum 26.07.1995
EP date of grant 30.05.2001
Veröffentlichungstag im Patentblatt 05.07.2001
IPC-Hauptklasse G11C 27/00

Beschreibung[en]
BACKGROUND OF THE INVENTION 1. Field of the Invention:

The present invention relates to the field of solid state message storage and playback devices, such as voice signal storage and playback.

2. Prior Art:

Message management, (more popularly known as "Garbage Collection"), is normally used to make more efficient use of a limited amount of expensive storage medium. The key concept behind garbage collection is to somehow logically connect all the available storage space into one contiguous space, even though the available storage space is physically fragmented in the storage medium. There are various techniques used in computer systems for the mass storage and retrieval of data files, with the garbage collection capability normally being provided by the operating system.

The present message management methods and apparatus are specifically intended for use in a solid state voice messaging chip where voice messages are stored in a solid state memory medium. More specifically, the preferred embodiment of the present invention is intended for use in integrated circuit form realized at least in part as part of analog storage devices of the type manufactured by Information Storage Devices of San Jose, Calif. By way of specific example, the ISD 1016 Single Chip Voice Message System is an analog storage device which has the capability of sequentially sampling and storing in analog voltage level form, an analog signal such as a voice signal, and playing back the stored samples on command so as to reconstruct the voice signal with sufficient fidelity to provide quality voice message annunciation for phone answering machines and other electronically controlled voice message systems. The ISD 1016 is a highly versatile device, as it includes as part of the integrated circuit a preamp, AGC, anti-aliasing filter and nonvolatile solid state analog signal storage as well as all support circuitry required to sample and store a voice signal in analog form, and to play the same back on command. These devices may also be cascaded so that n devices may be used to provide n times the record and playback time of a single device without additional support circuitry.

In the ISD 1016, a voice message may terminate at the end of the storage space, or be earlier terminated by the recording of a unique end of message (EOM) signal which, once initiated, will terminate the playback at that point. This, plus the ability to address starting points for playback, allows the storage and selective playback of multiple messages, and with additional control, the concatenation of words or short phrases to give different messages if desired. However, each message or message segment to be concatenated with another message segment must be in contiguous storage space, as the ISD 1016 cannot concatenate message segments in different memory space with a single starting signal. By way of specific example, if one recorded as the first message on an answering machine:

   "Sorry, we are currently not in the office. Please leave a message following the beep."

and a second message:

   "Sorry, we are closed. Our normal hours are 8 to 5 weekdays. Please leave a message at the beep and we will return your call on our next business day."

a simple two state signal could select between the two messages. However if the first message was later changed to:

   "Sorry, we are currently not in the office. Please leave a message following the beep, or call our other office at 123-4567."

it would likely overrun the second message, requiring re-recording of the second message also. Thus, for applications wherein individual messages are to be selectively eliminated and new messages of variable length are to be recorded from time to time, a simple method and apparatus is desired to manage the memory space in a manner transparent to those recording and those playing back the remaining messages.

The ISD 1016 Single Chip voice Message System is described in an article entitled "Analogue Data Storage - Speaking of the Future?" by A. Wright in Electronics world + Wireless World, Vol. 97 (1992) Feb, No. 1671, pp. 110-113. The Wright article shows a schematic diagram of the ISD 1016 chip in Figure 1, and describes the components therein. Central to the ISD 1016 Chip is an analog storage array which stores samples of an analog signal, and is divided into 160, 800 cell segments, where each segment stores a 100 ms signal.

US Patent No. 4, 780,855 describes a system for controlling a non-volatile memory to provide a large number of writing cycles. The non-volatile memory is divided into logical memory blocks each including a plurality of message segments each having a data memory area and an identifier. Only one message segment in a logical memory block can be programmed with valid data at any one time. When a message segment holds valid data, the corresponding identifier is set to "1". When data are re-written to memory, the identifier corresponding to the previously written memory segment is set to "0", the data is written in the next memory segment, and the associated identifier is set to "1". This technique ensures that different message segments in the logical memory blocks hold data, thereby distributing write cycles evenly across the memory segments to maximise the life of the non-volatile memory.

From UK patent application GB - A - 2 253 078, which discloses the features in the preambles of the independent claims, an apparatus for the storage and playback of spoken messages is known. The messages are stored in a RAM such that individual messages within a sequence may easily be selected and played back. The disclosed device is intended to replace conventional pocket tape dictation machines. User buttons allow replay previous, current or next message or to erase selected messages. Message identifiers, registers and a stack pointer are used to manage the stored texts ("slots"), which may be different in length. However, a message can only be stored in a single message slot or as one record. This technique is inefficient and problematic since the memory becomes fragmented after messages are recorded, erased etc. Consequently memory management is required. The document is silent on how the memory fragmentation can be solved.

BRIEF SUMMARY OF THE INVENTION

Message management methods and apparatus for the storage and selective playback, erase and other manipulation of messages such as voice messages in a voice message system are disclosed.

The apparatus and method of the present invention are set forth in the appended claims.

Other aspects of the invention, including other features and capabilities of the devices and details of the method are disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram of a preferred embodiment of the present invention.

Figure 2 illustrates the linking of the stack registers of each device to a respective addressable message segment.

Figure 3 is a circuit diagram showing the signal connections for a cascaded system comprising a microcontroller and a plurality of cascaded analog storage and playback devices.

Figure 4 is a circuit diagram similar to Figure 3 showing the signal connections for a system comprising a microcontroller and a single analog storage and playback device.

DETAILED DESCRIPTION OF THE INVENTION

As stated before, the present message management method and apparatus are specifically intended for use in a solid state voice messaging chip wherein voice messages are stored in a solid state memory medium. More specifically, the preferred embodiment of the present invention is intended for use in integrated circuit form realized at least in part as part of analog storage devices of the type manufactured by Information Storage Devices of San Jose, Calif. In the description to follow, first an overview of the message management method and apparatus will be described, and then details of a preferred implementation will be described.

Now referring to Figure 1, a block diagram of a preferred embodiment of the present invention may be seen. The heart of the storage device is a nonvolatile storage array 20, in this embodiment capable of storing in analog sample form and playing back, ten minutes of analog (audio or speech) information sampled at a 6.4 KHz rate. For recording, a microphone, telephone speaker signal or corresponding signal is applied through one of the preamp inputs PREIN1 or PREIN2 to the preamplifier 22 through multiplexer 24 controlled by the address/configuration/control logic 26. The output of the preamp 22 is coupled to an output pin ANAOUT, which in turn is normally capacitively coupled through an external capacitor to the input ANAIN of a fixed gain amplifier 28, the output of which is provided to the automatic gain control (AGC) circuit 30, controlling the gain of the preamp 22. The output of amplifier 28 is also coupled to antialiasing filter 32, the function of which is to limit the upper frequency of the audio (or other analog) signal so that the signal frequency range does not violate the sampling theorem for the analog signal sampling and storing in the non-volatile storage 20. Alternatively of course, the audio signal input may be applied directly through the ANAIN terminal to the input of the fixed gain amplifier 28 if the audio signal has been properly pre-conditioned to be of appropriate amplitude, etc.

For both recording and playback, an internal clock source 34 provides a reference clock signal to the timing/sequencer circuit 36 which controls the sampling clock 38 to sample the analog signal from the antialiasing filter 32 at an appropriate audio signal reproduction rate and in conjunction with other circuitry on the chip, sequences the sampling of the audio signal and the storage thereof during recording and during playback of the recorded analog signal samples. During playback, the stored analog voltages are read from the non-volatile analog storage 20 at the same rate as they were taken and passed through a smoothing filter 40 and analog mixer 42 to provide the output signal AUXOUT. The output of mixer 42 is also coupled to a multiplexer 44 as is an auxiliary input AUXIN, the multiplexer 44 selecting between these two signals to drive a power amplifier 46. having a balanced output to directly drive a speaker if desired.

In the preferred embodiment, because of the similar characteristics desired and the circuit savings which result, the antialiasing filter 32 is actually switched between the input during recording and the output during playback so that the antialiasing filter 32 becomes the smoothing filter 40 during playback. In addition, high voltage generating circuits 48 for programming (recording) and erasing of the storage cells on chip (both analog and digital storage cells) are also provided on chip so that external high voltage power supplies are not required.

The foregoing general types of devices are described in U.S. Patent Nos. 4,890,259 and 4,989,179. Further details may be found in U.S. Patent No. 5,241,494, with details of various circuits used therein being shown in U.S. Patent Nos. 5,126,967, 5,220,531 and 5,243,239. Finally, cascading of such devices to extend the record and playback time is shown in U.S. Patent No. 5,164,915, and a one-transistor non-volatile floating gate storage cell usable in an advanced version of such devices is shown in U.S. Patent No. 5,294,819.

The key features of this invention are that; a), message management can be performed through references to message or message segment numbers, and b), under the supervision of a conventional microcontroller or microprocessor, one can accomplish all the message management functions found in voice messaging systems, (i.e., telephone answering machines) by operating on a fixed number of read/write registers, e.g., selective save and delete of messages, skip forward or backward from message to message, re-numbering of messages, looping on messages, selective record and playback of messages by numbers, tagging of new messages, etc.

Referring again to Figure 1, nonvolatile read/write registers form a stack in logic 26 in each analog storage device. The message management functions are performed through the manipulation of the message numbers in the stack registers. For example, in a telephone answering machine application, callers normally leave audio messages and the recipient listens to the messages and discretely saves or deletes some or all of these messages. The messages are normally numbered in an ascending order, e.g., lowest number representing the earliest message received and the highest number representing the latest message received or vice-a-versa. During the normal course of time, as the user saves and deletes messages and receives still further messages, the available storage space for recording new messages gets fragmented (not contiguous any more, but scattered across the storage media in small segments). To make efficient use of the storage medium (the ability to use the total available recordable space at any time even though fragmented), the present invention message management is used to convert this fragmented recordable space into one contiguous logical space without physically relocating messages and without packing the available fragmented space into one contiguous space.

In the description presented herein, the following definitions apply:

  • 1. Message Segments: The smallest addressable message or piece of a message. Each message segment has a respective register linked to it that may be written to, to hold a message number for later reference. The set of registers in a single analog storage device is referred to as a stack in this description.
  • 2. Message: All or part of one or more message segments. A unique number is associated with each message. The number of possible messages is determined by the number of addressable message segments and the size of the register linked to each message segment. The size of the register means the number of individual storage cells forming the register, e.g., byte-wide means eight cells per register, capable of holding any of 256 numbers 0 through 255.
  • 3. Message Number: A numerical reference to a message. One or more message segments may have the same message number. Contiguous or non-contiguous message segments may have the same message number. Message segments with the same message number (contiguous or non-contiguous), concatenated in a physical order, collectively form a message.
  • 4. Stack Pointer: A pointer, one of which is associated with each register in a stack and used to directly address any message segment. The size of the stack pointer is that necessary to address the number of message segments in the system.
  • 5. Message Stack: The message stack are the registers linked to each respective message segment. The depth of the message stack is the number of message segments in each device.
  • 6. Overflow: Occurs whenever an attempt is made to address past the end of the stack. This may happen either through an internal operation of the system, or if addressed through the stack pointer.
  • 7. Register: A register is a collection of memory cells, e.g., a byte wide register has eight memory cells that can be written to or read from simultaneously. These registers can be volatile or non-volatile.

The key to the method of the present invention is to work with a reasonable number of message segments. Assume that a device having a 10 minute storage capability at a sample rate of 6.4 KHz is used, that the maximum number of message segments is 234, and that a message segment, typically of the order of 2 sec. to 4 sec. in duration, is actually 2.54 sec. in duration (2.54 sec. per segment times 234 segments = 10 minutes recording time). A message stack is required to keep track of these message segments. The stack should be wide enough to hold the maximum message segment number count (note that this maximum message segment count is also the maximum number of messages possible, for a single device, though alternatively a device could be designed with substantially cascading in mind where the total number of messages could exceed the number of message segments in one device, thereby calling for a nine or ten bit wide or wider stack.) In the embodiment being described, the stack is byte-wide, since there is 234 message segments on chip. The depth of the stack, which also means the total number of registers in the stack, should be equal to the total number of individually addressable message segment locations within a particular device, and the stack should be preferably a linear stack. Each register in the stack is linked to a respective addressable message segment, as shown in Figure 2. Preferably the top register of the stack is linked to the first addressable message segment, the second stack register is linked to the second physical message segment etc., with the bottom stack register being linked to the last addressable message segment. The link between stack registers and physical message segment locations can be in any order desired, so long as it is fixed or predetermined.

Alternatively, a circular stack could be used if flag bits are used in the stack registers to signify the beginning and ending message segments of messages on a device.

Now referring to Figure 3, the signal connections for a cascaded system comprising a microcontroller 60 and a plurality of cascaded analog storage and playback devices 62, 64 and 66 may be seen. As shown in Figure 3, microcontroller 60 is connected in parallel to the four SPI port connections of each of the cascaded devices. Accordingly all control registers in the devices are set to the same conditions (or under certain circumstances, to different conditions) by the microcontroller, which typically operates on a program stored in read only memory (ROM) or EPROM or EEPROM. For recording, the analog signal IN on line 68, in a telephone answering machine the equivalent of the handset speaker signal, is capacitively coupled to the input of preamp 22 (Figure 1) through connection PREIN of the first analog storage device. The preamp 22 and AGC circuit 30, the parameters of which are set by the external resistor-capacitor network 70, provides an amplitude controlled signal on the analog output ANAOUT pin of the first device, which in turn is capacitively coupled to the analog in connection ANAIN of all devices in parallel. Thus, with this connection, the preamp and AGC circuit of the first device provides the same amplitude controlled analog signal to all devices.

For playback, on the other hand, it will be noted that for all devices other than the first, the positive speaker output SP+ for each device is connected to the auxiliary input AUXIN for the prior device, thus daisy-chaining the devices in the reverse order, with the ultimate output of the cascaded devices being derived from the first device 62, typically in the form of a balanced output as shown. In that regard, when a particular device is itself playing back an analog signal stored in its own analog storage cells, multiplexer 44 will select as the input to the speaker amplifier 46 the output of the smoothing filter 40. At the end of its playback, which depending upon its mode of operation in accordance with the present invention, may be a playback of the last message segment in the storage device or alternatively the playback of the last message segment in the storage device having the message number commanded to be played back by the microcontroller, the input to the speaker amplifier 46 is switched by the multiplexer 44 to the auxiliary input connection AUXIN. This, coupled with the unity gain of the speaker amplifiers 46 in each device and the reverse daisy-chaining of the devices, results in the output signal of a device currently playing back being daisy-chained to the first device to provide the output signal OUT as shown. While the speaker amplifier 46 (Figure 1) is a balanced output, the same may be used as a single ended output if desired.

It will be noted that while the four SPI bus lines are in parallel to all devices, the CASCADE connection of only the first device is coupled to the microcontroller 60. Thereafter, each device has its CASCADE connection connected to the overflow OVF of the prior device, thus daisy-chaining all devices, so that while the microcontroller may set up all devices for either record or playback, it will trigger the operation initially of only the first device through the CASCADE connection. When the stack pointer hits the bottom of the stack in the first device, a stack overflow OVF is triggered. This overflow is communicated to the next device, if a plurality of storage devices are used as shown, triggering the stack pointer in the next device.

The data loaded in the stack registers is the binary equivalent of message numbers. There also is a binary equivalent code for the designation of a vacant message segment, preferably 00h (h => hexadecimal numbering system). In the beginning when the entire storage space is empty (or cleared), the 00h code is intentionally set in all of the stack register locations to indicate all are available for recording purposes. However after a few record and erase operations, wherein in the erase operations the stack registers for the respective message segments are reset to 00h to indicate a corresponding empty message segment storage location, these empty locations will be somewhat randomly distributed (fragmented) throughout the stack (or plurality of stacks of an equal number of identical concatenated storage devices), as stated earlier, thereby necessitating the garbage collection capability. Before a recording can begin, the stack pointer (counter) in the storage device or the first storage device in a chain of such devices, (which also represents the physical address for the message segment), starts stepping down the stack until a location with 00h therein is found. At this point the message number of the current message is stored in this location and the recording begins at the pointed-to physical message segment location. After the message recording begins at that segment, the pointer continues a look-ahead search down the stack to locate another empty message segment position as will be indicated by a 00h code in the respective empty stack register. If the pointer finds a register with 00h therein, it stays at this location until the previous segment gets filled, at which time the message number is stored in the current stack register and the recording continues transparently at the presently pointed to message segment. The pointer then moves on, looking ahead for still another empty 00h location in the stack. This continues until the stack pointer hits the bottom of the stack and an overflow trigger is generated. If only a single storage device is used, this will stop the recording. If a plurality of devices are used as shown in Figure 3, the overflow is coupled to the next device and the stack pointer therein repeats the process described for that device, etc. until the last device in the chain is reached. The recording can also be stopped anytime before the last overflow is reached, as is normally most likely, by a normal end of record operation triggered by the microcontroller in response to some operating parameter or characteristic of the system, such as in a telephone answering machine a detected hangup by the caller, a lack of a cadence signal from the first analog storage device in the chain, or a message length limit from a timeout of the microcontroller. In this case, an EOM (End-Of-Message) marker is written at the point in the segment where the recording ended. The EOM markers are digital markers which may be stored in memory cells provided on each analog storage device just for that purpose. Such markers are used in the ISD 1016 device, and described in the literature thereon, and in detail in U.S. Patent No. 5,241,494.

To play a message, the microcontroller provides the message number to all devices 62, 64 and 66 over the SPI bus, and initiates a play operation in device 62 by a signal on the cascade line. The stack pointer in the first device 62 starts from top of the stack and steps down until the message number in the associated stack register compares with the message number initially provided over the SPI bus. The playback is performed from this message location as the stack pointer continues a look-ahead for the next stack location with the same message number. If it finds one, it stops at that location until the previous message segment play is completed, at which time the present segment pointed to immediately begins playing in a seamless manner transparent to the listener. As this segment starts playing back, the pointer then moves further down the stack, etc., until the bottom of the stack is hit and the overflow is triggered. Note that the playback may stop any time earlier by the detection of the EOM bit, at which time the playback operation is complete and thus stops. When the overflow is triggered, it provides the initiating cascade signal to the second device 64, which in turn will replay all its message segments of the same number, etc. until either an end of message EOM signal is found in one of the devices for this message number, or alternatively, all message segments of the same message number in all devices have been replayed in order.

This play operation with the stack is very similar to the record operation, with the difference that during recording the stack pointer looks ahead searching for the empty (OOh) code and then loads the message number in place of the empty code, whereas during playback the stack pointer is looking ahead searching for the specific (non-00h) message number.

In both the record and playback operations, the look-ahead is done at digital speeds, not analog (voice) rates. Consequently many devices may be cascaded in a relatively large system and the first segment of a particular message actually stored in one of the later devices, yet the time to locate the first message segment will be sufficiently short so as to be transparent to the user. Similarly, of course, during recording, a large number of devices may be searched for the next stack register containing 00h, so that even if the next segment to be stored can only be stored many devices down the cascaded string, the same will be ready to transparently start recording as soon as the current segment recording is completed, and during playback, the resulting physically disparate message segments may be seamlessly located and sequentially played back in a manner transparent to the user.

An erase of a certain message may be performed by providing the message number to all devices through the SPI bus and then initiating an erase operation. At this time the stack pointer sequentially steps through the stack in each device, as in a record and playback operations, and locates all the locations which have the message number and writes the empty code OOh. One does not have to erase the array, as writing the empty code OOh into the proper stack register locations essentially releases the associated storage area of the device for further writing, and like the ISD 1016 device hereinbefore referred to, writing is always immediately preceded by a single pulse erase cycle to clear the associated storage cells for the storage of the new message segment. Note in this regard, the empty code is stored in a digital storage space, not an analog storage space, so that this writing operation is a fast one shot storage operation rather than the iterative write of the analog storage of the ISD 1016 type devices.

Reordering of message numbers can be permanently performed by the microcontroller by changing the message numbers in the stack registers appropriately, or temporarily in memory associated with the controller. No physical transfer of messages is required in the array. Skipping forward messages can be initiated by the microcontroller by loading a message number other than that of the first message and requesting a play operation. Repeating earlier messages can also be initiated by the microcontroller by loading in the message number and requesting a play operation. Playback of all messages can be also be performed by the microcontroller through iteratively incrementing the message number with each request of a play operation until the final message play request is complete. Selective erase and save can also be performed by the microcontroller by just changing the message numbers in the stack to 00h for the messages that are to be deleted. A message can be appended to a previous message by requesting a record operation with the same message number to which message appending is required, and then appending the new message after the last message segment of the previous message. In that regard the microcontroller may read or write to the stack pointers at any time, and therefore can determine where all message segments of a given message are, thus giving the overall system great flexibility and versatility, such as concatenating messages, splitting a message to inject inserts, etc.

For looping on a message, the microcontroller provides the message number and initiates a loop play operation. The stack pointer in this mode essentially starts from the top of the stack and plays all the segments with the selected message number and jumps back to the top and repeats this sequence until the operation is stopped. Hard message segment boundaries can be set up by programming the appropriate segment numbers into the proper stack registers and never changing it again. This for instance, could be used in an answering machine where the answering message is to be protected from write-overs, even though other old messages are to be written over. Additionally, the message pointer can be moved backward from segment to segment, or caused to move back n segments at a time to allow reviewing/rewinding of messages or message portions, such as the repeat of a phone number to allow writing down and verification of the number without requiring replay of the entire message or message list. Specific single or multiple bits of the stack registers can be set aside for the purpose of setting special flag information, e.g. old or new messages, private message, urgent message, saved message, etc. Note that when some bits of the stack register are to be set aside for flag information, the maximum number of addressable messages will be determined by the number of stack register bits left for message number identification purpose. The sum of the flag bits and the message number bits will make up the total width of the stack register.

Having now described the operation of the device of the present invention in a generalized cascaded system of n devices, it will be apparent that substantially any number of such devices may be cascaded as desired. In the event that the number of devices to be cascaded exceeds the number of available individual port lines on the microcontroller to be used, one or more groups of m port lines may be used for providing up to 2m binary coded SS signals which are decoded to accommodate up to 2m cascaded devices. Also from the prior description, it will be apparent that the number of "cascaded" devices may simply be one, as shown in Figure 4, with all of the various functions and capabilities of a larger system being preserved, albeit with a lower total recording and playback time capability.

The present invention has to this point been described in term of a voice messaging system. It should be noted however, that the messages could be in the form of data messages. In particular, the present invention could also be used for managing data files as normally found in computer file systems and solid state data storage systems, particularly such systems as are or may be required to handle files of variable length. In the case of data in the preferred embodiment, the data may be conventionally binary encoded as high and low voltages, or higher order multilevel voltages may be used. By way of example, four voltage levels may be used to effectively store two bits per memory cell.


Anspruch[de]
  1. Ein Speicherbauelement in integrierter Schaltungstechnik zum Speichern und selektiven Wiedergeben von Nachrichten, aufweisend:
    • ein Speicher-Array (20) mit einer Vielzahl von Speicherzellen;
    • eine Eingabeschaltung (22, 24, 28, 30, 32) zum sequentiellen Bereitstellen von Eingabeinformationen an die Speicherzellen, um sie darin während einer Aufzeichnungsoperation zu speichern;
    • Ausgabeschaltungen (40-46) zum sequentiellen Bereitstellen von in den Speicherzellen gespeicherten Informationen als Ausgabesignal während einer Wiedergabeoperation; gekennzeichnet durch:
    • eine Mehrzahl von Registern, wobei jedes Register jeweils einer Serie von Speicherzellen in dem Speicher-Array zugeordnet ist und in der Lage ist, einen Nachrichtenidentifizierer zu speichern; gekennzeichnet durch:
    • eine Kommunikationsschaltung (56) zum Empfangen von Steuersignalen, die von außen der Schaltung zugeführt werden;
    • eine Stapelzeiger- und Steuerschaltung (26), die auf die Kommunikationsschaltung anspricht, zum sequentiellen Lokalisieren jedes sukzessiven, den von der Kommunikationsschaltung spezifizierten speziellen Nachrichtenidentifizierer speichernden Registers und zum Veranlassen der Ausgangsschaltung, nahtlos während einer Wiedergabeoperation in der jeweiligen Serie von Speicherzellen, die den jeweiligen, den speziellen Nachrichtenidentifizierer speichernden sukzessiven Registern zugeordnet sind, gespeicherten Informationen als Ausgabe zur Verfügung zu stellen.
  2. Das Speicherbauelement in integrierter Schaltungstechnik nach Anspruch 1, wobei die Stapelzeiger- und Steuerschaltung (26) ferner auf die Kommunikationsschaltung (56) während einer Löschoperation anspricht, um Register zu lokalisieren, die einen speziellen Nachrichtenidentifizierer enthalten, und um bei diesen Registern diesen speziellen Nachrichtenidentifizierer durch einen Referenzidentifizierer zu ersetzen.
  3. Das Speicherbauelement in integrierter Schaltungstechnik nach Anspruch 2, wobei die Stapelzeiger- und Steuerschaltung (26) ferner auf die Kommunikationsschaltung (56) während einer Aufzeichnungsoperation anspricht, um sukzessive Register zu lokalisieren, die den Referenzidentifizierer enthalten, um sequentiell Eingabeinformationen an die Serie von Speicherzellen bereitzustellen, die den Registern zugeordnet sind, und um den Referenzidentifizierer in den jeweiligen Registern durch einen speziellen Nachrichtenidentifizierer zu ersetzen.
  4. Das Speicherbauelement in integrierter Schaltungstechnik nach Anspruch 3, ferner bestehend aus einer Kaskadenschaltung und einer Überlaufschaltung, wobei die Kaskadenschaltung auf ein externes Signal zum Initiieren einer Lese- oder Schreiboperation innerhalb der integrierten Schaltung, wie sie über die Kommunikationsschaltung angewiesen wird, anspricht, und wobei die Überlaufschaltung ein Signal zur Verfügung stellt, das mit der Kaskadenschaltung einer identischen integrierten Schaltung koppelbar ist, um nahtlos eine Lese- oder Schreiboperation darin zu initiieren, nachdem die Stapelzeiger- und Steuerschaltung sämtliche Register durchsucht hat, um sequentiell jedes sukzessive Register zu lokalisieren, das den durch die Kommunikationsschaltung für die Lese- oder Schreiboperation spezifizierten speziellen Nachrichtenidentifizierer speichert.
  5. Das Speicherbauelement in integrierter Schaltungstechnik nach einem der Ansprüche 1 bis 4, wobei die Kommunikationsschaltung (56) auf einen externen Mikrocontroller anspricht.
  6. Das Speicherbauelement in integrierter Schaltungstechnik nach einem der Ansprüche 1 bis 4, wobei die Eingabeinformation ein analoges Signal ist, wobei das Speicherarray ein Analogspannungsspeicherarray ist und die Eingabeschaltung Abtast- und Halteschaltungen zum periodischen Abtasten eines analogen Signals zur Speicherung der Abtastwerte in dem Analogspannungsspeicherarray enthält.
  7. Das Speicherbauelement in integrierter Schaltungstechnik nach Anspruch 6, wobei die Kommunikationsschaltung (56) auf einen externen Mikrocontroller anspricht.
  8. Das Speicherbauelement in integrierter Schaltungstechnik nach einem der Ansprüche 1 bis 4, wobei die Nachricht digitale Informationen umfaßt.
  9. Das Speicherbauelement in integrierter Schaltungstechnik nach Anspruch 1, wobei jede Speicherzelle dem Speichern eines Abtastwertes einer Vielzahl aufeinanderfolgender Abtastwerte von Audiosignalen in Form einer analogen Spannung dient, wobei die

       Eingangsschaltung zum sequentiellen Empfangen eines Audiosignals und zum Bereitstellen sequentieller Abtastwerte davon für die Speicherzellen zur Speicherung in diesen während einer Aufzeichnungsoperation dient, und wobei die Ausgabeschaltung zum sequentiellen Bereitstellen von Abtastwerten des Audiosignals, die in den Speicherzellen gespeichert sind, als Ausgangssignal während einer Wiedergabeoperation dient.
  10. Das Speicherbauelement in integrierter Schaltungstechnik nach Anspruch 2, wobei der Referenzidentifizierer ein digitaler Referenzidentifizierer ist.
  11. Das Speicherbauelement in integrierter Schaltungstechnik nach Anspruch 1, wobei jedes Register in der Lage ist, den Nachrichtenidentifizierer in digitaler Form zu speichern.
  12. Ein Verfahren zum Aufzeichnen und Wiedergeben von Nachrichten variierender Länge, umfassend die Schritte:
    • (a) Bereitstellen eines eine Speicherkapazität aufweisenden Speichermediums (20), durch welches eine Vielzahl von Nachrichten gespeichert werden können;
    • (b) Bereitstellen einer Mehrzahl von Registern und Zuordnen jedes Registers zu einem zugehörigen Abschnitt des Speichermediums, in welchem ein Nachrichtensegment gespeichert werden kann; gekennzeichnet ferner dadurch, daß es die Schritte umfaßt:
    • (c) daß für das Aufzeichnen einer Nachricht sukzessive Register lokalisiert werden, in denen ein Referenzidentifizierer gespeichert ist, der darin gespeicherte Referenzidentifizierer durch einen speziellen Nachrichtenidentifizierer ausgetauscht wird und Segmente der Nachricht gespeichert werden, bis die vollständige Nachricht gespeichert ist;
    • (d) daß bei der Wiedergabe einer speziellen Nachricht sukzessive Register lokalisiert werden, die den speziellen Nachrichtenidentifizierer speichern, und die zugehörigen Nachrichtensegmente in ihrer Reihenfolge wiedergegeben werden, bis die vollständige Nachricht wiedergegeben ist.
  13. Das Verfahren zum Aufzeichnen und Wiedergeben von Nachrichten variierender Länge nach Anspruch 12, ferner umfassend die Beseitigung einer aufgezeichneten Nachricht, umfassend den Schritt des:

       sukzessiven Lokalisierens von Registern, in denen der Nachrichtenidentifizierer für die zu beseitigende Nachricht gespeichert ist, und Ändern des Nachrichtenidentifizierers auf den Referenzidentifizierer in diesen Registern.
  14. Das Verfahren nach einem der Ansprüche 12 oder 13, wobei in den Schritten a) und b) das Speichermedium und die Mehrzahl von Registern eine Mehrzahl integrierter Schaltungen umfaßt, wobei jede der integrierten Schaltungen einen entsprechenden Abschnitt der Speicherkapazität aufweist und einen entsprechenden Anteil der Register enthält.
  15. Das Verfahren nach Anspruch 14, wobei jede integrierte Schaltung ein mit der nächstnachfolgenden integrierten Schaltung koppelbares Signal zur Verfügung stellt, um nahtlos einen Aufzeichnungs-, Wiedergabe- oder Nachrichtenbeseitigungsprozeß in der nächstnachfolgenden integrierten Schaltung bei Abschluß desselben in der vorhergehenden integrierten Schaltung zu initiieren.
  16. Das Verfahren nach Anspruch 14, wobei die Nachrichten Sprachnachrichten sind.
  17. Das Verfahren nach Anspruch 14, wobei die Nachrichten digitale Informationen darstellen.
Anspruch[en]
  1. An integrated circuit storage device for storing and selective playback of messages comprising:
    • a storage array (20) having a plurality of storage cells;
    • input circuitry (22,24,28,30,32) for sequentially providing input information to the storage cells for storage therein during a record operation;
    • output circuitry (40-46) for sequentially providing during a playback operation, information stored in the storage cells as an output; characterised by:
    • a plurality of registers, each register being associated with a respective series of storage cells of the storage array and capable of storing a message identifier; characterised by:
    • communication circuitry (56) for receiving control signals from outside the circuit;
    • stack pointer and control circuitry (26) responsive to the communication circuitry for sequentially locating each successive register storing the specific message identifier specified by the communication circuitry and causing the output circuitry to seamlessly provide during a playback operation, information stored in the respective series of storage cells associated with each successive register storing the specific message identifier as an output.
  2. The integrated circuit storage device of claim 1 wherein the stack pointer and control circuitry (26) is further responsive to the communication circuitry (56) during an erase operation to locate registers having a specific message identifier therein and for those registers, to replace that specific message identifier with a reference identifier.
  3. The integrated circuit storage device of claim 2, wherein the stack pointer and control circuitry (26) is further responsive to the communication circuitry (56) during a record operation to successfully locate registers having the reference identifier therein, to sequentially provide input information to the series of storage cells associated with those registers, and to replace the reference identifier in the respective registers with a specific message identifier.
  4. The integrated circuit storage device of claim 3, further comprised of cascade circuitry and overflow circuitry, the cascade circuitry being responsive to an external signal to initiate a read or write operation within the integrated circuit as directed through the communication circuitry, and the overflow circuitry providing a signal coupleable to the cascade circuitry of an identical integrated circuit for seamlessly initiating a read or write operation therein after the stack pointer and control circuitry has searched all registers to sequentially locate each successive register storing the specific message identifier specified by the communication circuitry for the read or write operation.
  5. The integrated circuit storage device of any one of claims 1 through 4 wherein the communication circuitry (56) is responsive to an external microcontroller.
  6. The integrated circuit storage device of any one of claims 1 through 4 wherein the input information is an analog signal, the storage array is an analog voltage storage array and the input circuitry includes sample and hold circuits for periodically sampling an analog signal for storage of the samples in the analog voltage storage array.
  7. The integrated circuit storage device of claim 6, wherein the communication circuitry (56) is responsive to an external microcontroller.
  8. The integrated circuit storage device of any one of claims 1 through 4 wherein the message is digital information.
  9. The integrated circuit storage device of claim 1 wherein each storage cell for storing one sample of a plurality of successive samples of audio signals in analog voltage form, wherein the

       input circuitry for sequentially receiving an audio signal and providing sequential samples thereof to the storage cells for storage therein during a record operation, and wherein the output circuitry for sequentially providing, during a playback operation, samples of the audio signal stored in the storage cells as an output.
  10. The integrated circuit storage device of claim 2, wherein the reference identifier is a digital reference identifier.
  11. The integrated circuit storage device of claim 1, wherein each register being capable of storing the message identifier in digital form.
  12. A method of recording and playback of messages of varying length comprising the steps of:
    • (a) providing storage media (20) having a storage capacity by which a plurality of messages may be stored;
    • (b) providing a plurality of registers and associating each with a respective portion of the storage media on which a message segment may be stored; characterised by further comprising the steps of:
    • (c) for the recording of a message, successively locating registers having a reference identifier stored therein, changing the reference identifier stored therein to a specific message identification and storing segments of the message therein until the entire message is stored;
    • (d) for the playback of a specific message, successively locating registers having the specific message identifier stored therein and playing back the respective message segments in order until the entire message is played back.
  13. The method of recording and playback of messages of varying length of claim 12 further comprising the elimination of a recorded message comprising the step of:

       successively locating registers having the message identifier stored therein for the message to be eliminated and for those registers, changing the message identifier to the reference identifier.
  14. The method of any one of claims 12 or 13 wherein in steps (a) and (b), the storage media and the plurality of registers comprise a plurality of integrated circuits, each having a respective portion of the storage capacity and a respective portion of the registers thereon.
  15. The method of claim 14 wherein each integrated circuit provides a signal coupleable to the next successive integrated circuit to seamlessly initiate a record, playback or message elimination process in the next successive integrated circuit upon completion of the same in the previous integrated circuit.
  16. The method of claim 14 wherein the messages are voice messages.
  17. The method of claim 14 wherein the messages are digital information.
Anspruch[fr]
  1. Un dispositif de mémoire à circuit intégré pour mémoriser des messages et les lire sélectivement comprenant:
    • un ensemble (20) de mémoire à plusieurs cellules de mémoire;
    • un circuit d'entrée (22, 24, 28, 30, 32) pour amener en séquence une information d'entrée aux cellules de mémoire afin de l'y mémoriser pendant une opération d'enregistrement;
    • un circuit de sortie (40 à 46) pour envoyer en séquence comme sortie, pendant un opération de lecture, une information mémorisée dans les cellules de mémoire; caractérisé par
    • une série de registres, chaque registre étant associé à une série respective de cellules de mémoire de l'ensemble de mémoire et susceptible de mémoriser un identifiant de message:
       caractérisé par
    • un circuit de communication (56) pour recevoir des signaux de commande de l'extérieur du circuit;
    • un circuit (26) de commande et de pointeur de pile qui répond au circuit de communication pour localiser en séquence chaque registre successif qui mémorise l'identifiant spécifique de message spécifié par le circuit de communication et pour amener le circuit de sortie à envoyer de façon transparente comme sortie, pendant une opération de lecture, une information mémorisée dans la série respective de cellules de mémoire associée à chaque registre successif qui mémorise l'identifiant spécifique de message.
  2. Le dispositif de mémoire à circuit intégré selon la revendication 1, dans lequel le circuit (26) de commande et de pointeur de pile répond en outre au circuit de communication (56) pendant une opération d'effacement pour localiser des registres qui incluent un identifiant spécifique de message et remplacer, pour ces registres, cet identifiant spécifique de message par un identifiant de référence.
  3. Le dispositif de mémoire à circuit intégré selon la revendication 2, dans lequel le circuit (26) de commande et de pointeur de pile répond en outre au circuit de communication (56) pendant une opération d'enregistrement pour localiser avec succès des registres qui incluent l'identifiant de référence, envoyer en séquence une information d'entrée à la série de cellules de mémoire associée à ces registres et remplacer l'identifiant de référence des registres respectifs par un identifiant spécifique de message.
  4. Le dispositif de mémoire à circuit intégré selon la revendication 3, qui comprend en outre un circuit en cascade et un circuit de débordement, le circuit en cascade répondant à un signal externe pour lancer une opération de lecture ou d'écriture à l'intérieur du circuit intégré en fonction des instructions reçues par l'intermédiaire du circuit de communication, et le circuit de débordement envoyant un signal qui peut être couplé au circuit en cascade d'un circuit intégré identique pour y lancer de manière transparente une opération de lecture ou d'écriture lorsque le circuit de commande et pointeur de pile a exploré tous les registres pour localiser en séquence chaque registre successif qui mémorise l'identifiant spécifique de message spécifié par le circuit de communication pour l'opération de lecture ou d'écriture,
  5. Le dispositif de mémoire à circuit intégré selon l'une quelconque des revendications 1 à 4, dans lequel le circuit de communication (56) répond à un microcontrôleur externe.
  6. Le dispositif de mémoire à circuit intégré selon l'une quelconque des revendications 1 à 4 dans lequel l'information d'entrée est un signal analogique, l'ensemble de mémoire est un ensemble de mémoire à tension analogique, et le circuit d'entrée inclut des circuits d'échantillonnage et de maintien pour échantillonner périodiquement un signal analogique afin de mémoriser les échantillons dans l'ensemble de mémoire à tension analogique..
  7. Le dispositif de mémoire à circuit intégré selon la revendication6, dans lequel le circuit de communication (56) répond à un microcontrôleur externe.
  8. Le dispositif de mémoire à circuit intégré selon l'une quelconque des revendications 1 à 4 dans lequel le message est une information numérique.
  9. Le dispositif de mémoire à circuit intégré selon la revendication 1 dans lequel chaque cellule de mémoire est destinée à mémoriser un échantillon d'une série d'échantillons successifs de signaux sous forme de tension analogique, dans lequel

       le circuit d'entrée est destiné à recevoir en séquence un signal audio et envoyer des échantillons séquentiels de celui-ci aux cellules de mémoire pour les y mémoriser pendant une opération d'enregistrement et dans lequel le circuit de sortie est destiné à envoyer en séquence comme sortie, pendant une opération de lecture, des échantillons du signal audio mémorisés dans les cellules de mémoire.
  10. Le dispositif de mémoire à circuit intégré selon la revendication 2, dans lequel l'identifiant de référence est un identifiant numérique de référence
  11. Le dispositif de mémoire à circuit intégré selon la revendication 1, dans lequel chaque registre est susceptible de mémoriser l'identifiant de message sous forme numérique.
  12. Un procédé d'enregistrement et de lecture de messages de longueur variable comprenant les étapes consistant à:
    • (a) agencer un moyen de mémoire (20) dont la capacité de mémoire permet que plusieurs messages y soient mémorisés;
    • (b) agencer une série de registres et associer chacun d'eux à une partie respective du support de mémoire sur laquelle un segment de message peut être mémorisé;
       caractérisé par les étapes additionnelles consistant à:
    • (c) pour enregistrer un message, localiser successivement des registres dans lesquels est mémorisé un identifiant de référence, remplacer l'identifiant qui y est mémorisé par une identification spécifique de message et y mémoriser des segments du message jusqu'à ce que le message entier soit mémorisé;
    • (d) pour lire un message, localiser successivement des registres dans lesquels est mémorisé l'identifiant spécifique de message et lire dans l'ordre les segments de message respectifs jusqu'à ce que le message soit lu en entier.
  13. Le procédé d'enregistrement et de lecture de messages de longueur variable selon la revendication 12 comprenant en outre l'élimination d'un message enregistré comprenant l'étape consistant à:

       localiser successivement des registres dans lesquels est mémorisé l'identifiant de message afin que le message soit éliminé et remplacer, pour ces registres, l'identifiant de message par l'identifiant de référence.
  14. Le procédé selon la revendication 12 ou 14 dans lequel le support de mémoire et la série de registres comprennent, aux étapes (a) et (b), une série de circuits intégrés qui contiennent chacun une partie respective de la capacité de mémoire et une partie respective des registres.
  15. Le procédé selon la revendication 14 dans lequel chaque circuit intégré envoie un signal qui peut être couplé au circuit intégré qui le suit immédiatement de manière à lancer de façon transparente, dans le circuit intégré qui le suit immédiatement, un processus d'enregistrement de lecture ou d'élimination de message lorsque ce même processus été achevé dans le circuit intégré précédent.
  16. Le procédé selon la revendication 14 dans lequel les messages sont des messages vocaux.
  17. Le procédé selon la revendication 14 dans lequel les messages sont une information numérique.






IPC
A Täglicher Lebensbedarf
B Arbeitsverfahren; Transportieren
C Chemie; Hüttenwesen
D Textilien; Papier
E Bauwesen; Erdbohren; Bergbau
F Maschinenbau; Beleuchtung; Heizung; Waffen; Sprengen
G Physik
H Elektrotechnik

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