PatentDe  


Dokumentenidentifikation EP0905712 28.05.2003
EP-Veröffentlichungsnummer 0905712
Titel Verfahren und Vorrichtung zum analogen Programmieren einer Flash-EEPROM-Speicherzelle mit Selbstprüfung
Anmelder STMicroelectronics S.r.l., Agrate Brianza, Mailand/Milano, IT
Erfinder Pasotti, Marco, 27028 S. Martino Siccomario, IT;
Canegallo, Roberto, 15057 Tortona, IT;
Chioffi, Ernestina, 27100 Pavia, IT;
Gerna, Danilo, 23020 Montagna In Valtellina, IT;
Rolandi, Pier Luigi, 15059 Monleale, IT
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 69721252
Vertragsstaaten DE, FR, GB, IT
Sprache des Dokument EN
EP-Anmeldetag 29.09.1997
EP-Aktenzeichen 978304772
EP-Offenlegungsdatum 31.03.1999
EP date of grant 23.04.2003
Veröffentlichungstag im Patentblatt 28.05.2003
IPC-Hauptklasse G11C 27/00

Beschreibung[en]

The present invention relates to a method and a device for analog programming of flash EEPROM memory cells with autoverify.

As is known, and shown by way of example in Fig. 1, a flash memory array 1 comprises a plurality of flash cells 2 disposed on lines and columns, in which the gate terminals of the cells 2 disposed on one and the same line are connected to a respective word line 3, the drain terminals of the cells 2 disposed on one and the same column are connected to a respective bit line 4 and the source terminals are generally connected to ground. The word lines 3 are connected to a row decoder 5 and the bit lines 4 are connected to a column decoder 6 which receive respective address and control signals from a control unit 7 which permits the selection, from time to time, of a single word line 3 and a single bit line 4 and the biasing of the cell 2 connected to the word line and to the bit line selected at the operating voltages provided.

In particular, a cell 2 may be read by connecting the selected word line 3 to an external voltage VG of preset value (such as 8-9 V) and forcing a biasing current If into the selected bit line 4. Keeping the selected cell in linear region, the following equation applies: If = K*(W/L)*[(VG - Vth) - VDS/2]*VDS in which K is a constant associated with the production process, W/L is the dimensional width/length ratio of the cell, Vth is the threshold voltage of the cell (or the minimum voltage to be applied between the gate and source terminals of the cell so that it begins to conduct current) and VDS is the drain/source drop of the cell. In (1) the term K*(W/L)*VDS=GMf represents the transconductance (gain) of the cell and the term (VG - Vth) represents the overdrive of the cell.

By suitably biasing the cell, the drop VDS is constant and the term VDS/2 is negligible with respect to the overdrive (VG-Vth); consequently, in this state the current If flowing through the cell depends linearly on the threshold voltage Vth.

During writing (programming) of the cell, the latter is selected by biasing the selected word and bit lines at respective preset programming voltage values. Writing takes place thanks to the phenomenon of hot electron injection, whereby the high voltage supplied to the drain terminal of the cell to be written causes an increase in the velocity of the electrons and some of them achieve sufficient energy to overcome the barrier of the oxide. By forcing on the gate terminal a voltage which is higher than the drain terminal, the electric field which is created accelerates the electrons through the layer of oxide which separates the channel region from the floating gate region and permits the trapping of those electrons inside the floating gate region. The cell modifies its threshold voltage because of this trapping of the electrons.

By its nature, the phenomenon of hot electron injection is not controlled and not repeatable with accuracy; consequently, at the present time, during programming, the cell is read several times for reading the threshold voltage reached (verify phase).

This procedure is far from optimal, however, in view of the long periods of time required because of the need to interrupt programming, measure the threshold level reached and supply a new programming pulse. To overcome these problems for EEPROM memory cells, a system of programming and simultaneous verification of the programming has already been proposed (see US-A-5,422,842; US-A-5,495,442 and US-A-5,532,964 for example) which consists of measuring the current flowing through the cell during programming and comparing it with a reference current; as soon as the measured current becomes equal to or lower than the reference one, programming is interrupted.

A different solution to these problems is proposed in US-A-5 606 522, which discloses an analog memory including a cell array, a comparator, a mode selector, and a controller. The cell array includes a plurality of memory cells each having a control gate, an injector, and a floating gate, and a first input part of a differential input stage. A first high-voltage pulse signal is applied to the control gate and a second high-voltage pulse signal is applied to the injector. Charges are injected into or are erased from the floating gate through the injector. The comparator has a differential input port whose first input is a reference voltage signal and whose second input is a floating gate voltage signal of one of the plurality of memory cells. The comparator compares and outputs the difference between the reference voltage signal and the floating gate voltage signal. The mode selector connects the output of the comparator to the first input, functions as a unit amplifier during a reading mode, and connects the external reference voltage signal to the first input of the comparator during a writing mode. The controller maintains a program enable state if the current state of the comparator output signal is the same as its previous state and maintains a program disable state if the current state is different from the previous state. The controller generates first and second high-voltage pulse signals according to the state of the comparator output signal.

The object of the invention is therefore to provide a method and a device which permit the verification of the threshold reached by flash-EEPROM cells during programming.

The present invention provides a method and a device for analog programming of flash EEPROM memory cells with autoverify, as defined in Claims 1 and 4 respectively.

For an understanding of the invention, preferred embodiments will now be described, purely by way of non-exhaustive example, with reference to the accompanying drawings in which:

  • Fig. 1 shows a simplified circuit diagram of a flash memory of known type;
  • Fig. 2 shows a simplified circuit diagram of the present programming and verify device;
  • Fig. 3 shows a more detailed circuit diagram of the present device; and
  • Fig. 4 shows the plot of significant electrical variables of the present device.

Fig. 2 shows the programming and verify device 10 as connected to a cell to be read 2 belonging to the memory array 1 shown in Fig. 1. For reasons of simplicity, of the array 1 Fig. 2 shows only the cell to be read 2 addressed via the row decoder 5 and the column decoder 6; the row decoder 5 has been omitted and only the essential elements of the column decoder 6 have been shown.

In particular, as shown in Fig. 2, the cell to be read 2 has source terminal 11 connected to ground, gate terminal 12 biased at the programming voltage VG and drain terminal 13 connected to a node 18 via a selector switch 16 and a first biasing transistor 17 of NMOS type, both belonging to the column decoder 6 of Fig. 1. The node 18 is connected to a current mirror device 19 formed by two PMOS transistors 21, 22; in detail, the PMOS transistor 21 is diode-connected (i.e. it has short-circuited drain and gate terminals) and has drain terminal connected to the node 18, source terminal connected to the supply line 23 set at Vdd and gate terminal connected to the gate terminal of the PMOS transistor 22; this latter has source terminal connected to the supply line 23 and drain terminal connected to a node 24.

Via a second biasing transistor 25 also of NMOS type and a dummy switch 26 kept closed at all times, the node 24 is connected to the drain terminal 28 of a reference transistor 27, of NMOS type, having source terminal 29 connected to ground and gate terminal 30 connected to the output of an operational amplifier 31; this latter has inverting input connected to the node 18 and non-inverting input connected to the node 24. The second biasing transistor 25 has gate terminal connected to the gate terminal of the first biasing transistor 17 and to a biasing node 15 to which a biasing voltage VB is supplied. The biasing transistors 17 and 25 have the function of biasing the cell 2 and the reference transistor 27 at the desired voltage on the basis of the operating condition provided.

Fig. 2 also shows the output voltage Vo of the operational amplifier 31, also forming the output voltage of the programming and verify device 10; the voltage drop VDS,2 and VDS,27 between the drain and source terminals of the cell to be read 2 and, respectively, the reference transistor 27; as well as the currents I2 and I27 flowing through the cells.

European patent application No. 97830172.9, published as EP-A-0 872 850, entitled "High-precision analog reading circuit for memory arrays, in particular analog flash memory arrays" filed on 15.4.97 in the name of the same applicant, incorporated here for reference, describes a read device structurally similar to that of Fig. 2, in which a flash cell similar to the cell 2 is provided in place of reference transistor 27. For this device to which European application No. 97830172.9 relates, it has been shown, as briefly reported below, that the output voltage Vo of the operational amplifier 31 is linearly dependent on the threshold voltage Vth,2 of the cell 2. In fact, on the basis of (1), the current I2 flowing through the cell to be read 2 and the current IR flowing through the reference cell are expressed by: I2 = K* (W/L)*[(VG - Vth,2) - VDS,2/2]*VDS,2 IR = K* (W/L)*[(Vo - Vth,R) - VDS,R/2]*VDS,R in which Vth,2 and Vth,R are the threshold voltages of the cell to be read 2 and of the reference cell respectively, VDS,R is the source/drain drop of the reference cell and the other variables have the meaning already explained.

In the read condition, by assuming that the PMOS transistors 21 and 22 belonging to the current mirror device 19 and the biasing transistors 17 and 25 work at saturation, we have: I2 = IR

Furthermore, in the equilibrium condition, the voltages at the inputs of the operational amplifier 31 (voltages at the nodes 18 and 24) are equal and, given that the biasing transistors 17, 25 receive, at the gate terminal, a same biasing voltage VB (of 1.2-1.4 V for example), they have the same gate-to-source drop; it follows that if we admit equal voltage drops at the terminals of the selector switch 16 and the dummy switch 26, we have: VDS,2 = VDS,R

From (2) and (3), and taking account of (4) and (5), we obtain: VG - Vth,2 = Vo - Vth,R

From (7) we also immediately obtain: Vo = VG - (Vth,2 - Vth,R)

From (7) we see that the output voltage Vo of the amplifier 31 is linearly dependent on the threshold voltage Vth,2 of the cell to be read 2, so that the reading of this output voltage Vo supplies the threshold value Vth,2, knowing the threshold voltage of the reference cell R and the read voltage VG applied to the gate terminal 12 of the cell to be read 2.

In the case of the device of Fig. 2, during reading, (7) is still valid, given that (1) also applies to the reference transistor 27 and assuming equal values for the parameters K, W and L.

At the start of programming, a high voltage VB is supplied to the gate terminal of the biasing transistors 17, 25 so as to bring the drain terminal 13 of the cell to be programmed 2 to the programming drain voltage (7-8 V for example); a high voltage VG (12 V for example) is also applied to the gate terminal 12 of the cell 2. In this condition, hot electrons are injected into the floating gate region of the cell 2 which thus gradually modifies its threshold voltage. In this phase, the currents I2 and I27 are no longer equal but are nonetheless correlated and the output voltage Vo is still linearly dependent on the instantaneous threshold voltage of the cell 2. As the programming of the cell 2 continues and its threshold voltage increases, the current I2 flowing in the cell 2 decreases, the voltage at the node 18 increases, the output voltage Vo and hence the voltage at the gate terminal of the reference transistor 27 decreases and its current I27 decreases; in particular, the reduction of the current I27 is substantially equal to the decrease of the current I2 flowing in the cell 2, as can also be seen from Fig. 4 showing the plot of the currents I2 and I27 for the cell 2 and the transistor 27 versus the gate voltage VG for two different threshold voltage values corresponding to two different moments of programming. In particular, the curves A and B refer to current I2 of cells 2 having threshold voltages Vth' and Vth'', where Vth' < Vth'' and the curves C and D refer to the plots of current I27 in the conditions of the curves A and B. In practice, during programming, the current characteristics of the cell 2 and of the reference transistor 27 move contemporaneously downwards because of the increase of the threshold voltage of the cell 2 and of the corresponding reduction of the gate voltage of the reference transistor 27.

In this way, by reading the output voltage Vo of the device 10, it is possible to monitor the programming phase instant by instant and interrupt it when the cell 2 has reached the desired threshold value.

Fig. 3 shows a more complete embodiment of the device 10, equipped with means for automatically interrupting the programming when the desired threshold voltage is reached, and with means of compensation of the loop formed by the components 31, 27, 26, 25 and 22.

In addition to the elements of Fig. 2, Fig. 3 shows a comparator 36, having a first input connected to the output of the operational amplifier 31 and a second input receiving a reference voltage VTAR representing the target voltage, correlated to the threshold voltage desired for the cell 2; the output of the comparator 36 is connected to a selection input 37a of a switch 37 selectively connecting one of two nodes 37b, 37c to the biasing node 15. The node 37b is connected to a first voltage source 38 supplying the programming biasing voltage VH and the node 37c is connected to a second voltage source 39 supplying the read biasing voltage VL of lower value.

Fig. 3 further shows a compensation capacitor 40, a compensation transistor 41 and a current source 42. In detail, the compensation capacitor 40 is connected between the node 24 and a node 43; the current source 42 is arranged between the supply line 23 and the node 43 and the compensation transistor 41, of PMOS type, has its source terminal connected to the node 43, its gate terminal connected to the output of the operational amplifier 31 and its drain terminal connected to ground. These elements thus compensate for the loop 31, 27, 26, 25 which constitutes a two-stage amplifier, the first stage of which is formed by the operational amplifier 31 and the second stage uses the reference transistor 27 as amplifier element and in which the biasing transistor 25 operates as a cascode element which supplies a high impedance to the output of the loop (node 24).

Finally, Fig. 3 shows a capacitor 45, shown by broken lines and representing the parasitic capacitance of the bit line to which the cell to be read 2 is connected; the transistors (of NMOS type) which form the switches 16 and 26 and a reset transistor 44, of NMOS type, having the drain terminal connected to the intermediate node between the transistors 16 and 17, the source terminal connected to ground and the gate terminal receiving a control signal R.

In the device of Fig. 3, at the start of the programming phase, when the gate programming voltage VG is supplied to the gate terminal 12 of the cell 2, the cell has low threshold voltage, the output Vo of the operational amplifier 31 is greater than the target voltage VTAR (which, on the basis of (7), is equal to the programming gate voltage value VG minus the desired threshold value and minus the threshold voltage value of the reference transistor 27) and the comparator 36 keeps the switch 37 in the position connecting the node 37b to the node 15. The node 15 is thus supplied by the high voltage VH and the cell 2 begins to be programmed.

When, on increase of the threshold of the cell 2, the voltage Vo reaches the target value VTAR, the comparator switches, bringing the switch into the position connecting the node 37c to the node 15. The node 15 is thus supplied at low voltage VL and programming of the cell 2 is interrupted.

The above-mentioned system operates with high accuracy for medium-low values of the drain-to-source voltage VDS in which the characteristic of the flash cell and of the MOS transistor change in the same way with respect to the drain-to-source voltage. For high values of this voltage, the existing structural differences (so-called "short channel" effect of the flash cell, on the basis of which the drain current of the cell increases much more quickly than that of the MOS transistor, which flattens out, as can also be seen from the graphs of Fig. 4) are such as to reduce the accuracy provided by this device. To solve this problem it is possible to use the simultaneous autoverify procedure solely in the first part of the programming phase in which high accuracy is not necessary. Subsequently, as the desired threshold value is approached, it is advisable to use the traditional programming system, sending programming pulses and then verifying, by means of a flash reference cell equal to the memory cell to be programmed, that the desired threshold has been reached, as described in the above-mentioned European patent application. In this case, with respect to the diagram of Fig. 3, a further comparator may be provided which is similar to the comparator 36 and receives a reference voltage correlated to a value which is lower than VTAR; this comparator may control a further switch which may switch off the reference transistor 27 (by acting on the dummy transistor 26, for example, which would operate like a selection transistor for this purpose) and switch on a reference cell equal to the cell 2 downstream of the biasing transistor 25.

The advantages of the described method and device are as follows. Firstly, they permit an extremely speedy method of programming, including in the case of use solely in the first part of the programming, due to at least partial elimination of the dead times for interrupting programming, reading the threshold reached voltage and deciding as to whether to continue programming or not. Furthermore, the device is simple, occupies a reduced space in the memory and is reliable.

Finally it will be clear that numerous modifications and variants may be introduced to the method and the device described and illustrated herein, all of which come within the scope of the inventive concept as defined in the accompanying claims.


Anspruch[de]
  1. Verfahren zum analogen Programmieren einer Flash-EEPROM-Speicherzelle, welches die Schritte aufweist:
    • Verbinden einer Stromquelle (19) mit zwei Ausgängen mit einem ersten Anschluss (13) der Zelle (2) und mit einem ersten Anschluss (28) eines MOS-Transistors (27);
    • Liefern einer ersten Spannung an einen Steueranschluss (12) der Zelle, Verbinden des ersten Anschlusses dieser Zelle und des ersten Anschlusses des MOS-Transistors mit einer zweiten Spannung und Verbinden eines zweiten Anschlusses (11) der Zelle (2) und eines zweiten Anschlusses (29) des MOS-Transistors mit einem Referenzpotenzial, wobei die erste und zweite Spannung eine derartige Amplitude haben, um so die Zelle zu programmieren;
    • Verbinden der ersten Anschlüsse der Zelle und des MOS-Transistors mit einem ersten und einem zweiten Eingang eines negativen Rückkopplungselementes (31) und Verbinden eines Ausgangs des negativen Rückkopplungselementes mit einem Steueranschluss (30) des MOS-Transistors;
    gekennzeichnet dadurch, dass es ferner die Schritte aufweist:
    • Anzeigen der Ausgangsspannung des negativen Rückkopplungselementes (31), während der erste Anschluss (13) der Zelle (2) mit der zweiten Spannung verbunden ist, und Vergleichen der Ausgangsspannung mit einer Referenzspannung; und
    • Unterbrechen der Versorgung der zweiten Spannung mit dem ersten Anschluss der Zelle, wenn die Ausgangsspannung wenigstens gleich der Referenzspannung wird.
  2. Verfahren nach Anspruch 1 dadurch gekennzeichnet, dass die Ausgangsspannung proportional zu einem aktuellen Schwellwertspannungspegel der Zelle (2) ist und dass die Referenzspannung proportional zu einem gewünschten Schwellwertspannungspegel ist, welcher von der Zelle gewünscht wird.
  3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass das negative Rückkopplungselement ein Operationsverstärker (31) ist.
  4. Vorrichtung zum analogen Programmieren einer Flash-EEPROM-Speicherzelle, welche eine Speicherzelle (2), welche einen ersten (13) und einen zweiten (11) Anschluss besitzt, und einen Steueranschluss (12) aufweist, wobei diese Vorrichtung (10) ferner aufweist:
    • Einen MOS-Transistor (27), welcher einen ersten (28) und einen zweiten (29) Anschluss und einen Steueranschluss (30) besitzt, wobei der Steueranschluss (12) der Zelle (2) mit einer ersten Spannung verbunden ist, wobei der erste Anschluss (13) der Zelle (2) und der erste Anschluss (28) des MOS-Transistors (27) mit einer zweiten Spannung verbunden sind, und der zweite Anschluss (11) der Zelle (2) und der zweite Anschluss (29) des MOS-Transistors (27) mit einem Referenzpotenzial verbunden sind, wobei die erste und zweite Spannung eine derartige Amplitude besitzt, um die Zelle (2) zu programmieren;
    • eine Vorrichtung (21, 22) zum Erzeugen eines ersten und zweiten Stromes, welche jeweils einen ersten und einen zweiten Strom, welche zueinander korreliert sind, erzeugen, wobei die erste Stromerzeugungsvorrichtung (21) mit dem ersten Anschluss (13) der Zelle (2) verbunden ist und die zweite stromerzeugende Vorrichtung (22) mit dem ersten Anschluss (28) des MOS-Transistors (27) verbunden ist;
    • eine negative Rückkopplungsvorrichtung (31), welche einen ersten und einen zweiten Eingang besitzt, welcher jeweils mit dem ersten Anschluss (13) der Zelle (2) und dem ersten Anschluss (28) des MOS-Transistors (27) verbunden ist, und einen Ausgang, welcher mit dem Steueranschluss (30) des MOS-Transistors (27) verbunden ist;
    dadurch gekennzeichnet; dass sie ferner aufweist:
    • eine Vergleichsvorrichtung (36), welche die Ausgangsspannung der negativen Rückkopplungsvorrichtung (31) mit einer Referenzspannung vergleicht; und
    • eine Unterbrechungsvorrichtung (37), welche das Liefern der zweiten Spannung an den ersten Anschluss (13) der Zelle (2) unterbricht, wenn die Ausgangsspannung wenigstens gleich der Referenzspannung wird.
  5. Vorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass die negative Rückkopplungsvorrichtung einen Operationsverstärker (31) aufweist, welcher einen invertierenden Eingang besitzt, welcher mit dem ersten Anschluss (13) der Zelle (2) verbunden ist, und einen nicht invertierenden Eingang besitzt, welcher mit dem ersten Anschluss (28) des MOS-Transistors (27) verbunden ist.
  6. Vorrichtung nach Anspruch 4 oder 5, dadurch gekennzeichnet, dass die erste und zweite Stromerzeugungsvorrichtung (21, 22) einen Stromspiegelschaltkreis (19) bildet.
  7. Vorrichtung nach einem der Ansprüche 4-6, dadurch gekennzeichnet, dass sie einen ersten (17) und einen zweiten (25) Vorspannungstransistor aufweist, welcher zwischen der ersten Stromerzeugungsvorrichtung (21) und dem ersten Anschluss (13) der Zelle (2) liegt und jeweils zwischen der zweiten Stromerzeugungsvorrichtung (22) und dem ersten Anschluss (28) des MOS-Transistors (27) liegt, wobei der erste und der zweite Vorspannungstransistor jeweils Steueranschlüsse besitzen, welche miteinander (15) verbunden sind und welche ein gewöhnliches Vorspannungssignal empfangen.
  8. Vorrichtung nach Anspruch 7, dadurch gekennzeichnet, dass die Vergleichsvorrichtung ein Vergleichselement (36) aufweist und dass die Unterbrechungsvorrichtung einen Zwei-Positionen-Schalter (37) aufweist, wobei das Vergleichselement (36) einen ersten und einen zweiten Eingang und einen Ausgang besitzt; wobei der erste Eingang des Vergleichselements mit dem Ausgang der negativen Rückkopplungsvorrichtung (31) verbunden ist; wobei der zweite Eingang des Vergleichselements die Referenzspannung empfängt und der Ausgang des Vergleichselements mit einem Steueranschluss (37a) des Zwei-Positionen-Schalters (37) verbunden ist, wobei der Schalter mit einer ersten und einer zweiten Vorspannung und mit den Steueranschlüssen des ersten und zweiten Vorspannungstransistors (17, 25) verbunden ist; wobei der Schalter in einer ersten Kommutierungsposition den ersten Eingang mit den Steueranschlüssen der vorspannenden Transistoren verbindet und in einer zweiten Kommutierungsposition den zweiten Eingang mit den Steueranschlüssen der vorspannenden Transistoren verbindet.
  9. Vorrichtung nach einem der Ansprüche 4-8, dadurch gekennzeichnet, dass der erste Anschluss (13, 28) der Zelle (2) und des MOS-Transistors (27) ein Drain-Anschluss ist, der zweite Anschluss (11, 29) der Zelle und des MOS-Transistors ein Quellanschluss ist und der Steueranschluss (12, 30) der Zelle und des MOS-Transistors ein Gate-Anschluss ist.
  10. Vorrichtung nach einem der Ansprüche 4-9, dadurch gekennzeichnet, dass sie einen Kompensationsschaltkreis (40-42) aufweist, welcher zwischen dem ersten Anschluss (28) des MOS-Transistors (27) und dem Ausgang (30) der negativen Rückkopplungsvorrichtung (31) liegt.
  11. Vorrichtung nach Anspruch 10, dadurch gekennzeichnet, dass der Kompensationsschaltkreis (40-42) einen Kompensationskondensator (40) und einen Kompensationstransistor (41) aufweist, wobei der Kompensationskondensator (40) einen ersten Anschluss aufweist, welcher mit dem ersten Anschluss (28) des MOS-Transistors (27) verbunden ist, und einen zweiten Anschluss aufweist, welcher mit einem ersten Anschluss (43) des Kompensationstransistors (41) verbunden ist, wobei der Kompensationstransistor einen Steueranschluss besitzt, welcher mit dem Ausgang (30) der negativen Rückkopplungsvorrichtung (31) verbunden ist.
Anspruch[en]
  1. A method for analog programming of a flash EEPROM memory cell, comprising the steps of:
    • connecting a current source (19) with two outputs to a first terminal (13) of said cell (2) and to a first terminal (28) of a MOS transistor (27);
    • supplying a first voltage to a control terminal (12) of said cell, connecting said first terminal of said cell and said first terminal of said MOS transistor to a second voltage and connecting a second terminal (11) of said cell (2) and a second terminal (29) of said MOS transistor to a reference potential, said first and second voltage being of amplitude such as to program said cell;
    • connecting said first terminals of said cell and of said MOS transistor to a first and a second input of a negative feedback element (31) and connecting an output of said negative feedback element to a control terminal (30) of said MOS transistor;
    characterized in that it further comprises the steps of:
    • monitoring the output voltage of said negative feedback element (31) while said first terminal (13) of said cell (2) is connected to said second voltage and comparing said output voltage with a reference voltage; and
    • interrupting the supply of said second voltage to said first terminal of said cell when said output voltage becomes at least equal to said reference voltage.
  2. A method according to Claim 1, characterized in that said output voltage is proportional to a current threshold voltage level of said cell (2) and in that said reference voltage is proportional to a desired threshold voltage level desired of said cell.
  3. A method according to Claim 1 or 2, characterized in that said negative feedback element is an operational amplifier (31).
  4. A device for analog programming of a flash EEPROM memory cell, comprising a memory cell (2) having a first (13) and a second (11) terminal and a control terminal (12), said device (10) further comprising:
    • a MOS transistor (27) having a first (28) and a second (29) terminal and a control terminal (30), said control terminal (12) of said cell (2) being connected to a first voltage, said first terminal (13) of said cell (2) and said first terminal (28) of said MOS transistor (27) being connected to a second voltage, and said second terminal (11) of said cell (2) and said second terminal (29) of said MOS transistor (27) being connected to a reference potential, said first and second voltage being of amplitude such as to program said cell (2);
    • first and second current generating means (21, 22) generating a first and, respectively, a second current correlated to each other, said first current generating means (21) being connected to said first terminal (13) of said cell (2), and said second current generating means (22) being connected to said first terminal (28) of said MOS transistor (27);
    • negative feedback means (31) having a first and a second input connected to said first terminal (13) of said cell (2) and, respectively, to said first terminal (28) of said MOS transistor (27), and an output connected to said control terminal (30) of said MOS transistor (27);
    characterized in that it further comprises:
    • comparator means (36) comparing the output voltage of said negative feedback means (31) with a reference voltage; and
    • interruption means (37) interrupting the supply of said second voltage to said first terminal (13) of said cell (2) when said output voltage becomes at least equal to said reference voltage.
  5. A device according to Claim 4, characterized in that said negative feedback means comprise an operational amplifier (31) having an inverting input connected to said first terminal (13) of said cell (2) and a non-inverting input connected to said first terminal (28) of said MOS transistor (27).
  6. A device according to Claim 4 or 5, characterized in that said first and second current generating means (21, 22) form a current mirror circuit (19).
  7. A device according to one of Claims 4-6, characterized in that it comprises a first (17) and a second (25) biasing transistor interposed between said first current generating means (21) and said first terminal (13) of said cell (2) and, respectively, between said second current generating means (22) and said first terminal (28) of said MOS transistor (27), said first and second biasing transistor having respective control terminals connected to each other (15) and receiving a common biasing signal.
  8. A device according to Claim 7, characterized in that said comparator means comprise a comparator element (36) and said interruption means comprise a two-position switch (37), said comparator element (36) having a first and a second input and an output; said first input of said comparator element being connected to said output of said negative feedback means (31); said second input of said comparator element receiving said reference voltage and said output of said comparator element being connected to a control terminal (37a) of said two-position switch (37), said switch being connected to a first and a second biasing voltage and to said control terminals of said first and second biasing transistor (17, 25); said switch, in a first commutation position, connecting said first input to said control terminals of said biasing transistors and, in a second commutation position, connecting said second input to said control terminals of said biasing transistors.
  9. A device according to one of Claims 4-8, characterized in that said first terminal (13, 28) of said cell (2) and of said MOS transistor (27) is a drain terminal, said second terminal (11, 29) of said cell and of said MOS transistor is a source terminal and said control terminal (12, 30) of said cell and of said MOS transistor is a gate terminal.
  10. A device according to one of Claims 4-9, characterized in that it comprises a compensation circuit (40-42) interposed between said first terminal (28) of said MOS transistor (27) and said output (30) of said negative feedback means (31).
  11. A device according to Claim 10, characterized in that said compensation circuit (40-42) comprises a compensation capacitor (40) and a compensation transistor (41), said compensation capacitor (40) having a first terminal connected to said first terminal (28) of said MOS transistor (27) and a second terminal connected to a first terminal (43) of said compensation transistor (41), said compensation transistor having a control terminal connected to said output (30) of said negative feedback means (31).
Anspruch[fr]
  1. Procédé de programmation analogique d'une cellule de mémoire EEPROM flash, comprenant les étapes consistant :
    • à connecter une source de courant (19) ayant deux sorties à une première borne (13) de ladite cellule (2) et à une première borne (28) d'un transistor MOS (27) ;
    • à appliquer une première tension à une borne de commande (12) de ladite cellule, à connecter ladite première borne de ladite cellule et ladite première borne dudit transistor MOS à une seconde tension, et à connecter une seconde borne (11) de ladite cellule (2) et une seconde borne (29) dudit transistor MOS à un potentiel de référence, lesdites première et seconde tensions étant d'une amplitude qui permet de programmer ladite cellule ;
    • à connecter lesdites premières bornes de ladite cellule et dudit transistor MOS à une première et une seconde entrée d'un élément de contre-réaction (31) et à connecter une sortie dudit élément de contre-réaction à une borne de commande (30) dudit transistor MOS ;
    caractérisé en ce qu'il comprend, en outre, les étapes consistant :
    • à contrôler la tension de sortie dudit élément de contre-réaction (31) alors que ladite première borne (13) de ladite cellule (2) est connectée à ladite seconde tension, et à comparer ladite tension de sortie à une tension de référence ; et
    • à interrompre l'application de ladite seconde tension à ladite première borne de ladite cellule lorsque ladite tension de sortie devient au moins égale à ladite tension de référence.
  2. Procédé selon la revendication 1, caractérisé en ce que ladite tension de sortie est proportionnelle à un niveau de tension de seuil de courant de ladite cellule (2), et en ce que ladite tension de référence est proportionnelle à un niveau de tension de seuil souhaité de ladite cellule.
  3. Procédé selon la revendication 1 ou 2, caractérisé en ce que ledit élément de contre-réaction est un amplificateur opérationnel (31).
  4. Dispositif de programmation analogique d'une cellule de mémoire EEPROM flash, comprenant une cellule de mémoire (2) ayant une première (13) et une seconde (11) borne et une borne de commande (12), ledit dispositif (10) comprenant, en outre :
    • un transistor MOS (27) ayant une première (28) et une seconde (29) borne et une borne de commande (30), ladite borne de commande (12) de ladite cellule (2) étant connectée à une première tension, ladite première borne (13) de ladite cellule (2) et ladite première borne (28) dudit transistor MOS (27) étant connectées à une seconde tension, et ladite seconde borne (11) de ladite cellule (2) et ladite seconde borne (29) dudit transistor MOS (27) étant connectées à un potentiel de référence, lesdites première et seconde tensions étant d'une amplitude qui permet de programmer ladite cellule (2) ;
    • des premiers et seconds moyens générateurs de courant (21, 22) générant un premier et, respectivement, un second courant corrélés l'un à l'autre, lesdits premiers moyens générateurs de courant (21) étant connectés à ladite première borne (13) de ladite cellule (2), et lesdits seconds moyens générateurs de courant (22) étant connectés à ladite première borne (28) dudit transistor MOS (27) ;
    • des moyens de contre-réaction (31) ayant une première et une seconde entrée connectées à ladite première borne (13) de ladite cellule (2) et, respectivement, à ladite première borne (28) dudit transistor MOS (27), et une sortie connectée à ladite borne de commande (30) dudit transistor MOS (27) ;
    caractérisé en ce qu'il comprend, en outre :
    • des moyens comparateurs (36) comparant la tension de sortie desdits moyens de contre-réaction (31) à une tension de référence ; et
    • des moyens d'interruption (37) interrompant l'application de ladite seconde tension à ladite première borne (13) de ladite cellule (2) lorsque ladite tension de sortie devient au moins égale à ladite tension de référence.
  5. Dispositif selon la revendication 4, caractérisé en ce que lesdits moyens de contre-réaction comprennent un amplificateur opérationnel (31) ayant une entrée d'inversion connectée à ladite première borne (13) de ladite cellule (2) et une entrée de non-inversion connectée à ladite première borne (28) dudit transistor MOS (27).
  6. Dispositif selon la revendication 4 ou 5, caractérisé en ce que lesdits premiers et seconds moyens générateurs de courant (21, 22) forment un circuit miroir de courant (19).
  7. Dispositif selon l'une des revendications 4 à 6, caractérisé en ce qu'il comprend un premier (17) et un second (25) transistor de polarisation interposés entre lesdits premiers moyens générateurs de courant (21) et ladite première borne (13) de ladite cellule (2) et, respectivement, entre lesdits seconds moyens générateurs de courant (22) et ladite première borne (28) dudit transistor MOS (27), lesdits premier et second transistors de polarisation ayant des bornes de commande respectives connectées l'une à l'autre (15) et recevant un signal de polarisation commun.
  8. Dispositif selon la revendication 7, caractérisé en ce que lesdits moyens comparateurs comprennent un élément comparateur (36) et lesdits moyens d'interruption comprennent un commutateur à deux positions (37), ledit élément comparateur (36) ayant une première et une seconde entrée et une sortie ; ladite première entrée dudit élément comparateur étant connectée à ladite sortie desdits moyens de contre-réaction (31) ; ladite seconde entrée dudit élément comparateur recevant ladite tension de référence et ladite sortie dudit élément comparateur étant connectée à une borne de commande (37a) dudit commutateur à deux positions (37), ledit commutateur étant connecté à une première et une seconde tension de polarisation et auxdites bornes de commande desdits premier et second transistors de polarisation (17, 25) ; ledit commutateur, dans une première position de commutation, connectant ladite première entrée auxdites bornes de commande desdits transistors de polarisation et, dans une seconde position de commutation, connectant ladite seconde entrée auxdites bornes de commande desdits transistors de polarisation.
  9. Dispositif selon l'une des revendications 4 à 8, caractérisé en ce que la première borne (13, 28) de ladite cellule (2) et dudit transistor MOS (27) est une borne de drain, ladite seconde borne (11, 29) de ladite cellule et dudit transistor MOS est une borne de source et ladite borne de commande (12, 30) de ladite cellule et dudit transistor MOS est une borne de grille.
  10. Dispositif selon l'une des revendications 4 à 9, caractérisé en ce qu'il comprend un circuit de compensation (40-42) interposé entre ladite première borne (28) dudit transistor MOS (27) et ladite sortie (30) desdits moyens de contre-réaction (31).
  11. Dispositif selon la revendication 10, caractérisé en ce que ledit circuit de compensation (40-42) comprend un condensateur de compensation (40) et un transistor de compensation (41), ledit condensateur de compensation (40) ayant une première borne connectée à ladite première borne (28) dudit transistor MOS (27) et une seconde borne connectée à une première borne (43) dudit transistor de compensation (41), ledit transistor de compensation ayant une borne de commande connectée à ladite sortie (30) desdits moyens de contre-réaction (31).






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