PatentDe  


Dokumentenidentifikation EP0909028 07.08.2003
EP-Veröffentlichungsnummer 0909028
Titel FIR-Filter für programmierbare Dezimation
Anmelder Tektronix, Inc., Wilsonville, Oreg., US
Erfinder Keith, R. Slavin, Beaverton, Oregon 97008, US
Vertreter Hofstetter, Schurack & Skora, 81541 München
DE-Aktenzeichen 69815986
Vertragsstaaten DE, GB
Sprache des Dokument EN
EP-Anmeldetag 15.09.1998
EP-Aktenzeichen 983074881
EP-Offenlegungsdatum 14.04.1999
EP date of grant 02.07.2003
Veröffentlichungstag im Patentblatt 07.08.2003
IPC-Hauptklasse H03H 17/06

Beschreibung[en]
BACKGROUND OF THE INVENTION

The present invention relates to finite impulse response (FIR) filters, and more particularly to a FIR filter for programmable decimation by powers of two.

A decimate-by-two FIR filter has the following ideal characteristics: A(ω) ≈ 1   0 ≤ ω ≤ π/4 0 ≤ A(ω) ≤ 1   π/4 < ω < π/2 A(ω) ≈ 0   π/2 ≤ ω ≤ π

In practice a Parks-McClellan equi-ripple design algorithm, using the Remez exchange algorithm with Chebyshev design theory, has a smooth and monotonic response in the transition region of Equation (2). With this response every other output from the filter may be discarded without aliasing problems, and the transition band becomes the rejected band for any following decimation stage, allowing for cascading. Therefore decimation by 2m may be performed with m filter stages coupled in series. Such a direct approach to decimating by 2m where m is large results in a huge amount of hardware. Furthermore later decimation stages have lower structural usage, defined as operations per gate per clock event.

What is desired is a FIR filter for programmable decimation by powers of two that reduces the amount of hardware required while maximizing the operations per gate per clock event.

SUMMARY OF THE INVENTION

Accordingly the present invention provides a FIR filter for programmable decimation by powers of two that uses context registers with the output from the filter being fed back to the input. An input signal is sampled at one-half an input clock rate and progressively decimated, with each decimation result stored in a separate register within each context register. An output context register contains the result for each level of decimation by two, and the desired decimation output is selected for output according to a selected output signal. A cascade of timing circuits provide appropriate timing signals for the FIR filter, one timing circuit for each level of decimation corresponding to the number of separate registers in each context register. In this way any decimation is available for output, and multiple devices may access the FIR filter to get different decimation factors for the same input signal.

The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing.

DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

Fig. 1 is a table view illustrating timing for a FIR filter for programmable decimation by powers of two according to the present invention.

Fig. 2 is a block diagram view of a FIR filter for programmable decimation by powers of two according to the present invention.

Fig. 3 is a block diagram view of a representative timing circuit for the FIR filter of Fig. 2.

Fig. 4 a block diagram view of a representative context register for use in the FIR filter of Fig. 2.

DETAILED DESCRIPTION OF THE INVENTION

The following precepts are the basis for the FIR filter design for programmable decimation by powers of two:

  • 1. The data rate in and out of a filter may be less than the system clock by the use of input and output valid signals that control register state changes within the design. Such state changes may be implemented with synchronous input-enable registers, allowing fully synchronous designs.
  • 2. For a decimating filter the output data rate is half the input rate.
  • 3. For any finite integer m this geometric sum is known: Σi=1->m(1/2i) = 1 - (1/2m) < 1
  • 4. The present and new state of any register-oriented hardware system depends only upon the state of its registers and inputs, analogous to "contexts" in software.

If the FIR filter is designed to receive an initial input rate of fs/2 where fs is the clock rate, then the output rate is fs/4 which is the input rate for the next filter, etc. Now the above equation gives the sum of the input rates, fs/2+fs/4+fs/8..., for m such filters as less than fs so the entire bandwidth of all the inputs to all m filters fits within the clock rate fs for any number of decimation stages m.

Every register within a filter design is replaced with an m-register file to allow m filter contexts, and control of the input of the filter comes from either the external input stream at fs/2 or less or from the output of the filter in its previous context, in both cases with the data-valid from the appropriate source or context, such that only the first decimation context receives data from the filter system input. Such a filter decimates by any factor up to 2m merely by marking which output valid context to send out from the filter system. Indeed such a design decimates by any power of two up to 2m simultaneously by generating separate valid signals marking the required data for each system receiving the filter output stream.

This approach is more hardware economical than cascading decimating filters because only the registers are duplicated m times, not the logic between them which includes multipliers and adders. This results in a hardware saving of about a factor of two. The constraint on using arbitrarily large values of m is the amount of register storage required for m contexts. Another advantage is that changing the decimation factors is merely a matter of generating proper valid signals, so the filter coefficients may be fixed, such as by using shift-add structures, allowing for even more economical designs.

The trick is controlling the timing of such a system. To understand this conceptually a recursive argument is used by imagining filtering from the perspective of the pth decimation context, 0≤p<m. Two control signals are defined between each stage rather than a single valid signal such that:

  • CLK_EN[p] marks the "clock context" in which the pth stage operates, i.e., other clock edge events don't exist in its little universe
  • VALID[p] marks the input data as valid

The Table of Fig. 1 illustrates a control sequence where each column is sampled at intervals of 2p clock periods in time, i.e., at every clock for p=0. "!" denotes logical inversion, and "toggle[p]" is a register for context p whose state changes as:

  • if CLK_EN[p] then
  • toggle[p] <- !toggle[p].

From the Table of Fig. 1 the derived outputs are identical to the inputs if the columns when CLK_EN[p+1] equals zero are ignored, so that the new pattern is identical to the old but with the enabled clock events now separated by 2p+1 clocks instead of 2p for the inputs. If for the first stage, p=0, CLK_EN[0] is true on all clocks and VALID[0] is enabled at fs/2 rate, and if the timing control being true for p implies that it is also true for p+1 as long as p<m, then inductively the entire system works.

For this "context switch" scheme to work, all state changes for a given context p occur when VALID[p]=1. Otherwise if additional state changes occur, there are time conflicts for different context access to register state. Also the corresponding VALID[p+1] signal output appears at a time which is not coincident with VALID[p], which requires that there is an output register OUT[p] whose input stage changes only if VALID[p]=1 and which presents the output for that context if VALID[p+1]=1. This requirement is met with a register file that has separate register write arid read selection at any given clock period. All other context registers within the FIR filter share a common read and write address selection.

The FIR convolution Vt = Σi=0->(n-1)hixt-i is for an n-tap FIR filter with a sampled input sequence xt as a function of time and n filter coefficients {hi}, 0≤i<n. This sum may be separated into two sums, one over even values of i and the other for the remaining odd values: Vt = Σj=0->((n+1)/2-1)h2jxt-2j + Σk=0->(n/2-1)h2k+1xt-2k-1 where the first sum over j is for a change of variable i=2j and the second sum over k is for a change of variable i=2k+1. For decimation by two the outputs Vt for either t odd or t even are discarded. Changing the variables so that t=2T for integer T produces the output for even time t as: V2T = Σj=0->((n+1)/2-t)h2jx2(T-j) + Σk=0->(n/2-1)h2k+1x2(T-k)-1 where the first sum is a convolution of the even time series in {x}, (the same as the output V2T) with the even index coefficients of {h}, and the second sum is a convolution of the odd time series in {x} with the odd index coefficients of {h}. Therefore the first filter needs only to change its state at even time, and the second at odd time. Each FIR filter has about half of the coefficients of the original convolution (for odd n the length of the first filter is one more than the length of the second).

To implement these filters in pipelined form rather than the direct forms given above, using induction or z-transforms for an n-tap filter, the following relations define a structure with an equivalent transfer function to the basic FIR convolution equation above: Vt = R[t,n-2] + h0x[t] R[t,j] <- R[t-1,i-1] + hn-1-ix[t-1] R[t,i] = 0 for i<0 where "<-" denotes a register assignment and R[t,i] is the ith register contents at time t. Adding an additional pipeline register to the output produces: OUTt <- Vt-1 so that OUTt = R[t,n-1].

If n1 = floor((n+1)/2) n2 = floor(n/2) where "floor" is a function that returns the integer portion of the result, then from Equations 8, 9 and 10: OUT2T = R[2T,n1-1] + R[2T-1,n2-1] where for t=2T, T being an integer, R[2T,j] <- R[2(T-1),j-1] + hn-1-2jx[2(T-1)] R[2T-1,k] <- R[2(T-1)-1,k-1] + hn-2kx[2(T-1)-1]

These equations describe separate pipelined transversal filters, although there are now 2T delays between adjacent taps and the state of each recursion depends only upon odd and even t terms respectively. The delays may be implemented by a single register for each context p, each on alternating VALID[p] inputs, so that if at t=0 toggle[p]=0, then for the pth context the clock enables are: clk_enable_A[p] = VALID[p] & toggle[p] clk_enable_B[p] = VALID[p] & !toggle[p] where the terms on the right are described with reference to the Table of Fig. 1.

Now the terms in 2T and 2T-1 in the above equations change on alternate VALID[p]=1 events because of the toggle[p] term, and the right-hand term for OUT2T is one time period t behind the left term, i.e., it has a time index one less than 2T, so the right-hand term is delayed by another register delay enabled on clk_enable_A[p], as with the left-hand term R[2T,n1-1], to get: Z(2T] <- R[2T-1,n2-1] so that: OUT2T = R[2T,n1-1] + Z[2T]

Finally by substitution into the above equation into the left added term and moving the add before the final enable-coincident registers R[2T,n1-1] and Z[2T]: OUT2T <- (R[2(T-1),n1-2] + h0x[2(T-1)]) + R[2T-1,n2-1] where the parenthesis denotes addition precedence order as defined implicitly in the equations. For higher speed pipelining a short path from h0x[2(T-1)] to OUT2T is achieved by rearranging as follows: OUT2T <- [R[2(T-1),n1-2] + R[2T-1,n2-1]) + h0x[2(T-1)]

Referring now to Fig. 2 a diagram of a four-tap final FIR filter structure based upon the above equations is shown. An input signal INPUT[0] is applied to one input of a 2 to 1 multiplexer 12, the output of which is input to a plurality of multipliers 14. Each multiplier 14 multiplies the selected output from the multiplexer 12 by a respective filter coefficient h0, h1, ... h3. The outputs from the odd multipliers 141 and 143 are combined by a first adder 16 after the output from multiplier 143 has been delayed by a first context register 18. The output from the first adder 16 is delayed by a second context register 20. The first and second context registers 18, 20 are enabled by a CLK_ENABLE_B[p] signal. The output from the second context register 20 provides the R[2T-1,n2-1] term of Equation 23.

The output from multiplier 142 delayed by a third context register 22 provides the R[2(T-1),n1-2] term of Equation 23, which is added to the output from the second context register 20 by a second adder 24. Finally the h0x[2[T-1)] term of Equation 23 is provided by the output from multiplier 140, which in turn is added to the output from the second adder 24 by a third adder 26. The output from the third adder 26 is input to an output context register 28 that has separate input and output enable ports. A CLK_ENABLE_A[p] signal enables the third context register 22 and the input enable port of the output context register 28. The output from the output context register 28 is the output signal OUT2T of Equation 23. The selection of the particular decimation output from the output context register 28 is determined by a multiplexer 27 which selects one of the VALID[p+1] lines to read out the desired context from the context register corresponding to a desired decimation factor 2p. Programmability may also be achieved in other ways, as are readily apparent to those skilled in the art.

The other inputs to the FIR filter are those necessary for timing, namely, VALID[p] and CLK_EN[p]. Timing circuits 29 are cascaded, one timing circuit for each of the m contexts. The VALID[0] signal input to the first timing circuit 290 provides the select signal to the multiplexer 12 to select the input INPUT[0]. Otherwise the output signal OUT2T is fed back through the multiplexer 12 for another divide by two iteration. For a given timing circuit 29p, as shown in Fig. 3, a toggle[p] register 30 is enabled by the VALID[p] signal, and is configured so that for every VALID[p] pulse it switches state. The input to the toggle[p] register 30 and the VALID[p] signal are combined by a first AND gate 32 to produce the CLK_ENABLE_B[p] signal occurring at one-half of the VALID[p] signal rate. The output from the toggle[p] register 30 which is of opposite phase to the input is combined with the VALID[p] signal by a second AND gate 34 to produce the CLK_ENABLE_A[p] signal. The VALID[p] signal is inverted by an inverter circuit 36 and then combined with the CLK_EN[p] signal by a third AND gate 38 to produce a CLK_EN[p+1] signal as an output to the next timing circuit 29p+1. The CLK_EN[p+1] signal is combined with the output from the toggle[p] register 30 by a fourth AND gate 40 to produce a VALID[p+1] signal as an output. The VALID[p+1] signal is out of phase with the CLK_ENABLE_A[p] signal, and is applied to the output enable port of the output context register 28 so that the register stores data and transfers out data on a non-interferring basis. The VALID[p+1] signal also is input to the next timing circuit 29p+1.

Each context register 18, 20, 22, 28 has m internal registers 42, one for each context. Each of the ENABLE[p] bus signals form an address that enables just one of the registers 42 at a time for storing data. The outputs of the registers 42 are input to respective AND gates 44 which, for context registers 18, 20, 22, are enabled also by the ENABLE[p] bus signal. The outputs from the AND gates 44 are input to an OR gate 46 that provides the selected register 42 output for that context register 18, 20, 22. For the output context register 28 the AND gates 44 are enabled by the VALID[p+1] bus, as shown by the dotted line, so that the data is stored and read out on a non-interfering basis. By appropriately selecting the desired context, or p value, for the OUT2T, the desired decimation-by-two output is provided. Since all of the decimation by powers of two results are available in the output context register 28 at any given time, the same FIR filter output may be accessed by different end users to achieve any desired decimation by powers of two up to 1/2m.

Thus the present invention provides a FIR filter for programmable decimation by powers of two that uses context registers and just one set of multipliers and adders with cascaded timing circuits, the output of which is fed back to the input, to produce simultaneously all decimation by powers of two results up to 1/2m from which a desired decimation result may be programmably selected.


Anspruch[de]
  1. Vorrichtung für eine programmierbare Dezimation mit Zweierpotenzen, wobei die Vorrichtung folgendes umfasst:
    • einen Dezimations-FIR-Filter mit einem Eingang zum Empfang eines Eingangssignals, das um Zweierpotenzen dezimiert werden soll, und mit einem Ausgang, wobei der Ausgang zurück zu dem Eingang geführt wird, und wobei der Dezimations-FIR-Filter Kontextregister (18, 20, 22) aufweist, so dass ein zum Vorsehen des Ausgangs gekoppeltes Ausgangs-Kontextregister (28) gleichzeitig alle Ergebnisse einer Dezimation durch zwei bis zu 1/2m aufweist, wobei m gleich der Anzahl der Kontexte für jedes Kontextregister ist; und
    • eine Einrichtung zur Taktung des Dezimations-FIR-Filters für jede Dezimation einer Zweierpotenz, die als Eingabe ein anfängliches Taktsignal und ein anfängliches gültiges Signal auf der halben Frequenz des anfänglichen Taktsignals aufweist, und die als Ausgabe Taktsignale an den Dezimations-FIR-Filter vorsieht, wobei die Kontextregister selektiv freigegeben werden, wobei ein gewünschtes Dezimationsergebnis zur Ausgabe durch Auswahl eines geeigneten Ausgangs-Dezimationsfaktors 2p bestimmt wird, mit 0 ≤ p ≤ m.
  2. Vorrichtung nach Anspruch 1, wobei der Dezimations-FIR-Filter folgendes umfasst:
    • einen n-Anzapfungs-FIR-Filter, der erstens die Kontextregister verwendet, wobei die ungeraden Anzapfungen summiert werden, um ein ungerades dezimiertes Ergebnis vorzusehen, und zweitens die Kontextregister, wobei die geraden Anzapfungen summiert werden, um ein gerades dezimiertes Ergebnis vorzusehen;
    • eine Einrichtung zum Summieren (24, 26) der ungeraden und geraden dezimierten Ergebnisse, um die Ausgabe über die Ausgangs-Kontextregister vorzusehen; und
    • eine Einrichtung zur Auswahl (12) zur Kopplung mit dem Eingang des n-Anzapfungs-FIR-Filters entweder des Eingangssignals oder der Ausgabe aus dem Ausgangs-Kontextregister als Reaktion auf als anfängliches gültige Signal.
  3. Vorrichtung nach Anspruch 2, wobei die Takteinrichtung eine Mehrzahl von Taktschaltungen (29) aufweist, die in Kaskade geschaltet sind, wobei jede Schaltung einen Taktfreigabeeingang und einen gültigen Eingang aufweist, wobei jeder gültige Eingang die halbe Frequenz des Taktfreigabeeingangs aufweist, und mit einem Taktfreigabeausgang mit der halben Frequenz des Taktfreigabeeingangs und einem gültigen Ausgang mit der halben Frequenz des gültigen Eingangs, wobei der Taktfreigabeausgang und der gültige Ausgang entsprechende Taktfreigabe- und gültige Eingänge in die nächste Taktschaltung der Kaskade darstellen, wobei die Taktschaltung ein Paar phasenungleicher Freigabesignale (M) für die Kontextregister vorsieht, wobei eines der Freigabesignale für die Kontextregister für die ungeraden dezimierten Ergebnisse verwendet wird, während das andere Freigabesignal für die Kontextregister für die geraden dezimierten Ergebnisse verwendet wird, wobei es sich bei den Freigabesignalen und den gültigen Ausgängen um Taktsignale handelt.
  4. Vorrichtung nach Anspruch 3, wobei jede Taktschaltung folgendes umfasst:
    • ein Wechselregister (30), das einen Eingang und ein Paar von Ausgängen mit entgegengesetzter Polarität (Q, Q)aufweist, wobei einer der Ausgänge mit dem Eingang gekoppelt ist, wobei die Ausgänge den Zustand für jede Zustandsänderung des gültigen Eingangs ändern;
    • eine Einrichtung zum Erzeugen (32) eines der Freigabesignale aus dem gültigen Eingang und dem Eingang des Wechselregisters und zum Erzeugen (36) des anderen Freigabesignals aus dem gültigen Eingang und dem Ausgang des nicht mit dem Eingang gekoppelten Wechselregisters; und
    • eine Einrichtung zum Erzeugen (40) des gültigen Ausgangs und (38) des Taktfreigabeausgangs als eine Funktion des gültigen Eingangs, des Taktfreigabeeingangs und des nicht mit dem Eingang gekoppelten Ausgangs des Wechselregisters.
Anspruch[en]
  1. An apparatus for programmable powers of two decimation comprising:
    • a decimation FIR filter having an input for receiving an input signal to be decimated by powers of two and an output, the output being fed back to the input and the decimation FIR filter having context registers (18,20,22) such that an output context register (28) coupled to provide the output simultaneously contains all decimation by two results up to 1/2m, where m is the number of contexts for each context register; and
    • means for timing the decimation FIR filter for each power of two decimation having as inputs an initial clock signal and an initial valid signal at one-half the frequency of the initial clock signal and providing as outputs timing signals to the decimation FIR filter selectively enabling the context registers, a desired decimation result for output being determined by selecting an appropriate output decimation factor 2p where 0≤p≤m.
  2. The apparatus as recited in claim 1 wherein the decimation FIR filter comprises:
    • an n-tap FIR filter using, firstly, the context registers having odd taps summed together to provide an odd decimated result and secondly the context registers having even taps summed together to provide an even decimated result;
    • means for summing (24,26) the odd and even decimated results to provide the output via the output context register; and
    • means for selecting (12) for coupling to the input of the n-tap FIR filter either the input signal or the output from the output context register in response to the initial valid signal.
  3. The apparatus as recited in claim 2 wherein the timing means comprises a plurality of timing circuits (29) coupled in cascade, each having a clock enable input and a valid input, the valid input being one-half the frequency of the clock enable input, and having a clock enable output at one-half the frequency of the clock enable input and a valid output at one-half the frequency of the valid input, the clock enable output and valid output being respective clock enable and valid inputs to the next timing circuit in the cascade, each timing circuit providing a pair of out-of-phase enabling signals (M) for the context registers, one of the enabling signals for the context registers used for the odd decimated results and the other for the context registers used for the even decimated results, the enabling signals and valid outputs being the timing signals.
  4. The apparatus as recited in claim 3 wherein each timing circuit comprises:
    • a toggle register (30) having an input and a pair of outputs of opposing polarity (Q,Q), one of the outputs being coupled to the input, the outputs changing state for each change of state of the respective valid input;
    • means for generating (32) one of the enabling signals from the valid input and the input of the toggle register and for generating (34) the other of the enabling signals from the valid input and the output of the toggle register not coupled to the input; and
    • means for generating (40) the valid output and (38) the clock enable output as a function of the valid input, the clock enable input and the output of the toggle register not coupled to the input.
Anspruch[fr]
  1. Appareil pour une décimation à la puissance deux programmable comprenant :
    • un filtre à réponse impulsionnelle finie (en anglais « FIR ») de décimation ayant une entrée pour recevoir un signal d'entrée à décimer par des puissances deux et une sortie, la sortie étant ramenée à l'entrée et le filtre FIR de décimation ayant des registres de contexte (18, 20, 22) de sorte telle qu'un registre de contexte de sortie (28) couplé pour fournir la sortie contient simultanément tous les résultats de la décimation par deux jusqu'à Sm, où m est le nombre de contextes pour chaque registre de contexte ; et
    • des moyens pour synchroniser le filtre FIR de décimation pour chaque décimation à la puissance deux ayant comme entrées un signal d'horloge initial et un signal valide initial à la moitié de la fréquence du signal d'horloge initial et fournissant comme sorties des signaux de synchronisation au filtre FIR de décimation activant sélectivement les registres de contexte, un résultat de décimation voulu pour la sortie étant déterminé en sélectionnant un facteur de décimation de sortie approprié 2p dans lequel 0 ≤ p ≤ m.
  2. Appareil selon la revendication 1 dans lequel le filtre FIR de décimation comprend :
    • un filtre FIR à n-prises utilisant, premièrement, les registres de contexte ayant des prises impaires ajoutées pour fournir un résultat décimé impair et, deuxièmement, le registre de contexte ayant des prises paires ajoutées pour fournir un résultat décimé pair ;
    • des moyens pour ajouter (24, 26) les résultats décimés impairs et pairs pour fournir la sortie via le registre de contexte de sortie ; et
    • des moyens pour sélectionner (12) pour coupler à l'entrée du filtre FIR à n-prises soit le signal d'entrée soit la sortie du registre de contexte de sortie en réponse au signal valide initial.
  3. Appareil selon la revendication 2 dans lequel les moyens de synchronisation comprennent une pluralité de circuits de synchronisation (29) couplés en cascade, chacun ayant une entrée de validation d'horloge et une entrée valide ; l'entrée valide étant la moitié de la fréquence de l'entrée de validation d'horloge, et ayant une sortie de validation d'horloge à la moitié de la fréquence de l'entrée de validation d'horloge et une sortie valide à la moitié de la fréquence de l'entrée valide, la sortie de validation d'horloge et la sortie valide étant des entrées de validation d'horloge et valide respectives vers le prochain circuit de synchronisation dans la cascade, chaque circuit de synchronisation fournissant une paire de signaux de validation déphasés (4) pour les registres de contexte, l'un des signaux de validation pour les registres de contexte utilisés pour les résultats décimés impairs et l'autre pour les registres de contexte utilisés pour les résultats décimés pairs, les signaux de validation et les sorties valides étant les signaux de synchronisation.
  4. Appareil selon la revendication 3 dans lequel chaque circuit de synchronisation comprend :
    • un registre de bascule (30) ayant une entrée et une paire de sorties de polarité opposée (Q, Q), l'une des sorties étant couplée à l'entrée, les sorties changeant d'état pour chaque changement d'état de l'entrée valide respective ;
    • des moyens pour générer (52) l'un des signaux d'activation à partir de l'entrée valide et de l'entrée du registre de bascule et pour générer (34) l'autre des signaux de validation à partir de l'entrée valide et de la sortie du registre de bascule non couplée à l'entrée ; et
    • des moyens pour générer (40) la sortie valide et (38) la sortie de validation d'horloge comme une fonction de l'entrée valide, de l'entrée de validation d'horloge et de la sortie du registre de bascule non couplée à l'entrée.






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