The present invention relates to a communication system, and more particularly to a method and apparatus for transmitting a signal in such a communication system.

New cellular standards such as EDGE and EDGE phase II require transmitters with low error vector magnitude (EVM) in order to limit the link level degradation for high-speed data transmission. A prior art modulator is shown in FIG. 1. This type of modulator uses an In-Phase/Quadrature Phase (IQ) modulator with analog balancing using varactors and digital-to-analog (D/A) converters 103 to control the quadrature local oscillator (LO) network in order to minimize image components. As depicted in FIG. 1, most direct IQ modulators today use a local oscillator set at the selected RF channel and use a phase locked loop (PLL) synthesizer 106 with steps equal to the channel spacing (e.g., 200khz for GSM). In this implementation, the LO leakage is then centered directly at the RF channel (a typical value is in the range of 30-35 dB of LO leakage), as is the image component introduced by a gain/phase imbalance of the IQ modulator. A typical value of 30-35 dB of image rejection is achieved using a polyphase RC/CR quadrature network 109. Considering an image rejection of IMr = 35 dB as best case with an LO leakage of LO leak = 30dB, the total EVM achieved by this system is in the range of EVM = 4.28% (or EVM = 2.03% if the LO leakage is removed from the EVM calculation) under the assumptions of having a LO phase noise of 0.5 degrees rms, the third order intermodulations of the IQ baseband at -60 dBc and a power amplifier (PA) with a limited non-linearity.

An other prior art modulator showing a similar structure as used in the present application is known from EP-A-0 999 645.

In order that the present invention may be better understood, an embodiment thereof will now be described by way of example only, with reference to the accompanying drawings in which:

• FIG. 1 generally depicts a block diagram of a prior art IQ modulator;
• FIG. 2 generally depicts a transmitter capable of operating in either a low IF (LIF) mode or in a very low IF (VLIF) mode in accordance with the invention;
• FIG. 3 generally depicts a block diagram of a first order complex balanced multiplier suitable for use in the modulator of FIG. 2;
• FIG. 4 generally depicts a block diagram similar to FIG. 3 depicting a mathematical model of a balanced multiplier suitable for use in the transmitter of FIG. 2;
• FIG. 5 generally depicts a power spectrum of an EDGE 8PSK modulated signal and the generated image components when operating at Very Low IF;
• FIG. 6 generally depicts an alternate implementation which combines a balanced complex multiplier with modulation phase mapping at a operating frequency equal to the data symbol rate in accordance with the invention;
• FIG. 7 further depicts the phase accumulator of FIG. 6 in accordance with the invention; and
• FIG. 8 generally depicts the digital quadrature local oscillator as shown in FIG. 2 in accordance with the invention.

Stated generally, transmitter uses a digital very low IF with a digital complex balanced multiplier in conjunction with a fractional N synthesizer which reduces the impact of IQ quadrature circuitry imbalance and LO leakage in the overall error vector magnitude (EVM) budget while still meeting spectral mask purity requirements is disclosed. In addition, the presence of the digital transmit balanced complex multiplier offers the capability to perform a digital phase/amplitude pre-distortion adjustment as required.

Stated more specifically, in a first embodiment, a transmitter for use in a wireless communication system is provided according to the features of Claim 1. The balanced complex multiplier provides a gain and phase adjustment related to at least a component imbalance in the IQ modulator circuitry. Additionally, the gain and phase adjustment is performed at a specific frequency to produce the signal having a reduced IF LO leakage or at a plurality of frequencies to produce the signal having a reduced IF LO leakage.

The transmitter in this embodiment also includes a low IF value which is in the range of 2*channel spacing to 10*channel spacing. The balanced complex multiplier operates in either a 1X symbol rate mode or an oversampling mode and includes an AC coupling network which is implemented on the I and Q baseband outputs to reduce the level of IF LO leakage. The transmitter in this embodiment also includes a TX clean-up filter at the IF value which is implemented to reduce the image level and the IF LO leakage prior to transmission.

In an alternate embodiment a transmitter for use in a wireless communication system includes a balanced complex multiplier having as inputs I and Q signals and signals from a digital local oscillator (LO) and producing I and Q output signals at a first intermediate frequency (IF) and IQ modulator circuitry having as input the I and Q output signals at a very low IF value and a LO signal at a final transmit frequency and producing a signal having a reduced image level and a reduced LO leakage prior to transmission. In this embodiment, the very low IF value is in the range of the channel spacing/10 to the channel spacing/2 and the signal produced has a reduced image level displaced by twice the low IF value without compromising the output spectrum.

FIG. 2 generally depicts a block diagram of a transmitter 200 in accordance with the invention. As shown in FIG. 2, digital IQ input signals 201, 202 generated by a pulse shaping filter 203 from a serial data transmission (SDTX) are processed by a balanced complex multiplier 204 which is driven by signals output from a digital local oscillator (LO) 218 to produce digital IQ output signals 205, 206. As shown in FIG. 2, these signals 205, 206 are at a low IF as compared to the prior art transmitter implementation where these signals would reside at DC. These signals 205, 206 are then converted to analog signals via DACs 103 and low pass filtered via filters 112. The resulting analog I and Q signals drive respective quadrature IQ modulators 207, 208 where the local oscillator (LO) 212 is based on a fractional N synthesizer with fine tuning resolution.

As shown in FIG. 2, balanced complex multiplier 204 operates at the oversampling clock, i.e. at the same frequency as input signals 201 and 202, which normally for a communication system compatible with EDGE is 16 times higher than the symbol rate. Additionally, the balanced complex multiplier 204 provides several functions in accordance with the invention. First, it provides gain and phase imbalance correction of the IQ modulator circuitry 215 in order to reduce the image component produced by the circuitry 215. Second, it moves the I & Q signals to a shifted IF or in general adds a phase modulation O_sd(t) or 2*pi*DIF*t in the particular case of Low IF or Very Low IF in order to offset the image component by 2*O_sd from the selected radio frequency (RF) transmit (TX) channel and to get additional image reduction due to the receive (RX) filter. It also moves the LO leakage at O_sd in order to reduce the LO leakage contribution in the overall EVM. Finally, in an additional embodiment, it may be used to provide a partial AM/PM correction of the overall transmitter since it allows a phase component to be beneficially added to compensate for the overall phase distortion of the transmitter.

As shown in the preferred embodiment of FIG. 2, either a very low IF (VLIF) in the range of 20 to 80 kHz or a low IF (LIF) in the range of 1 to 4 MHz (nominally 2 MHz) is chosen to generate signals I_out 205 and Q_out 206. In the VLIF mode, after these signals are converted to analog and filtered, they are then up-converted to the final TX frequency. In the LIF mode, these signals are up-converted to the final TX frequency by a fixed IF in the range of 100 MHz where a TX IF filter 221 cleans up the spectrum by reducing the level of IF LO leakage which is 100 MHz + 2 MHz away (for the case of Low IF only). Filter 221 also reduces the level of the image at the frequency offset of 100 MHz + 4 MHz before the filtered output signal 224 is up-converted to the final transmit frequency using an upconverter mixer 226.

In this LIF transmitter topology, the choice of the 2 MHz IF with IQ modulator circuitry 215 allows the generation of a 100 MHz modulated signal with the imperfections of the IF LO leakage and the corresponding image moved in frequency away from the transmitted channel by a frequency offset of 2 MHz and 4 MHz respectively. In addition, the level of these imperfections is reduced. The IF LO leakage is reduced through the use of AC coupling on the Low IF IQ signals to filter the DC component. The image level is reduced through the use of the balanced complex multiplier 204 to compensate for the gain and phase mismatches. Further imperfections are filtered by the TX cleanup filter 221 such that the overall imperfections are below the minimum requirements of the spectrum mask; for example, -60 dBc for EDGE. The Low IF IQ modulator reduces the level of images at -35 dBc, such that the TX cleanup filter 221 only requires -35 dB of attenuation at 4 MHz frequency offset to achieve -60 dBc.

The balanced complex multiplier 204 using first order correction is shown in FIG. 3 in accordance with the invention. The complex balanced multiplier 204 comprises a Q-path gain adjustment means 320; first, second, third and fourth multipliers 331, 332, 333, 334; and first and second adder/subtractors 341, 342. Digital LO 218 receives a phase signal O_sd from an IF LO generated by a two phase accumulators 801, 802 as shown in FIG. 8 which increments at a fixed step equal to a value of phase 2*pi*DIF/f_in where DIF is the programmed IF value and f_in is the frequency of the operating clock. The phase output accumulates the fixed step value 2*pi*DIF/f_in at every clock cycle of f_in to get the total phase 2*pi*DIF/f_in*n where n is the neme clock cycle used by the digital IF (e.g., if n=5, then 5 clock cycles have elapsed that have accumulated 5 values in the digital IF accumulator). As shown in FIG. 8, the Q-path accumulator loads the phase correction β at the beginning of a transmission. The phase accumulators 801, 802 outputs an address to a ROM table 805 which outputs cos(O_sd), sin(O_sd), cos(O_sd + β) and sin(O_sd + β) signals, which are then applied to the second inputs of the first, second, third and fourth multipliers 331, 332, 333, 334 respectively. Additionally, the first and second multipliers 331, 332 have the digital I-path signal I_in that are generated by the pulse shaping filters 203 applied to their first inputs, while the third and fourth multipliers 333, 334 have the digital Q-path signal Q_in that are generated by the pulse shaping filters 203 applied to their first inputs. The outputs of the first and fourth multipliers 331, 334 are applied as inputs to the first adder/subtractor 341 which outputs a digital baseband I signal while the outputs of the second and third multipliers 332, 333 are applied as inputs to the second adder/subtractor 342 which outputs a digital baseband Q signal Q_out.

The effect of the complex balanced multiplier 204 is to generate output I and Q signals I_out and Q_out from input signals I_in, Q_in and O_sd, as set out in equation (1) below: V_out = I_out + jQ_out = (I_in + jA_de^jβQ_in)e^jO_sd or V_out(n) = 1 / (2) [V_in(n)e^jO_sd(n) (1 + Ad₀e^jb₀)] + 1 / (2) [V*_in(n)e^-jO_sd(n) (1 - Ad₀e^-jb₀)] where V_in = I_in + jQ_in and V *_in = I_in - jQ_in (where * stands for vector conjugate). This corresponds to: I_out(n) = cos(b₀)A(n)cos(O_sd(n) + O(n)) Q_out(n) = Ad₀ cos(b₀)A(n)sin(O_sd(n)+O(n) + b₀). From equation (1), it can be seen that Q_in may differ from what it is supposed to be because of relative imbalances between the I and Q paths by 1/A_d in gain and -β in phase. The effect of the balanced complex multiplier 204 is to correct the imbalance as desired. Unfortunately, the imbalance between the paths will not be constant over frequency due to mismatches in filters 112. Thus, in this embodiment, the balanced complex multiplier 204 of FIG. 2 is only able to exactly balance the I and Q paths at a single frequency. Equation (2) can be expanded for multiple frequency correction, in alternate embodiments, to become: V_out(n) = 1 / (2) [V_in(n)e^jO_sd(n)(1 + Ad₀e^jb₀)] + 1 / (2) [V*ⁱⁿ(n)e^jO_sd(n)(1 - Ad₀e^-jb₀)] +1 / (2) [V_in(n - 1)e^jO_sd(n)(1 + Ad₁e^jb₁)] +1 / (2) [V*_in(n - 1)e^jO_sd(n)(1 - Ad₁e^-jb₁)] + ...1 / (2) [V_in(n - k)e^jO_sd(n)(1 + Ad_ke^jb_k)] + 1 / (2) [V*_in(n - k)e^jO_sd(n)(1 - Ad_ke^-jb_k)] +

In order to fully describe the imbalance between the paths created by the differences in the analogue components contained in these paths, one must consider the imbalances as being caused by a filter having a Finite Impulse Response (FIR) given by equation (6) below: H_imbalance(z) = 1 / (A_d0)·e^-jβ₀ + 1 / (A_d1)·e^-jβ₁ · z^-1 + 1 / (A_d2)·e^-jβ₂ · z^-2 + ... Clearly, to counter the effect of such an FIR one needs to provide a filter or equivalent means having the response given by equation (7) below: H_balance(z) = A_d0 · e^+jβ₀ + A_d1 · e^+jβ₁· z^-1 + A_d2 · e^-jβ₂ · z^-2 + ... From equation (7), it is apparent that the first-order compensation provided by balanced complex multiplier 204 corresponds to the first term of H_balance. In order to provide higher-order compensation or balancing, one could provide a dedicated digital filter having an FIR to compensate for the imbalance up to as many orders as desired. However, it is preferable to re-use some of the elements of the complex multiplier contained within the digital VLIF mixer stage.

A model for balanced complex multiplier 204 is shown in FIG. 4. This is a mathematical vector representation of the IQ modulator with the presence of IQ mismatches, i.e. H_balance not equal to 1. The first mixer 401 with the * is a representation of a balanced complex multiplier. With reference to this figure, when H_balance from equation (7) is equal to 1, perfect balance exists and no image component is generated. However, when an imbalance exists, a path for the image component is generated through 1-H_balance in such a way as to compensate the created image component introduced by IQ modulator circuitry 215 as will be shown.

A model for IQ modulator circuitry 215 is given by equation (8): S(t) = (V_outm+V*_outm) / (2) where S(t) is the output of IQ modulator circuitry 215 which is a real signal and V_outm is the equivalent output vector of IQ modulator circuitry 215. Given the presence of a gain A_d and a phase mismatch of IQ modulator circuitry 215, then V_outm can be expressed by: V_outm = e^{j(ω_RFt+O_sd(t))}[V_inm (Ade^jb - 1) / (2)] + e^{j(ω_RFt+O_sd(t))} [V*_inm (Ade^jb + 1) / (2)]. Note that the first term represents the image component that will be at a phase offset of +2O_sd (since V_sd is already phase shifted by +O_sd(t) by balanced complex multiplier 204) from the RF channel while the second term is the wanted channel centered at the RF channel (since V*_inm is phase shifted by -O_sd(t)).

Now, if balanced complex multiplier 204 and IQ modulator circuitry 215 driven by synthesiser 206 operating at O_sd, then the resulting output is: V_outm = e^{j(ω_RFt+2O_sd(t))} [V_in (Ade^jb - Ad₀e^jb₀) / (2)] +e^j(ωRF_t) [V*_in (Ade^jb + Ad₀e^-jb₀) / (2)] Where V_in is the input of the balanced complex multiplier 204 and V_inm is the output of the balanced IQ multiplier. The first term represents the remaining image component at 2O_sd offset and is nulled if perfect balancing correction is performed, i.e. if Ade^jb = Ad₀e^jb₀. The second term is the wanted channel at zero offset multiplied by a gain factor, which in the case of perfect balancing is Ad₀cos(b₀). This gain factor is dependent upon the gain and phase imbalance of IQ modulator circuitry 215 and can be compensated digitally by dividing V_in by Ad₀cos(b₀). The image rejection ration is then equal to: Ade^jb + Ad₀e^-jb₀ / (Ade^jb - Ad₀e^jb₀).

To verify the inventive concept, simulations were performed for certain scenarios. The first scenario is for a very low IF (i.e., O_sd = 2πF_fi). The model includes a D/A resolution of 10 bits, a 4th order Butterworth low pass filter at 800 kHz bandwidth, a non-linear IQ modulator specified by its second and third order rejection IM2 and IM3, a programmable synthesiser at F_fi with a phase noise of 0.5 degrees rms, a linearised GMSK receive filter to measure the EVM and a non-linear power amplifier (PA). FIG. 5 generally depicts a very low IF transmit (TX) image and output channel for channel spectrum related to Enhanced Data rates for GSM Evolution (EDGE) modulation. As shown in FIG. 5, a very low IF with F_fi = 100 kHz with an image rejection of 35 dB appearing at -200 kHz was implemented. Important to note is that the choice of the IF value is critical in order to optimize the reduction of the EVM and still meet the spectral mask as defined by the GSM 05.05 template shown in FIG. 5. It was found that the baseband non-linearity of the IQ modulator is critical for this system, mainly the IM3 since when operating at F_fi, the non-linearity modulation is shifted at 3 F_fi. Higher F_fi means better EVM rejection, but higher sensitivity to IM3 for the modulator.

A comparison between a prior art IQ modulator and a very low IF (or Direct IQ modulator F_fi = 0) using balanced complex multiplier 204 is shown below. In the prior art case, F_fi = 0, IM2=IM3=60 dBc, image rejection = -35 dB, LO leakage = -30 dBc, LO phase noise = 0.5 degrees rms and a non-linear PA is implemented. In this example, EVM = 4.28 % (including LO leakage) or 2.03 % (without LO leakage). In an example in accordance with the invention where a direct IQ modulator is used with balanced complex multiplier 201, F_fi= 0, IM2=IM3=60 dBc, image rejection = -40 dB (due to digital correction), LO leakage = -30 dBc, LO phase noise = 0.5 degrees rms and a non-linear PA is implemented. In this example, EVM = 4.08 % (including LO leakage) or 1.51 % (without LO leakage). In another example in accordance with the invention, where a very low IF IQ modulator is used with balanced complex multiplier 201, F_fi = 65 kHz, IM2=IM3=60 dBc, image rejection = -40 dB (due to digital correction), LO leakage = -30 dBc, LO phase noise = 0.5 degrees rms and a non-linear PA is implemented. In this example, EVM = 2.76 % (including LO leakage). As can be seen, the improvement of using the very low IF IQ modulator rather than a prior art modulator is in the range of 1.50 % on the EVM, which is 35 % improvement.

FIG. 6 generally depicts an alternate implementation which combines a balanced complex multiplier with modulation phase mapping at a operating frequency equal to the data symbol rate in accordance with the invention while FIG. 7 further depicts the phase accumulator of FIG. 6 in accordance with the invention. As shown in FIG. 6, the SDTX input is the input data to be transmitted at a bit rate f_b and represents the data input to the phase mapping circuitry 600. The phase mapping mapped in block 600 for 3 bits is an equivalent phase symbol for an EDGE-compatible system (as an example) at a rate of 1X= f_b/3. At this point, the signals I_phase adjust 701 and Q_{phase adjust} 702 are added to the generated Low IF phase in phase accumulator 603 to generate two phase values Ifphase_I 604 and Ifphase_Q 605 which each address ROM tables 608, 609 respectively to generate a cos and sin signals labelled TM_I 612 and TM_Q 613. Signals TM_I 612 and TM_Q 613 are at the symbol rate 1X and are pulse shaped filtered and oversampled to a higher frequency clock with a Complex Filter 615 (Complex FIR or Complex IIR) since the spectrum of the input TM_I + j*TM_Q is frequency shifted to a Low IF value to produce signals I_out 205 and Q_out 206 in this alternate implementation in accordance with the invention.

While the invention has been particularly shown and described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein within the scope of the invention, as described in the accompanying claims. The corresponding structures, materials, acts and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or acts for performing the functions in combination with other claimed elements as specifically claimed.