PatentDe  


Dokumentenidentifikation EP0989664 12.01.2006
EP-Veröffentlichungsnummer 0000989664
Titel TREIBERVORRICHTUNG FUR EINEN BÜRSTENLOSEN DREIPHASENMOTOR
Anmelder Rohm Co. Ltd., Kyoto, JP
Erfinder HASHIMURA, Tomohide, Kyoto-shi, Kyoto 615-0045, JP
Vertreter Glawe, Delfs, Moll, Patentanwälte, 80538 München
DE-Aktenzeichen 69832703
Vertragsstaaten DE, FR, GB, IT, NL
Sprache des Dokument EN
EP-Anmeldetag 18.02.1998
EP-Aktenzeichen 989043955
WO-Anmeldetag 18.02.1998
PCT-Aktenzeichen PCT/JP98/00698
WO-Veröffentlichungsnummer 0098037621
WO-Veröffentlichungsdatum 27.08.1998
EP-Offenlegungsdatum 29.03.2000
EP date of grant 07.12.2005
Veröffentlichungstag im Patentblatt 12.01.2006
IPC-Hauptklasse H02P 6/18(2006.01)A, F, I, ,  ,  ,   
IPC-Nebenklasse H02P 6/14(2006.01)A, L, I, ,  ,  ,      

Beschreibung[en]
Technical field

The present invention relates to a driving device for a three-phase brushless motor used to rotate a head in, for example, a portable MD (MiniDisk) apparatus or a VCR (videocassette recorder).

Background art

In a conventional driving device for a three-phase brushless motor, the back electromotive forces VU, VV, and VW appearing in the coils of the motor are individually compared with the common-terminal voltage VN of the coils by a comparator to obtain three-phase square-wave signals PU, PV, and PW, which are then directly synthesized together to produce a speed signal (hereafter referred to as an "FG (frequency generator) signal") and drive signals DUU, DUL, DVU, DVL, DWU, and DWL.

The FG signal is then subjected to 30-degree phase shifting performed by a phase shifting circuit so as to be converted into a phase signal FGP. In accordance with this phase signal FGP and the above-mentioned drive signals DUU, DUL, DVU, DVL, DWU, and DWL, drive currents are supplied from a current supply circuit such as a power transistor circuit to the three-phase brushless motor.

However, in this conventional driving device, as long as the motor is rotating stably, the square-wave signals PU, PV, and PW exhibit stable waveforms as shown in Fig. 6; however, as shown in Fig. 7, when irregular variations occur in the back electromotive forces VU, VV, and VW as a result of polarity inversion caused by braking applied as in the period T, or by noise appearing as indicated by reference numerals 40 and 41, or by other factors, the square-wave signals PU, PV, and PW exhibit irregular variations accordingly.

Thus, the FG signal and the drive signals DUU, DUL, DVU, DVL, DWU, and DWL, which are produced from the square-wave signals PU, PV, and PW, are also affected such that the FG signal is no longer usable if left intact and that the drive signals DUU, DUL, DVU, DVL, DWU, and DWL, cause unstable rotation of the motor, making it impossible to obtain stable rotation characteristics. Note that, in Figs. 6 and 7, only the drive signals DUU and DUL are shown, and the other drive signals DVU, DVL, DWU, and DWL are omitted.

EP 0 429 412 A discloses a method for controlling a multi phase brushless motor without position sensors for a rotor. The control is carried out by detecting signals being representative of the difference voltage between ends of the phase windings and the star-centre, by selecting the signal relating to a non excited phase winding, by detecting the crossing by the selected signal of a reference voltage, and by generating a logic commutation signal upon the crossing. Furthermore, these signals are masked for a sufficiently long time before restarting the circle.

US 5,017,845 A discloses a brushless motor and an operating method thereof. The slope of the back electromotic force is sampled and a zero or a predetermined slope condition is searched. A masking circuit is included to prevent an unwanted commutation.

JP 08-251978 A teaches that when a masking means masks a signal obtained from the counter electromotive forces, noise can be eliminated therefrom at the time of conduction. However, the masking means masks only for a predetermined period immediately after a level-change-point.

In JP 08-033382 A voltage waveforms u, v, w and output signals from a mask-signal generator are input to a counter-electromotive-force detector. By this arrangement, since only the signal of counter-electromotive force according to the rotation of the motor can be detected, the driving current which drives the driving calls can be changed over smoothly. The masking is not designed for preventing noise from disrupting control of motor coils.

In JP 08-182379 A masking signals are produced to mask signals generated only when an output current is cut off.

Disclosure of the invention

An object of the present invention is to provide a driving device for a three-phase brushless motor that offers stable rotation characteristics by preventing an FG signal and drive signals from being affected by polarity inversion resulting from braking applied, noise appearing, or other factors arising during rotation of the motor.

This and other objects of the present invention are achieved by a three-phase brushless motor device according to claim 1. The dependent claims treat further developments of the present invention.

Brief description of drawings

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of the gate circuits and the selector circuit employed therein, Fig. 3 is a waveform diagram of the signals observed at various points therein, Fig. 4 is a diagram showing the configuration of the comparator circuit employed in the device shown in Fig. 1, and Fig. 5 is a circuit diagram showing a part of the power transistor circuit employed in the device shown in Fig. 1. Fig. 6 is a waveform diagram of the signals observed at various points in a conventional driving device, and Fig. 7 is a waveform diagram illustrating how signals are affected by braking and noise therein.

Best mode for carrying out the invention

Hereinafter, an embodiment of the present invention will be described with reference to Figs. 1 to 5. Fig. 1 is a block diagram showing the configuration of this embodiment. A driving device 11 drives a three-phase brushless motor 10 by supplying it with drive currents IOU, IOV, and IOW. The driving device is formed, for example, as an IC (integrated circuit).

The motor 10 is provided with coils 10A, 10B, and 10C for the U, V, and W phases, respectively. These Coils 10A, 10B, and 10C are arranged at such intervals that their phases differ by 120 degrees from one another. The back electromotive forces VU, VV, and VW appearing in the coils 10A, 10B, and 10C, respectively, are, together with the common-terminal voltage VN, fed to the driving device 11 so as to be individually subjected to comparison performed by comparators in a comparator circuit 1. The comparator circuit 1 outputs, as the results of comparison, square-wave signals PU, PV, and PW. As shown in Fig. 4, the comparator circuit 1 is composed of three comparators 1a, 1b, and 1c. The square-wave signals PU, PV, and PW are then subjected to passage control performed by gate circuits 2, 3, and 4, and are thereby output as inverted signals MU, MV, and MW.

Next, in a drive waveform synthesizing circuit 5, the signals MU, MV, and MW are synthesized together to produce drive signals DUU, DUL, DVU, DVL, DWU, and DWL. For example, the signal DUU is so synthesized as to rise at a rising edge of the signal MU and fall at a rising edge of the signal MV. The other signals DUL, DVU, DVL, DWU, and DWL are synthesized in a similar manner from the signals MU, MV, and MW. The signals DUU, DVU, and DWU differ in phase by 120 degrees from one another. Similarly, the signals DUL, DVL, and DWL differ in phase by 120 degrees from one another.

In an FG circuit 7, the exclusive-OR value of the signals MU, MV, and MW is calculated by means of an exclusive-OR gate, and then the NOT value of the thus calculated value is calculated to produce an FG signal (described later). Then, in a phase shifting circuit 8, the FG signal is subjected to 30-degree phase shifting so as to be formed into a phase signal FGP. The phase shifting circuit 8 is composed of, for example, a delay circuit.

In a power transistor circuit 6, power transistors are turned on and off in accordance with the drive signals DUU, DUL, DVU, DVL, DWU, and DWL and the phase signal FGP, and thereby drive currents IOU, IOV, and IOW having a regular cycle are produced. The drive currents IOU, IOV, and IOW are supplied to the motor coils 10A, 10B, and 10C, respectively. The power transistor circuit 6 serves as a current supply circuit.

For example, to produce the drive signal IOU, a pnp-type transistor Q1 and an npn-type transistor Q2 are connected together as shown in Fig. 5 so that, when the signal DUU is at a high level, the transistor Q1 is turned on to cause a current to flow from the direct-current supplied voltage Vcc through the transistor Q1 to the coil 10A and, when DUL is at a high level, the transistor Q2 is turned on to cause a current to flow from the coil 10A to ground. Note however that, in the power transistor circuit 6, the phase signal FGP is used as a timing signal for switching the drive signal IOU, and therefore the drive signal IOU shows a 30-degree phase difference relative to the level shifts in the drive signals DUU and DUL. The drive currents IOV and IOW are output in a similar manner. The thus obtained drive currents IOU, IOV, and IOW differ in phase by 120 degrees from one another.

In a selector circuit 9, as will be described later, the drive signals DUU, DUL, DVU, DVL, DWU, and DWL are switched in accordance with whether the FGP signal is at a high level or at a low level to produce select signals FBU1, FBU2, FBV1, FBV2, FBW1, and FBW2. The select signals FBU1, FBU2, FBV1, FBV2, FBW1, and FBW2 are fed back to the gate circuits 2, 3, and 4, where they are used to control passage of the square-wave signals PU, PV, and PW. The gate circuits 2, 3, and 4 and the selector circuit 9 together constitute what will hereafter be referred to as the masking circuit. The comparator circuit 1, the gate circuits 2, 3, and 4, the drive waveform synthesizing circuit 5, the FG circuit 7, the phase shifting circuit 8, and the selector circuit 9 together constitute a passage control means.

The detailed configuration of the masking circuit is shown in Fig. 2. The phase signal FGP fed to the selector circuit 9 is subjected to level inversion by a NOT gate (inverter) 9M. The drive signal DUL and the signal output from the NOT gate 9M are fed to a NAND gate 9A. The drive signal DWU and the phase signal FGP are fed to a NAND gate 9B.

The drive signal DVL and the signal output from the NOT gate 9M are fed to a NAND gate 9C. The drive signals DUU and the phase signal FGP are fed to a NAND gate 9D. The drive signal DWL and the signal output from the NOT gate 9M are fed to a NAND gate 9E. The drive signal DVU and the phase signal FGP are fed to a NAND gate 9F.

An AND gate 9G calculates the AND value of the signals output from the NAND gates 9A and 9F, and thereby outputs the signal FBV2. An AND gate 9H calculates the AND value of the signals output from the NAND gates 9A and 9B, and thereby outputs the signal FBU1. An AND gate 9I calculates the AND value of the signals output from the NAND gates 9B and 9C, and thereby outputs the signal FBW2.

An AND gate 9J calculates the AND value of the signals output from the NAND gates 9C and 9D, and thereby outputs the signal FBV1. An AND gate 9K calculates the AND value of the signals output from the NAND gates 9D and 9E, and thereby outputs the signal FBU2. An AND gate 9L calculates the AND value of the signals output from the NAND gates 9E and 9F, and thereby outputs the signal FBW1.

In the gate circuit 2, a NOT gate 2A inverts the level of the square-wave signal PU. Then, a NAND gate 2B calculates the NAND value of the signal output from the NOT gate 2A and the signal FBU1 fed from the selector circuit 9. Then, a NAND gate 2C calculates the NAND value of the signal output from the NAND gate 2B and the signal FBU2. Thus, the gate circuit 2 outputs the signal MU.

In the gate circuit 3, a NOT gate 3A inverts the level of the square-wave signal PV. Then, a NAND gate 3B calculates the NAND value of the signal output from the NOT gate 3A and the select signal FBV1. Then, a NAND gate 3C calculates the NAND value of the signal output from the NAND gate 3B and the signal FBV2. Thus, the gate circuit 3 outputs the signal MV.

In the gate circuit 4, a NOT gate 4A inverts the level of the square-wave signal PW. Then, a NAND gate 4B calculates the NAND value of the signal output from the NOT gate 4A and the select signal FBW1. Then, a NAND gate 4C calculates the NAND value of the signal output from the NAND gate 4B and the signal FBW2. Thus, the gate circuit 4 outputs the signal MW.

Now, how driving of the motor 10 (see Fig. 1) is achieved will be described with reference to Fig. 3, which shows the waveforms of the signals observed at various points in the driving device when the motor 10 rotates. In the motor coils 10A, 10B, and 10C, the back electromotive forces VU, VV, and VW are induced to appear repeatedly with a regular cycle by the drive currents IOU, IOV, and IOW. Here, the back electromotive forces VU, VV, and VW differ in phase by 120 degrees from one another. On the other hand, the common-terminal voltage VN varies with one third of the cycle of the back electromotive forces VU, VV, and VW as long as the motor 10 is rotating normally.

As described previously, in the comparator circuit 1, the back electromotive forces VU, VV, and VW are individually compared with the common-terminal voltage VN to obtain three-phase square-wave signals PU, PV, and PW. If inversion occurs in the waveforms of the back electromotive forces VU, VV, and VW as a result of phase inversion as caused by braking as indicated by reference numerals 21 and 22, irregular variations occur in the square-wave signals PU, PV, and PW as indicated by reference numerals 23 and 24.

If these square-wave signals PU, PV, and PW are fed directly to the drive waveform synthesizing circuit 5 as in the conventional driving device described earlier, it is impossible to drive the motor 10 normally. By contrast, in this embodiment, where the gate circuits 2, 3, and 4 are inserted in the stage subsequent to the comparator circuit 1 to perform masking on the square-wave signals PU, PV, and PW and thereby form them into the signals MU, MV, and MW, it is possible to drive the motor 10 normally.

Here, when the phase signal FGP is at a high level, the selector circuit 9 (see Fig. 2) feeds DWU as the signal FBU1 to the NAND gate 2B, and feeds DUU as the signal FBU2 to the NAND gate 2C. By contrast, when the phase signal FGP is at a low level, the selector circuit 9 feeds DUL to the NAND gate 2B, and feeds DWL to the NAND gate 2C.

The signals FBU1 and FBU2 have the following relationship. When the signal FBU1 is at a low level, the signal FBU2 is at a high level. When the signal FBU2 is at a low level, the signal FBU1 is at a high level. The signals FBU1 and FBU2 are never at a low level simultaneously.

Thus, when the signal FBU1 is at a low level, the signal MU is invariably at a low level irrespective of the level of the square-wave signal PU. By contrast, when the signal FBU2 is at a low level, the signal MU is invariably at a high level irrespective of the level of the square-wave signal PU.

That is, a variation in the square-wave signal PU is passed along to the signal MU only when the signals FBU1 and FBU2 are both at a high level; otherwise, any variation in the square-wave signal PU, as caused by noise or the like, is masked by the gate circuit 2, and thus is not passed along to the signal MU. The periods in which a variation in the square-wave signal PU is passed along through the gate circuit 2 to the signal MU are, for example, as indicated by hatching 30 and 31. These periods each last for one sixth of the cycle of the signal MU, and are repeated so as to include a level-shift point of the signal PU each. On the other hand, in the periods between those periods, the signal MU is kept at the level at which it is set after a level-shift point of the signal PU.

Similarly, the gate circuit 3 controls passage of the square-wave signal PV in accordance with the signals FBV1 and FBV2 output from the selector circuit 9 in such a way that a variation in the square-wave signal PV is passed along to the signal MV only when the signals FBV1 and FBV2 are both at a high level.

Moreover, the gate circuit 4 controls passage of the square-wave signal PW in accordance with the signals FBW1 and FBW2 output from the selector circuit 9 in such a way that a variation in the square-wave signal PW is passed along to the signal MW only when the signals FBW1 and FBW2 are both at a high level.

The periods in which a variation in the square-wave signals PV and PW is passed along through the gate circuits 3 and 4 to the signal MV and MW, respectively, are also indicated by hatching in Fig. 3. In this way, for each of the signals MU, MV, and MW, the periods indicated by hatching occur with one third of the cycle of the back electromotive forces in such a way as not to overlap among the signals MU, MV, and MW.

Now, for example, suppose that, at the moment when the drive signal DUL causes a transistor provided within the power transistor circuit 6 (see Fig. 1) to be turned from an on state to an off state, pulse-like noise 25 appears in the back electromotive force VV, and accordingly noise 26 appears in the signal PV. Even in this case, no noise appears in the signal MV because it has been subjected to masking as described above. Therefore, the noise 25 does not affect generation of the FG signal or the drive signals DUU, DUL, DVU, DVL, DWU, and DWL, and thus does not cause unstable rotation of the motor 10 (see Fig. 1).

The power transistors provided within the power transistor circuit 6 operate in accordance with the phase signal FGP and thus with a 30-degree phase difference from the drive signals DUU, DUL, DVU, DVL, DWU, and DWL, and accordingly the back electromotive forces VU, VV, and VW are induced with a 30-degree phase difference from the drive signals DUU, DUL, DVU, DVL, DWU, and DWL. Similarly, noise appears also at the moment when other transistors than those mentioned just above are turned from an on state to an off state; however, masking prevents also such noise from being passed along to the signals MU, MV, and MW.

Moreover, even if noise as indicated by reference numeral 27 appears in the back electromotive force VW as a result of randomly occurring external disturbance, the noise is passed along to the signal PW, but is not passed along to the signal MW except in the periods in which the signals FBW1 and FBW2 are both at a high level (i.e. the periods indicated by hatching in the figure). Thus, it is also possible to prevent external disturbance from affecting the drive signals DUU, DUL, DVU, DVL, DWU, and DWL.

Note that the periods indicated by hatching in Fig. 3 include time points at which the values of the voltages of the back electromotive forces VU, VV, and VW cross the value of the common-terminal voltage VN. By detecting such time points, the rotor position of the motor 10 is recognized to produce the FG signal and the drive signals DUU, DUL, DVU, DVL, DWU, and DWL. Therefore, in these periods, variations in the individual three-phase square-wave signals PU, PV, and PW need to be passed along to the signals MU, MV, and MW, and thus no masking is performed. In these periods indicated by hatching, the square-wave signals PU, PV, and PW turn from a high level to a low level or from a low level to a high level.

As described above, in this embodiment, the masking circuits 2 to 4 and 9 mask disturbances in waveforms caused by noise or the like, so that the signals MU, MV; and MW, which have been subjected to masking, are fed to the drive waveform synthesizing circuit 5 and the FG circuit 7. This makes it possible to obtain stable waveforms in the FG signal and the drive signals DUU, DUL, DVU, DVL, DWU, and DWL without using an external sensor, and thereby achieve stable rotation of the motor 10.

The power transistor circuit 6 may be provided separately from the IC 11. This makes it possible to drive a larger-sized motor 10. The driving device of this embodiment can be used also to achieve stable rotation with a motor that is so configured as to obtain an FG signal by the use of an external sensor such as a hole sensor.

Industrial applicability

As described heretofore, according to the present invention, masking is performed by a selector circuit and gate circuits, and therefore it is possible to prevent braking or noise from making the rotation of a motor unstable, and thereby enhance rotation characteristics. Moreover, a stable FG signal can be produced without using an external sensor, and therefore it is possible to reduce mount surface area, and thereby reduce costs. Thus, a driving device according to the present invention can be suitably used as a driving device for a three-phase brushless motor for use in a VCR or portable MD apparatus.


Anspruch[de]
  1. Treibervorrichtung (11) für einen bürstenlosen Dreiphasenmotor zum Speisen des bürstenlosen Dreiphasenmotors (10) mit dreiphasigen Treiberströmen (IOU, IOV, IOW), die sich bezüglich ihrer Phase um 120 Grad voneinander unterscheiden,

       wobei Durchgangssteuermittel vorgesehen sind, die die elektromotorischen Rückkräfte (VU, VV, VW), welche in drei Spulen (10A, 10B, 10C) erscheinen, die für jede Phase (U, V, W) in dem bürstenlosen Dreiphasenmotor (10) vorgesehen sind, individuell mit einer gemeinsamen Anschlussspannung (VN) der drei Spulen (10A, 10B, 10C) vergleichen und eine Wählschaltung (9) und Gate-Schaltungen (2, 3, 4) enthalten,

       die Wählschaltung (9), basierend auf Treibersignalen (DUU, DUL, Dvu, DVL, DWU, DWL) zum Ein- und Ausschalten der dreiphasigen Treiberströme (IOU, IOV, IOW) und einem Phasensignal (FGP), das von einem Geschwindigkeitssignal (FG) durch Durchführen einer Phasenverschiebung erzeugt worden ist, für jede der drei Phasen (U, V, W) zwei Wählsignale (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) erzeugen, die während einer vorbestimmten Periode, die einen Null-Kreuzungspunkt jeder elektromotorischen Rückkraft (VU, VV, VW) hat, sowohl an der Anstiegs als auch an der Abstiebsflanke desselben gleichzeitig auf einem hohen Pegel gehalten sind und außerhalb der vorbestimmten Periode, die einem halben Zyklus des Phasensignals (FGP) entspricht, eines derselben auf einem hohen Pegel gehalten wird, während das andere auf einem niedrigen Pegel gehalten wird;

       die Gate-Schaltungen (2, 3, 4) die Vergleichsausgänge individuell so maskieren, dass jeder der Vergleichsausgänge in der vorbestimmten Periode, die einen Pegelschiebepunkt derselben enthält, durch die Gate-Schaltung (2, 3,4) hindurchgehen kann, wenn die Gate-Schaltung (2, 3, 4) zwei Wählsignale (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) von der Wählschaltung (9) empfängt, die hoch sind und in einer Perode zwischen einer derartigen vorbestimmten Periode und einer nächsten derartigen vorbestimmten Periode auf einem hohen Pegel gehalten wird, auf welchem es nach dem Pegelschiebepunkt gesetzt worden ist, wenn die Gate-Schaltung (2, 3, 4) die zwei Wählsignale (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) von der Wählschaltung (9) empfängt, wobei eines auf einem hohen Pegel und das andere auf einem niedrigen Pegel ist, und

       wobei die Treiberströme (IOU, IOV, IOW) durch die Stromversorgungsmittel (6) in Übereinstimmung mit den aus der Durchgangssteuerung resultierenden Signalen erzeugt werden.
  2. Treibervorrichtung (11) für einen bürstenlosen Dreiphasenmotor nach Anspruch 1, weiterhin mit:
    • einer Treibersignalform-Synthetisierschaltung (5) zum Synthetisieren jedes der Vergleichsausgänge, die von den Gate-Schaltungen (2, 3, 4) zugeführt worden sind, die die Treibersignale (DUU, DUL, DVU, DVL, DWU, DWL) zu erzeugen;
    • einer FG-Schaltung (7) zum Erzeugen des Geschwindigkeitssignals (FG) aus jedem der Vergleichsausänge, die von den Gate-Schaltungen (2, 3, 4) zugeführt worden sind; und
    • einer Phasenschiebeschaltung (8) zum Erzeugen des Phasensignals (FGP) aus dem Geschwindigkeitssignal (FG), das relativ zum Geschwindigkeitssignal (FG) eine Phasenverschiebung um 30 Grad hat,
       wobei die Wählschaltung (9) die Wählsignale (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) in Übereinstimmung mit den Treibersignalsignalen (DUU, DUL, DVU, DVL, DWU, DWL) und dem Phasensignal (FGP) zurück zu den Gate-Schaltungen (2, 3, 4) leitet, und

       wobei die Stromversorgungsmittel (6) den bürstenlosen Dreiphasenmotor (10) in Übereinstimmung mit den Treibersignalsignalen (DUU, DUL, DVU, DVL, DWU, DWL) und dem Phasensignal (FGP) mit den Treiberströmen (IOU, IOV, IOW) speisen.
  3. Treibervorrichtung (11) für bürstenlosen Dreiphasenmotor nach Anspruch 2,

       wobei die von den Gate-Schaltungen (2, 3, 4) zugeführten Vergleichsausgänge in dem vorbestimmten Pegel individuell von einem hohen Pegel auf einen niedrigen Pegel oder von einem niedrigen Pegel auf einen hohen Pegel schalten.
  4. Treibervorrichtung (11) für einen bürstenlosen Dreiphasenmotor nach Anspruch 2 oder 3, wobei die Treibervorrichtung als eine integrierte Schaltung ausgebildet ist.
Anspruch[en]
  1. A three-phase brushless motor driving device (11) for supplying a three-phase brushless motor (10) with three-phase drive currents (IOU, IOV, IOW) that differ in phase by 120 degrees from one another,

       wherein passage control means is provided that compares back electromotive forces (VU, VV, VW) appearing in three coils (10A, 10B, 10C) provided one for each phase (U, V, W) in the three-phase brushless motor (10) individually with a common-terminal voltage (VN) of the three coils (10A, 10B, 10C) and includes a selector circuit (9) and gate circuits (2, 3, 4),

       the selector circuit (9), based on drive signals (DUU, DUL, DVU, DVL, DWU, DWL) for turning on and off the three-phase drive currents (IOU, IOV, IOW) and a phase signal (FGP) produced from a speed signal (FG) by performing phase shift, generates, for each of the three phases (U, V, W), two select signals (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) both of which are kept at a high level simultaneously during a predetermined period including a zero-cross point of each back electromotive force (Vu, Vv, Vw) on both rising and trailing edges thereof and any one of which is kept at a high level while another is kept at a low level outside the predetermined period that corresponds to a half cycle of the phase signal (FGP),

       the gate circuits (2, 3, 4) mask the comparison outputs individually in such a way that each of the comparison outputs is, in the predetermined period including a level-shift point thereof, permitted to pass through the gate circuit (2, 3,4) intact when the gate circuit (2,3, 4) receives two select signals (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) that are high from the selector circuit (9) and is, in a period between one such predetermined period and a next such predetermined period, kept at a level at which it is set after the level-shift point when the gate circuit (2, 3, 4) receives two select signals (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) of which one is at a high level and another is at a low level from the selector circuit (9), and

       wherein the drive currents (IOU, IOV, IOW) are produced by current supply means (6) in accordance with signals resulting from passage control.
  2. The three-phase brushless motor driving device (11) as claimed in claim 1, further comprising:
    • a drive waveform synthesizing circuit (5) for synthesizing together each of the comparison outputs fed from the gate circuits (2, 3, 4) to produce the drive signals (DUU, DUL, DVU, DVL, DWU, DWL);
    • an FG circuit (7) for producing the speed signal (FG) from each of the comparison outputs fed from the gate circuits (2, 3, 4); and
    • a phase shifting circuit (8) for producing from the speed signal (FG) the phase signal (FGP) having a phase shifted by 30 degrees relative to the speed signal (FG),
       wherein the selector circuit (9) feeds the select signals (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) back to the gate circuits (2, 3, 4) in accordance with the drive signals signals (DUU, DUL, DVU, DVL, DWU, DWL) and the phase signal (FGP), and

       wherein the current supply means (6) supplies the drive currents (IOU, IOV, IOW) to the three-phase brushless motor (10) in accordance with the drive signals signals (DUU, DUL, DVU, DVL, DWU, DWL) and the phase signal (FGP).
  3. The three-phase brushless motor driving device (11) as claimed in claim 2,

       wherein the comparison outputs fed from the gate circuits (2, 3, 4) turn from a high level to a low level or from a low level to a high level individually in the predetermined level.
  4. The three-phase brushless motor driving device (11) as claimed in claim 2 or 3,

       wherein the driving device is formed as an integrated circuit.
Anspruch[fr]
  1. Dispositif d'actionnement de moteur sans balais triphasé (11) pour délivrer à un moteur sans balais triphasé (10) des courants d'actionnement triphasés (IOU, IOV, IOW) dont la phase diffère de 120 degrés les uns par rapport aux autres,

       dans lequel des moyens de commande de passage sont présents, ceux-ci comparant les forces contre-électromotrices (VU, VV, VW) apparaissant dans trois enroulements (10A, 10B, 10C) disposés chacun pour chaque phase (U, V, W) dans le moteur sans balai triphasé (10) de façon individuelle à une tension de borne commune (VN) des trois enroulements (10A, 10B, 10C), et comprenant un circuit de sélecteur (9) et des circuits de porte (2, 3, 4),

       le circuit de sélecteur (9), en fonction de signaux d'actionnement (DUU, DUL, DVU, DVL, DWU, DWL) pour établir et interrompre les courants d'actionnement triphasés (IOU, IOV, IOW) et d'un signal de phase (FGP) produit à partir d'un signal de vitesse (FG) en effectuant un déphasage, génère, pour chacune des trois phases (U, V, W), deux signaux de sélection (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2), tous deux étant maintenus à un niveau haut simultanément durant une période prédéterminée comprenant un point de passage au zéro de chaque force contre-électromotrice (Vu, Vv, Vw) aussi bien sur les fronts montant que descendant de celle-ci, et chacun d'entre eux étant maintenu à un niveau haut tandis qu'un autre est maintenu à un niveau bas à l'extérieur de la période prédéterminée qui correspond à un demi-cycle du signal de phase (FGP),

       les circuits de porte (2, 3, 4) masquant les sorties de comparaison individuellement de telle sorte qu'il soit permis à chacune des sorties de comparaison, dans la période prédéterminée comprenant un point de décalage de niveau de celle-ci, de passer à travers le circuit de porte (2, 3, 4) intacte lorsque le circuit de porte (2, 3, 4) reçoit deux signaux de sélection (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) qui sont hauts à partir du circuit de sélecteur (9), et que celle-ci soit, dans une période entre cette période prédéterminée et une telle période prédéterminée suivante, maintenue à un niveau auquel elle est établie après le point de décalage de niveau lorsque le circuit de porte (2, 3, 4) a reçu deux signaux de sélection (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) dont l'un est à un niveau haut et l'autre est à un niveau bas depuis le circuit de sélecteur (9), et

       dans lequel les courants d'actionnement (IOU, IOV, IOW) sont produits par des moyens de délivrance de courant (6) en fonction de signaux résultant de la commande de passage.
  2. Dispositif d'actionnement de moteur sans balais triphasé (11) selon la revendication 1, comprenant de plus :
    • un circuit de synthèse de forme d'onde d'actionnement (5) pour synthétiser ensemble chacune des sorties de comparaison délivrées à partir des circuits de porte (2, 3, 4) de façon à produire les signaux d'actionnement (DUU, DUL, DVU, DVL, DWU, DWL) ;
    • un circuit FG (7) pour produire le signal de vitesse (FG) à partir de chacune des sorties de comparaison délivrées à partir des circuits de porte (2, 3, 4) ; et
    • un circuit de déphasage (8) pour produire à partir du signal de vitesse (FG) le signal de phase (FGP) ayant une phase déphasée de 30 degrés par rapport au signal de vitesse (FG),
       dans lequel le circuit de sélecteur (9) redélivre les signaux de sélection (FBU1, FBU2, FBV1, FBV2, FBW1, FBW2) aux circuits de porte (2, 3, 4) en fonction des signaux d'actionnement (DUU, DUL, DVU, DVL, DWU, DWL) et du signal de phase (FGP), et

       dans lequel les moyens de délivrance de courant (6) délivrent les courant d'actionnement (IOU, IOV, IOW) au moteur sans balais triphasé (10) en fonction des signaux d'actionnement (DUU, DUL, DVU, DVL, DWU, DWL) et du signal de phase (FGP).
  3. Dispositif d'actionnement de moteur sans balais triphasé (11) selon la revendication 2,

       dans lequel les sorties de comparaison délivrées à partir des circuits de porte (2, 3, 4) passent d'un niveau haut à niveau bas ou d'un niveau bas à un niveau haut individuellement dans le niveau prédéterminé.
  4. Dispositif d'actionnement de moteur sans balais triphasé (11) selon la revendication 2 ou 3,

       dans lequel le dispositif d'actionnement est formé sous la forme d'un circuit intégré.






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