The present invention relates to a device for reading nonvolatile
memory cells, in particular analog flash memory cells.
As known, in nonvolatile, floating gate memory cells, writing
modifies the quantity of electric charges stored in the floating gate region of
each cell, for programming the cell threshold voltage according to analog or digital
values to be stored.
Analog nonvolatile memory cells are read now through a
reading device formed by an analog/digital (A/D) converter; in detail, the A/D converter
comprises a plurality of comparator circuits, receiving at a first input a voltage
correlated to the value of the current flowing in the read memory cell, and thus
to the value of the cell threshold voltage, and at a second input different predetermined
reference values. The comparator circuits then generate at the output respective
digital signals, each of which has a high or low logic state indicative of the outcome
of the comparison. The comparator circuit output signals are then supplied to a
decoding circuit that, according to the logic state of the output signals of the
comparator circuits, generates at the output a binary word associated with the threshold
voltage of the read memory cell.
It is also known that during programming, the memory cell
is verified to ensure that the required datum is stored. Verifying of a memory cell
must be carried out with much greater accuracy than during normal reading of the
cell, to ensure long term legibility of the cell and correctness of the datum.
Thus, during program and verify, it is typically necessary
to generate binary words correlated to the threshold voltage of the read memory
cells and have a bit number larger than that required during normal reading operations.
Consequently, the circuit architecture of reading devices of the above-described
type, comprising 2n-1 comparator circuits for binary words of n bits,
makes it difficult to use a single reading device both for verify and memory cell
US 4,973,974 discloses a multi-stage analog-to-digital
converting device, wherein an analog input is digitized by a first parallel type
A/D converter, and is also temporarily stored in an analog data holding section,
constituted by, for example, a sample and hold circuit or an analog delay line.
Then, the output of the first A/D converter is converted by a D/A converter, and
the original analog input values stored in the analog data holding section are supplied
to an adder amplifier constituted by, for example, an operation amplifier. The adder
amplifier properly amplifies the difference between these two received analog values,
thereby providing an analog value corresponding to the difference between the original
analog input value and the output of A/D converter of the first stage. The analog
value corresponding to the difference is then digitized by a second parallel type
A/D converter of the next stage. An adder adds, and synthesizes, the output of the
first A/D converter as the higher bits and the output of the second A/D converter
as the lower bits, so as to produce a digital output value with a high resolution,
and sends it out to an external unit.
US 5,105,194 discloses a high speed, high resolution, time-shift
two-step analog-to-digital conversion (ADC) employing only one ADC module for both
coarse and fine signal conversions. The same ADC module is used first for the coarse
signal conversion with its output signal stored until the ADC completes the slower
fine signal conversion to generate the conversion error for the subsequent compensation
process. A digital signal is then generated after the two signals are processed
by using a digital signal processing to compensate for conversion error.
US 5,745,409 discloses a non-volatile memory including
digital and analog read and write circuits and dual I/O interfaces which allow input
and output signals in digital or analog form. On-chip analog-to-digital and digital-to-analog
converters allow conversion of signals from one format into another.
The object of the present invention is thus to provide
a device for reading nonvolatile memory cells, which can be used equally well both
in verify and in reading operations.
According to the present invention, a reading device for
nonvolatile memory cells is provided, as defined in claim 1.
For the understanding of the present invention, a preferred
embodiment is now described, purely by way of nonlimiting example, with reference
to the sole attached figure, which shows the simplified circuit diagram of a reading
device according to the present invention.
In the attached figure, 1 indicates as a whole a reading
device of a memory cell 2.
In particular, memory cell 2 has a gate terminal 3 receiving
a reading voltage VPCX, a source terminal 4 connected to ground, and a drain terminal
5 connected to the input of the reading device 1. The purpose of the reading device
1 is to provide at the output a binary output word WT of n+m bits, correlated to
the threshold voltage VTH of memory cell 2, wherein n and m have the meaning apparent
Reading device 1 comprises a detection or "sense amplifier"
circuit 6, a sample and hold circuit, hereinafter indicated as S/H circuit 7, and
an A/D (analog/digital) converter 8, of n+m bits.
Sense amplifier circuit 6 has an input connected to the
drain terminal 5 of the memory cell 2, and an output supplying an input voltage
VIN, the amplitude of which is correlated to the value of the current flowing in
memory cell 2 during reading and thus correlated to the threshold voltage VTH of
memory cell 2. Sense amplifier circuit 6 is of a known type, and is for example
described in patent application EP-A-833348 in the name of the applicant.
S/H circuit 7, of known type, has an input connected to
the output of sense amplifier circuit 6, supplying input voltage VIN, and an output
supplying a first voltage signal V1 of constant value, equivalent to the value of
the input voltage VIN at the sampling instant.
A/D converter 8 has an input connected to S/H circuit 7
supplying the first signal V1, and an output supplying the binary output word WT.
A/D converter 8 is of the double conversion stage type,
to carry out a first, approximate conversion determining n bits of the binary output
word WT, and typically the most significant n bits, and a second, more accurate
conversion, determining the remaining m bits of the binary output word, typically
the least significant m bits.
In particular, A/D converter 8 comprises a first A/D conversion
stage 10 of n bits; a D/A conversion stage 12 of n bits; a differentiator stage
14; a second A/D conversion stage 16 of m bits; a storage stage 18; and an adder
The first A/D conversion stage 10, which carries out the
approximate conversion, has an input connected to the output of S/H circuit 7 and
receiving therefrom the first signal V1, and an output supplying a first intermediate
binary word W1 of n bits. D/A conversion stage 12 has an input connected to the
output of the first A/D conversion stage 10 and receiving therefrom the first intermediate
binary word W1, and an output supplying a second voltage signal V2. The differentiator
stage 14 has a first input connected to the output of S/H circuit 7 and receiving
therefrom the first signal V1, a second input connected to the output of D/A conversion
stage 12 and receiving therefrom the second signal V2, and an output supplying a
difference signal VD, correlated to the difference between the first and the second
signal V1, V2.
The second A/D conversion stage 16, which carries out the
accurate conversion, has an input connected to the output of the differentiator
stage 14 and receiving therefrom the difference signal VD, and an output supplying
a second intermediate binary word W2 of m bits. The storage stage 18 (formed by
a latch) has an input connected to the output of the first A/D conversion stage
10, and an output connected to a first input of the adder stage 20 receiving therefrom
the first intermediate binary word W1. The adder stage 20 also has a second input
connected to the output of the second A/D conversion stage 16 and receiving therefrom
the second intermediate binary word W2, and an output supplying the binary output
word WT of n+m bits, equivalent to the sum of the first and the second intermediate
binary words W1, W2.
D/A conversion stage 12, second A/D conversion stage 16,
and differentiator stage 14 also have a further input, receiving, for example from
a control stage not shown, an enabling/disabling ON/OFF signal, to command switching
on and off these stages.
In particular, during reading of memory cell 2, the enabling/disabling
ON/OFF signal has a first logic value such as to control switching off D/A conversion
stage 12, second A/D conversion stage 16, and differentiator stage 14. Consequently,
the reading device 1 acts as an analog/digital converter of n bits, and thus supplies
the binary output word WT of n+m bits, wherein n bits, for example the most significant
ones, are correlated to the threshold voltage of memory cell 2, whereas the remaining
m bits, in the present example the least significant bits, are not considered.
On the other hand, during verifying, enabling/disabling
ON/OFF signal has a second logic level such as to control switching on of stages
12, 14, 16; consequently, reading device 1 acts as an analog/digital converter of
n+m bits, and supplies the binary output word WT of n+m bits, indicative of the
threshold voltage of memory cell 2, with greater accuracy than that obtained during
normal reading operations.
Conveniently, the condition m=n may be applied, and thus
during verify, reading has twice the accuracy than during normal reading operations.
The operation of reading device 1 is now described briefly
with reference only to when stages 12, 14 and 16 are switched on, since where these
stages are switched off, operation of reading device 1 is reduced to that of a common
analog/digital converter of n bits.
When all stages 6-20 of reading device 1 are switched on,
reading device 1 carries out a first conversion of n bits of the first signal V1
(quantization of first signal V1 with respect to 2" intervals), and a second conversion
of m bits of difference signal VD, which is the difference between first signal
V1 and second signal V2, which has a value indicative of the quantization of first
signal V1, carried out in the first conversion.
Difference signal VD thus represents the difference between
the analog value of the first signal V1 and the quantized value of the same first
signal V1, and thus allows the second intermediate binary word W2 to be obtained,
which, when combined with the first intermediate binary word W1, supplies the output
word WT, of n+m bits.
The advantages of the present reading device are the following.
Firstly, use of an analog/digital converter of n+m bits
and double conversion stage, makes it possible to define a circuit architecture
allowing both use of a single reading device 1 for the operations of reading and
verify, and optimisation of the device for the specific application.
Indeed, during the program verify, memory cell 2 is read
using both the A/D conversion stages 10, 16, thus obtaining an output word of n+m
bits, and high reading accuracy, whereas during stored data reading, only the first
A/D conversion stage 10 is used, thus providing an output word of n bits. Therefore,
even if stored data reading is less accurate than program verify, nevertheless firstly
its accuracy is fully sufficient for these reading operations, and secondly energy
is saved by switching off some stages (D/A conversion stage 12, second A/D conversion
stage 16, and differentiator stage 14).
Finally, it is apparent that modifications and variants
can be made to the reading device described and illustrated here, without departing
from the scope of the present invention, as defined in the appended claims. For
example, reading device 1 can also comprise k analog/digital converter stages, wherein
k>2, thus providing respective intermediate binary words of any length. Use of
a plurality of converter stages in cascade, combined with the possibility of generating
binary output words WT of any length, provides for a reading device having high