PatentDe  


Dokumentenidentifikation EP1398796 24.05.2006
EP-Veröffentlichungsnummer 0001398796
Titel Unterschiedlichen Operationen eines Flash-Speichers zugeordnete Redundanzschaltungen und zugehörige Betriebsverfahren
Anmelder Samsung Electronics Co., Ltd., Suwon, Kyonggi, KR
Erfinder Im, Jae Woo, Yongin-shi, Gyeonggi-do, KR;
Lim, Samsung Suji 5 cha Apt., Young Ho;
512-1201, Gyeonggi-do, KR
Vertreter Patentanwälte Ruff, Wilhelm, Beier, Dauster & Partner, 70174 Stuttgart
DE-Aktenzeichen 60304642
Vertragsstaaten DE, FR, GB
Sprache des Dokument EN
EP-Anmeldetag 06.09.2003
EP-Aktenzeichen 030202352
EP-Offenlegungsdatum 17.03.2004
EP date of grant 19.04.2006
Veröffentlichungstag im Patentblatt 24.05.2006
IPC-Hauptklasse G11C 29/00(2000.01)A, F, I, 20051007, B, H, EP

Beschreibung[en]

The invention relates to a flash memory according to the preamble of claim 1 and a method of operating the same.

Flash EPROM devices, sometimes referred to as flash memory devices, typically include at least one memory array organized into rows and columns of flash memory cells. The array is typically partitioned into blocks, each of which is further divided into sectors. A row decoder and a column decoder are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers are coupled to column lines corresponding to the columns of memory cells to amplify the voltage levels on the addressed column lines corresponding to the data values stored in the addressed flash memory cells. The particular implementations of known arrays and row/column decoders will not be discussed further herein.

It is known for memory devices to have defects which can prevent the device from operating as designed. In particular, defects can occur during the manufacture of flash memory devices so that memory cells within the array do not operate properly. For example a defect in a memory cell (or associated circuitry) can cause data written to the memory cell to be stored incorrectly or not at all. Furthermore, the defect may prevent the data from being reliably read from the addressed memory cell. Any of these types of defects can reduce the manufacturing yield for the flash memory device.

It is known to include redundant memory cells in the flash memory, which can selectively replace normal memory cells that are determined to be defective to improve the manufacturing yield of the flash memory. Some flash memory devices utilize non-volatile registers to store addresses of memory cells that are known to be defective. The addresses associated with the defective memory cells can be stored in the registers and compared to addresses associated with memory operations (i.e., read operations and write operations). If the address matches an address stored in the register, a redundant circuit can re-route (or map) the data to or from the memory so that the defective memory cells are not used for the memory operation. For example, during a write operation, write data (which would otherwise be directed to a known defective memory cell) can be re-routed to a redundant memory cell. Later, when a read operation is directed to the address of the known defective memory cell, the redundant memory cell, as well as the known defective memory cells, is accessed. The data retrieved from the redundant memory cell is re-routed to replace the data that was read from the known defective memory cell to provide the data that was previously written to the accessed address.

Figure 1 illustrates a conventional multi-bank flash memory device 100. In particular, the conventional multi-bank flash memory device includes two banks: BANK0 101 and BANK1 102. Each of the banks has an associated row and column decoder that selects a set of memory cells in the respective bank to be accessed based on an address provided to the respective row/column decoder. BANK0 101 has an associated row decoder 111 and a column decoder 121 that receive respective addresses via address lines ABANK0. Similarly, BANK1 102 has an associated row decoder 112 and a column decoder 122 which select memory cells within the BANK1 102 to be accessed based on addresses provided via address lines ABANK1.

Each of the respective banks also includes redundant memory cells that can be accessed with the normal memory cells associated therewith. Accordingly, when data is written normal memory cells (or read from normal memory cells), data is also written to (or read from) the redundant memory cells selected by the respective row/column decoders.

The addresses are provided to the respective banks by address buffers 171 and 172. In particular, address buffer 171 provides the addresses for the row/column decoders 111, 121 associated with BANK0 101 whereas address buffer 172 provides the addresses for the row/column decoders 112, 122 associated with BANK1 102. Accordingly, different addresses can be provided to the different banks.

Data can be provided to/from the respective banks to a respective combination of sense amplifiers and write drivers dedicated to each of the banks. In particular, data to be written to BANK0 101 is provided by a write driver 151 via data lines BANKODL whereas data to be written to BANK1 102 is provided by a write driver 152 via data lines BANK1DL Data read from BANK0 101 is provided to a sense amplifier 141 via data lines BANKODL (i.e., the same lines used to provide write data to the BANK0 101). Data read from BANK1 102 is provided to a sense amplifier 142 via data lines BANK1DL (i.e., the same lines used to provide write data to BANK1 102). The data written to (or read from) either of the banks flows to/from the memory device via a data input/output buffer 160.

Each of the banks has an associated redundancy circuit. In particular, BANK0 101 has an associated redundancy circuit 131 whereas the BANK1 102 has an associated redundancy circuit 132. The redundancy circuits 131, 132 provide redundancy entries which identify memory cells within the respective bank that are known to be defective. In particular, the redundancy circuit 131 can include up to 4 entries each of which can identify an address within BANK0 101 which is known to include a defective memory cell. Similarly, the redundancy circuit 132 can include up to 4 entries each of which can identify a known defective memory cell within BANK1 102. As briefly discussed above, the entries in the redundancy circuits 131, 132 can be used to avoid known defective memory cells.

Figure 2, illustrates a general write operation carried out in BANK0 101. In particular, an address for the write operation is provided to BANK0 101 so that the normal and redundant cells associated with the address within the bank can be accessed. The address is also provided to the redundancy circuit 131. The redundancy circuit 131 compares the address used for the write operation with the addresses of known defective memory cells in the BANK0 101. If the address for the write operation matches an address of a known defective memory cell within the bank, the redundancy circuit 131 provides information associated with the matching address that can be used to write some of the data to a redundant memory cell rather than to a known defective memory cell.

The redundancy circuit 131 provides BANK0 REPAIR INFORMATION to a multiplexer 153 included within the data input/output buffer 160 shown in Figure 1. The multiplexer 153 "maps" the data bit within the data word DATA that would otherwise be written to the known defective memory cell to a redundant data line coupled to the redundant memory cell associated with the address in BANK0 101 to be written. Accordingly, the conventional system shown in Figure 1 can avoid writing data to known defective memory cells by, instead, storing data in redundant cells associated with the same address.

Figure 3 generally illustrates a read operation directed to BANK0 101 shown in Figure 1. The address for the read operation is provided to both the normal cells and the redundant cells in BANK0 101 so that data can be retrieved from both the normal cells and the redundant cells. In particular, NORMAL DATA BITS are retrieved from the normal memory cells whereas the REDUNDANT DATA BIT is retrieved from the redundant memory cell having the same address as the normal memory cells that are accessed. The NORMAL DATA BITS and the REDUNDANT DATA BIT are provided to the sense amplifier 141.

In addition to providing the address for the read operation to the normal and redundant cells of BANK0 101, the address is also provided to the redundancy circuit 131 that includes the entries identifying the known defective memory cells in the BANK0 101. The redundancy circuit 131 compares the address provided to the BANK0 101 with the addresses associated with the known defective memory cells in BANK0 101. If the address for the read operation matches any of the addresses of known defective memory cells in BANK0 101, BANK0 REPAIR INFORMATION is provided to a multiplexer included in the sense amplifier 141. The BANK0 REPAIR INFORMATION provided by the redundancy circuit 131 identifies which bit included in the DATA retrieved from the normal cells of BANK0 101 is known to be defective. Accordingly, the multiplexer maps the bit retrieved from the redundant cell in BANK0 101 to replace the bit of the DATA retrieved from the normal memory cells which is known to be defective. The multiplexer provides the "repaired" DATA as output.

Figure 4 illustrates a multi-bank flash memory device 200 that is similar to the structure shown in Figure 1, but includes 16 banks rather than 2 banks. The operation and structure of the multi-bank system shown in Figure 4 is similar to that described in reference to Figures 1-3. In particular, each of the banks 0 to 15 has an associated redundancy circuit each of which can include up to four entries. The entries within each of the redundancy circuits can identify a known defective memory cell within its corresponding bank. For example, redundancy circuit 231 includes up to four entries each of which can identify a known defective memory cell in the BANK0 associated with the redundancy circuit 231. Likewise, redundancy circuits 232, 233, 234 can each include up to four entries, each of which can identify a known defective memory cell in banks BANK1, BANK14, and BANK 15 respectively.

Redundant memory cells for flash memory devices and other memory devices are also discussed in the patent publications US 6,469,932, US 6,381,174, US 5,708,613, US 3,588,830, and US 4,473,895.

Patent publication US 5,847,998 discloses a flash memory according to the preamble of claim 1 and a method of operating such flash memory according to the preamble of claim 16.

It is the technical problem underlying the invention to provide a flash memory of the type mentioned at the beginning and a method of operating the same which are capable of further improving the prior art discussed above.

The invention solves this problem by providing a flash memory having the features of claim 1 and operation method having the features of claim 16. Advantageous embodiments of the invention are given in the dependent claims.

The invention provides a flash memory including a first redundancy circuit configured to provide read repair information for read operations to the flash memory. The flash memory also includes a second redundancy circuit, separate from the first redundancy circuit, configured to provide write repair information for write operations to the flash memory.

According to the invention, the flash memory device can include a dedicated-read operation redundancy circuit configured to provide read repair information and a dedicated-write operation redundancy circuit configured to provide write repair information. According to the invention, the flash memory device can also include a first redundancy circuit configured to store an address of a defective memory cell in the flash memory and a second redundancy circuit, separate from the first redundancy circuit, configured to store the address of the defective memory cell.

  • Figure 1 is a block diagram illustrating a conventional multi-bank flash memory device.
  • Figure 2 is a block diagram illustrating a write operation for the conventional multi-bank flash memory device shown in Figure 1.
  • Figure 3 is a block diagram illustrating a read operation for the conventional multi-bank flash memory device shown in Figure 1.
  • Figure 4 is a block diagram illustrating a conventional multi-bank flash memory device.
  • Figure 5 is a hierarchical drawing illustrating a relationship between the block diagrams shown in Figures 6A-6B according to embodiments of the invention.
  • Figure 6A-6B are block diagrams illustrating embodiments of multi-bank flash memory devices according to the present invention.
  • Figure 7 is a block diagram illustrating write operations for embodiments of multi-bank flash memory devices according to the present invention.
  • Figure 8 is a block diagram illustrating read operations for embodiments of multi-bank flash memory devices according to the present invention.

According to the embodiments of the invention, separate redundancy circuits can provide repair information for different memory operations. In particular, one redundancy circuit can provide repair information for write operations (i.e., a write redundancy circuit) whereas another redundancy circuit can provide repair information for read operations (i.e., a read redundancy circuit). Furthermore, each of the dedicated redundancy circuits can provide the appropriate repair information for memory operations to any of the banks of the flash memory. For example, the write redundancy circuit can provide write repair information for write operations to any of the banks of the flash memory whereas the read redundancy circuit can provide the read repair information for read operations to any of the banks.

Accordingly, different entries in one of the redundancy circuits can identify known defective memory cells across multiple banks of the flash memory, thereby avoiding the need to have a redundancy circuit dedicated to each of the banks of the multi-bank flash memory. Because a single redundancy circuit can provide repair information for any of the banks during a particular type of memory operation, the redundancy circuitry can be more efficiently utilized to provide redundancy for the multi-bank flash memory. For example, in some embodiments according to the invention, all of the known defective memory cells may be in a single one of the banks whereas in another embodiment according to the invention, the defective memory cells could be located in different banks of the multi-bank flash memory device. In both of these embodiments, a single redundancy circuit can provide the repair information (for a type of memory operation) thereby reducing the need for a dedicated redundancy circuit for each of the banks as done in conventional systems.

Figure 5 is a hierarchical diagram showing the relationship between the block diagrams shown in Figures 6A-6B. In particular, Figures 6A-6B illustrate embodiments of multi-bank flash memory devices according to the present invention connected via signals, such as address lines, data lines, read/write repair lines, and the like.

It will be understood that although Figures 6A and 6B illustrate embodiments of multi-bank flash memory devices including 16 banks of memory (banks 0-15), the invention may be practiced utilizing fewer or more banks of flash memory. Moreover, although Figures 6A-6B show specific a numbering scheme of, for example, the address and data lines provided to the circuits and elements illustrated (such as AR<21:0> and READ DL<16:0), it will be understood that the numbering scheme is illustrative of the invention and may be practiced in other embodiments using fewer or more of the signal lines shown in the figures, such as in embodiments where fewer or more banks of memory are used.

Figures 6A-6B are block diagrams that illustrate embodiments of multi-bank flash memory devices having dedicated read and write redundancy circuits according to the invention. In general, each of the banks of the flash memory device BANK0 601 to BANK15 604 include memory cells and associated redundant memory cells which can be accessed by providing address information to the respective row and column decoders coupled to each of the banks. For example, the normal and redundant memory cells included in BANK0 601 can be accessed by providing appropriate addressing to either the read column decoder 631 and the read row decoder 611 (for a memory read operation) or to the write column decoder 641 and the write row decoder 621 (during a memory write operation). The other banks of the flash memory device can be similarly accessed using the respective read row/column decoders or write row/column decoders associated with each of the banks.

In some embodiments as shown in Figure 6A, the address for the memory operation is provided via a read address buffer 690 or a write address buffer 600 depending on the type of operation to be performed. In the case of a read operation, the read address buffer 690 provides the address to dedicated address lines used for read operations (AR<21:0>) which are provided to the read column and row decoders in each of the banks of the flash memory and to a read redundancy circuit 651. In some embodiments according to the invention, some of the read address is provided to a read bank selector 610 that decodes which of the banks in the multi-bank flash memory device is to be accessed during the current read operation.

The read redundancy circuit 651 is a separate redundancy circuit that is dedicated to providing read repair information READ IO REPAIR <15:0> only during read operations in the memory. The read repair information can be provided by the read redundancy circuit 451 for read operations directed to any of the banks in the multi-bank flash memory device. The read redundancy circuit 451 includes a plurality of entries each of which stores an address of a known defective memory cell in any of the banks of the flash memory device. The entry also includes the read repair information READ IO REPAIR <15:0> that identifies which of the data bits accessed by the read address is known to be defective. In particular, as shown in Figure 6A, a read operation retrieves 17 data bits (i.e.,. READ DL <16:0>) from the addressed bank where 16 of the data bits are provided by normal memory cells and I of the data bits is provided by the redundant memory cell which is associated with the normal memory cells accessed.

The read repair information READ IO REPAIR <15:0> provided by the read redundancy circuit 651 can identify which of the 16 data bits provided by the accessed normal memory cells corresponds to the known defective memory cell. The read repair information READ IO REPAIR <15:0> can, therefore, be used by a sense amplifier circuit 660 to replace the data bit provided by the known defective memory cell with the data provided by the redundant memory cell. The 16 bit data word provided by the sense amplifier circuit 660 (i.e. including the data bit from the redundant memory cell) can be output from the memory device through a data input/output buffer 680.

As shown in Figures 6A-6B, the address is provided to write address lines AW <21:0> via a write address buffer 400. In some embodiments according to the invention, selected ones of the address lines such as AW <21:18>, are provided to a write bank selector 420 that generates an active write bank select signal to the bank that is to be written on WRITE BANK SEL <15:0>. In particular, the write bank select signal coupled to the bank that includes the memory cells identified by the write address AW <21:0> becomes active for the write operation whereas each of the other respective write bank select signals remains inactive. A write controller 630 provides a write control signal to a bank busy generator 640. The bank busy generator 640 provides an active BANKBUSY signal to the bank that includes the memory cells identified by the address for the write operation via the BANKBUSY <15:0> lines whereas the BANKBUSY signals to the other banks remain inactive.

The write addresses AW <21:0> are also provided to a write redundancy circuit 652 that includes a plurality of entries each indicating an address of a known defective memory cell in the memory device. Each of the plurality of entries in the write redundancy circuit 652 includes associated write repair information that identifies which of the data bits associated with the respective address of the known defective memory cells is defective. The write redundancy circuit 652 provides the write repair information for write operations in any of the banks of the flash memory device.

The write redundancy circuit 652 provides the write repair information only for write operations and not for read operations. The write repair information is provided to a write driver circuit 670 so that data provided by the data input/output buffer circuit 680 can be mapped to avoid use of the known defective memory cell identified by the entry in the write redundancy circuit 652. In particular, the write driver 670 can re-route a data bit provided by the data input/output buffer 680, which would otherwise be written to the known defective memory cell, to be written to redundant memory cell associated with the write address AW <21:0>.

Figure 7 is a block diagram that illustrates exemplary write operations to BANK0 601 according to embodiments of the present invention. According to Figure 7, the write address AW <21:0> is provided to the write address buffer 600. The write address buffer 600 provides the write address AW <21:0> to the write row decoder 621 and to the write column decoder 641 associated BANK0601 of the flash memory device. The write address AW <21:0> is also used by the write bank selector 620 to generate a write bank select signal WRITE BANK SEL <0> that indicates that BANK0 601 in the flash memory device is to be written based on the write address AW <21:0>.

The write address AW <21:0> is also provided to the write redundancy circuit 652. The write redundancy circuit 652 compares the write address AW <21:0> to each of the plurality of entries included therein. Each of the entries in the write redundancy circuit 652 includes an address of a known defective memory cell in the flash memory device and associated write repair information that indicates which of the memory cells to be accessed for the write operation is known to be defective. For example, the write repair information can be a mask including a bit for each of the bits in the data word to be written to flash memory during the write operation. The write repair information can indicate which of the data bits in the data word would otherwise be written to the defective memory cell associated with the write address by, for example, being a logic "high" level whereas the remaining bits in the write repair information are a logic "low" level.

If the write address AW<21:0> matches any of the entries included in the write redundancy circuit 652, the associated write repair information WRITE REPAIR INFORMATION <15:0> is provided to the write driver 670. The write driver 670 reroutes the data bit identified by the WRITE REPAIR INFORMATION <15:0> to write data line that is coupled to the redundant memory cell, such as WRITE DL <16> to avoid writing the identified data bit to the known defective memory cell. The write driver 670 can, therefore, reroute the appropriate data bit included in DATA <15:0> so that it is written to the redundant memory cell associated with the write address AW <21:0> rather than the defective memory cell.

Figure 8 is a block diagram that illustrates exemplary read operations to BANK0 601 according to embodiments of the present invention. As shown in Figure 8, a read address AR <21:0> is provided to the read address buffer 690 which outputs the read address AR <21:18> to the read bank selector 610 which generates a read bank select signal to the read row and column decoder 611 and 631, respectively.

The read address AR <21:0> is also provided to the read redundancycircuit 651 which includes a plurality of entries that store addresses of known defective memory cells and associated read repair information that can be used to reroute data read from the redundant memory cell to a data line that would otherwise provide data from the known defective memory cell. In particular, the read repair information READ REPAIR INFORMATION <15:0> is provided to the sense amplifier 660 via READ REPAIR LINES <15:0>. The READ REPAIR INFORMATION <15:0> can be, for example, a 16 bit word that identifies which of the bit positions of the data read from the memory corresponds to the known defective memory cell. The sense amplifier 660 can replace the data provided by the known defective memory cell with the data provided by the redundant memory cell.

Defective memory cells can be identified by testing each of the memory cells during manufacturing of the flash memory device. Upon determining which memory cells are defective, the write redundancy circuit 652 and the read redundancy circuit 651 can be programmed, using for example fuses to store the addresses of the memory cells determined to be defective and the repair information associated with each of the addresses. Accordingly, the addresses and repair information programmed into the separate read and write redundancy circuits 651, 652 are the same.

During a write operation to the flash memory device, the write repair information, stored in the write redundancy circuit 652, is used to write data to the redundant memory cell that is associated with the write address in the selected bank rather than the defective memory cell. When a read operation is performed to the same address, the read repair information stored in the read redundancy circuit 651 is used to replace the data provided by the known defective memory cell with the data that is retrieved from the redundant memory cell to which the data was written during the preceding write operation to the same address. Accordingly, the write redundancy circuit 652 is used during write operations whereas the read redundancy circuit 651 is used during read operations.

Accordingly, in some embodiments according to the present invention as discussed above, the write redundancy circuit 652 can be dedicated to providing write repair information for write operations in the flash memory device whereas the read redundancy circuit 651 is dedicated to providing read repair information for read operations in the flash memory device. Moreover, the read redundancy circuit 651 and the write redundancy circuit 652 can each include entries for any of the plurality of banks in the flash memory device. For example, the entries in the read redundancy circuit 651 and the write redundancy circuit 652 can indicate that a defective memory cell is present in any of the banks BANK0 601, BANK1 602.... BANK14 603. and BANK15 604, of the flash memory device. Accordingly, when a write operation is directed to any of the banks, the write redundancy circuit 652 provides the write repair information to avoid using the known defective memory cell. Likewise, the read redundancy circuit 651 provides the read repair information for read operations directed to any of the banks so that the data provided from the redundant memory cell replaces the data that is retrieved from the known defective memory cell.

As will be understood by those skilled in the art, a flash memory device according to the present invention can support what is referred to as Read-While-Write operation. In particular, a flash memory device according to the present invention can perform a read operation while a write operation is being performed in another bank of the flash memory. Furthermore, it will be understood by those skilled in the art, that a flash memory device according to the present invention can be a NOR or a NAND type flash memory device.

Many alterations and modifications may be made by those having ordinary skill in the an without departing from the spirit and scope of the invention. Therefore, it must be understood that the illustrated embodiments have been set forth only for the purposes of example, and that it should not be taken as limiting the invention as defined by the following claims.


Anspruch[de]
Flashspeicher, der für gleichzeitigen Lese- und Schreibbetrieb eingerichtet ist, so dass Lese- und Schreibvorgänge bezüglich unterschiedlicher Bänke des Speichers gleichzeitig ausführbar sind,

gekennzeichnet durch - eine erste Redundanzschaltung (651), die dafür ausgelegt ist, Lesereparaturinformationen für Lesevorgänge des Flashspeichers bereitzustellen und/oder eine Adresse einer defekten Speicherzelle im Flashspeicher zu speichern, und - eine zweite Redundanzschaltung (652), die von der ersten Redundanzschaltung getrennt ist und dafür ausgelegt ist, Schreibreparaturinformationen für Schreibvorgänge des Flashspeichers bereitzustellen und/oder die Adresse der defekten Speicherzelle zu speichern.
Flashspeicher nach Anspruch 1, wobei die Lesereparaturinformationen und die Schreibreparaturinformationen mit der gleichen Adresse einer defekten Speicherzelle in einer Bank des Flashspeichers verknüpft sind. Flashspeicher nach Anspruch 1 oder 2, wobei die erste Redundanzschaltung die Lesereparaturinformationen nicht für Schreibvorgänge in eine Bank des Flashspeichers bereitstellt und die zweite Redundanzschaltung die Schreibreparaturinformationen nicht für Lesevorgänge der Bank bereitstellt. Flashspeicher nach Anspruch 2 oder 3, wobei ein erster Eintrag in die erste Redundanzschaltung eine Adresse einer ersten defekten Speicherzelle in einer ersten Bank verknüpft mit den Lesereparaturinformationen beinhaltet und ein zweiter Eintrag in der ersten Redundanzschaltung eine Adresse einer zweiten defekten Speicherzelle in einer von der ersten Bank separaten, zweiten Bank des Flashspeichers beinhaltet. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei der Flashspeicher dafür ausgelegt ist, einen ersten Lese- oder Schreibvorgang in einem ersten Sektor einer Bank des Flashspeichers und gleichzeitig einen zweiten Lese- oder Schreibvorgang in einem zweiten Sektor einer anderen Bank des Flashspeichers auszuführen. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei die erste Redundanzschaltung zum Speichern von Adressen defekter Speicherzellen und zugehöriger Lesereparaturinformationen bestimmt ist, die für Lesevorgänge in irgendeiner von einer Mehrzahl von Bänken des Flashspeichers vorgesehen sind, und die zweite Redundanzschaltung zum Speichern der Adressen der defekten Speicherzellen und zugehöriger Schreibreparaturinformationen für Schreibvorgänge in irgendeine der Mehrzahl von Bänken des Flashspeichers bestimmt ist. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei der Flashspeicher einen solchen vom NOR- oder NAND-Typ beinhaltet. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei die Lesereparaturinformationen und die Schreibreparaturinformationen identische Informationen enthalten. Flashspeicher nach irgendeinem der vorherigen Ansprüche, weiter gekennzeichnet durch eine Mehrzahl von Bänken, wobei die erste Redundanzschaltung dafür eingerichtet ist, die Lesereparaturinformationen für den Lesevorgang irgendeiner der Mehrzahl von Bänken bereitzustellen, und die zweite Redundanzschaltung dafür eingerichtet ist, die Schreibreparaturinformationen für den Schreibvorgang irgendeiner der Mehrzahl von Bänken bereitzustellen. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei die erste Redundanzschaltung Lesereparaturinformationen für den Lesevorgang bereitstellt, die wenigstens eine defekte Bitposition an der zu lesenden Adresse bezeichnen, und die zweite Redundanzschaltung Schreibreparaturinformationen für den Schreibvorgang bereitstellt, die wenigstens eine defekte Bitposition an der zu schreibenden Adresse bezeichnen. Flashspeicher nach irgendeinem der vorherigen Ansprüche, weiter gekennzeichnet durch - eine Abtastverstärkerschaltung, die elektrisch mit der ersten Redundanzschaltung gekoppelt ist, wobei die Lesereparaturinformationen der Abtastverstärkerschaltung während des Lesevorgangs über Lesereparaturleitungen bereitgestellt werden, und - eine Schreibtreiberschaltung, die elektrisch mit der zweiten Redundanzschaltung gekoppelt ist, wobei die Schreibreparaturinformationen der Schreibtreiberschaltung während des Schreibvorgangs über von den Lesereparaturleitungen separate Schreibreparaturleitungen bereitgestellt werden. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei eine Leseadresse der ersten Redundanzschaltung über Leseadressleitungen während des Lesevorgangs zugeführt wird und eine Schreibadresse der zweiten Redundanzschaltung während des Schreibvorgangs über von den Leseadressleitungen separate Schreibadressleitungen zugeführt wird. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei auf die in der ersten Redundanzschaltung gespeicherte Adresse für einen Lesevorgang der defekten Speicherzelle im Speicher zugegriffen wird und auf diese beim Schreibvorgang in die defekte Speicherzelle nicht zugegriffen wird. Flashspeicher nach irgendeinem der vorherigen Ansprüche, wobei die erste Redundanzschaltung die in ihr gespeicherte Adresse der Speicherzelle nicht für einen Schreibvorgang zuführt und die zweite Redundanzschaltung die in ihr gespeicherte Adresse der Speicherzelle nicht für einen Lesevorgang zuführt. Flashspeicher nach Anspruch 14, wobei die Speicherzelle in einer ersten Bank des integrierten Schaltkreisspeichers enthalten ist, ein erster Eintrag in der ersten Redundanzschaltung eine Adresse einer ersten defekten Speicherzelle in der ersten Bank beinhaltet und ein zweiter Eintrag in der ersten Redundanzschaltung eine Adresse einer zweiten defekten Speicherzelle in einer von der ersten Bank separaten, zweiten Bank des Flashspeichers beinhaltet. Verfahren zum Betrieb eines Flashspeichers, der für gleichzeitigen Lese- und Schreibbetrieb eingerichtet ist, so dass Lese- und Schreiboperationen bezüglich unterschiedlicher Bänke des Speichers gleichzeitig ausführbar sind,

gekennzeichnet durch folgende Schritte: - Speichern von mit einer ersten defekten Speicherzelle verknüpften Lesereparaturinformationen in einer ersten Redundanzschaltung, - Speichern von mit einer zweiten defekten Speicherzelle verknüpften Schreibreparaturinformationen in einer von der ersten Redundanzschaltung separaten, zweiten Redundanzschaltung, - Bereitstellen der Lesereparaturinformationen durch die erste Redundanzschaltung für Lesevorgänge der Speicherzelle, um aus der ersten defekten Speicherzelle gelesene Daten zu reparieren, und - Bereitstellen der Schreibreparaturinformationen durch die zweite Redundanzschaltung für Schreibvorgänge in die Speicherzelle, um das Schreiben vom Daten in die zweite defekte Speicherzelle zu verhindern.
Verfahren nach Anspruch 16, wobei ein erster Lese- oder Schreibvorgang mit einem ersten Sektor einer Bank des Flashspeichers ausgeführt wird, während gleichzeitig ein zweiter Lese- oder Schreibvorgang mit einem zweiten Sektor einer anderen Bank des Flashspeichers ausgeführt wird. Verfahren nach Anspruch 16 oder 17, wobei die Lesereparaturinformationen durch die erste Redundanzschaltung nicht für den Schreibvorgang und die Schreibreparaturinformationen durch die zweite Redundanzschaltung nicht für den Lesevorgang bereitgestellt werden. Verfahren nach einem der Ansprüche 16 bis 18, wobei die Lesereparaturinformationen durch die erste Redundanzschaltung für den Lesevorgang irgendeiner von einer Mehrzahl von Bänken des Flashspeichers bereitgestellt werden und die Schreibreparaturinformationen durch die zweite Redundanzschaltung für den Schreibvorgang irgendeiner der Mehrzahl von Bänken bereitgestellt wird.
Anspruch[en]
A flash memory adapted for read-while-write operation so that read and write operations can simultaneously be performed with respect to different banks of the memory,

characterized by - a first redundancy circuit (651) configured to provide read repair information for read operations to the flash memory and/or to store an address of a defective memory cell in the flash memory; and - a second redundancy circuit (652), separate from the first redundancy circuit, configured to provide write repair information for write operations to the flash memory and/or to store the address of the defective memory cell.
A flash memory according to Claim 1, wherein the read repair information and the write repair information are associated with a same address of a defective memory cell in a bank of the flash memory. A flash memory according to Claim 1 or 2, wherein the first redundancy circuit does not provide the read repair information for write operations to a bank of the flash memory and the second redundancy circuit does not provide the write repair information for read operations to the bank. A flash memory according to Claim 2 or 3, wherein a first entry in the first redundancy circuit includes an address of a first defective memory cell in a first bank associated with the read repair information, and wherein a second entry in the first redundancy circuit includes an address of a second defective memory cell in a second bank of the flash memory that is separate from the first bank. A flash memory according to any of the preceding Claims, wherein the flash memory is configured to perform a first read or write operation in a first sector of a bank of the flash memory while simultaneously performing a second read or write operation in a second sector of another bank of the flash memory. A flash memory according to any of the preceding Claims, wherein the first redundancy circuit is dedicated to storing addresses of defective memory cells and associated read repair information provided for read operations in any of a plurality of banks of the flash memory, and wherein the second redundancy circuit is dedicated to storing the addresses of the defective memory cells and associated write repair information for write operations in any of the plurality of banks of the flash memory. A flash memory device according to any of the preceding Claims, wherein the flash memory comprises a NOR or NAND type flash memory. A flash memory according to any of the preceding Claims, wherein the read repair information and the write repair information comprise identical information. A flash memory according to any of the preceding Claims, further comprising a plurality of banks, wherein the first redundancy circuit is configured to provide the read repair information for the read operation to any of the plurality of banks, and wherein the second redundancy circuit is configured to provide the write repair information for the write operation to any of the plurality of banks. A flash memory according to any of the preceding Claims, wherein the first redundancy circuit provides read repair information for the read operation indicating at least one defective bit position at the address to be read, and

wherein the second redundancy circuit provides write repair information for the write operation indicating at least one defective bit position at the address to be written.
A flash memory according to any of the preceding Claims further comprising: a sense amplifier circuit electrically coupled to first redundancy circuit wherein the read repair information is provided to the sense amplifier circuit during the read operation via read repair lines; and a write driver circuit electrically coupled to the second redundancy circuit wherein the write repair information is provided to the write driver circuit during the write operation via write repair lines that are separate from the read repair lines. A flash memory according to the preceding Claims, wherein a read address is provided to the first redundancy circuit via read address lines during the read operation and write address is provided to the second redundancy circuit during the write operation via write address lines that are separate from the read address lines. A flash memory according to any of the preceding Claims, wherein the address stored in the first redundancy circuit is accessed for a read operation to the defective memory cell in the memory and is not accessed for write operation to the defective memory cell. A flash memory according to any of the preceding Claims,

wherein the first redundancy circuit does not provide the address stored therein for a write operation to the memory cell; and

wherein the second redundancy circuit does not provide the address stored therein for a read operation to the memory cell.
A flash memory according to Claim 14,

wherein the memory cell is included in a first bank of the integrated circuit memory;

wherein a first entry in the first redundancy circuit includes an address of a first defective memory cell in the first bank; and

wherein a second entry in the first redundancy circuit includes an address of a second defective memory cell in a second bank of the flash memory that is separate from the first bank.
A method for operating a flash memory adapted for read-while-write operation so that read and write operations can simultaneously be performed with respect to different banks of the memory,

characterized by the following steps: storing read repair information associated with a first defective memory cell in a first redundancy circuit; storing write repair information associated with a second defective memory cell in a second redundancy circuit that is separate from the first redundancy circuit; providing the read repair information from the first redundancy circuit for read operations to the memory cell to repair data read from the first defective memory cell; and providing the write repair information from the second redundancy circuit for write operations to the memory cell to avoid writing data to the second defective memory cell.
A method according to Claim 16, wherein a first read or write operation is performed in a first sector of a bank of the flash memory while simultaneously performing a second read or write operation in a second sector of another bank of the flash memory. A method according to Claim 16 or 17, wherein the read repair information is not provided by the first redundancy circuit for the write operation and the write repair information is not provided by the second redundancy circuit for the read operation. A method according to any of Claims 16 to 18, wherein the read repair information is provided by the first redundancy circuit for the read operation to any of a plurality of banks of the flash memory, and the write repair information is provided by the second redundancy circuit for the write operation to any of the plurality of banks.
Anspruch[fr]
Mémoire flash adaptée pour un fonctionnement en lecture pendant l'écriture, afin que des opérations de lecture et d'écriture puissent être exécutées simultanément sur des banques différentes de la mémoire, caractérisée par - un premier circuit de redondance (651), configuré pour fournir des informations correctives de lecture, pour des opérations de lecture dans la mémoire flash et/ou pour stocker une adresse d'une cellule de mémoire défectueuse dans la mémoire flash ; et - un second circuit de redondance (652), distinct du premier circuit de redondance, configuré pour fournir des informations correctives d'écriture, pour des opérations d'écriture dans la mémoire flash et/ou pour stocker une adresse de la cellule de mémoire défectueuse. Mémoire flash selon la revendication 1, dans laquelle les informations correctives de lecture et les informations correctives d'écriture sont associées à une même adresse d'une cellule de mémoire défectueuse dans une banque de la mémoire flash. Mémoire flash selon la revendication 1 ou 2, dans laquelle le premier circuit de redondance ne fournit pas les informations correctives de lecture pour des opérations d'écriture dans une banque de la mémoire flash et le second circuit de redondance ne fournit pas les informations correctives d'écriture pour des opérations de lecture dans la banque. Mémoire flash selon la revendication 2 ou 3, dans laquelle une première rubrique dans le premier circuit de redondance comprend une adresse d'une première cellule de mémoire défectueuse dans une première banque associée aux informations correctives de lecture et dans laquelle une seconde rubrique du premier circuit de redondance comprend une adresse d'une seconde cellule de mémoire défectueuse dans une seconde banque de la mémoire flash qui est distincte de la première banque. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle la mémoire flash est configurée pour exécuter une première opération de lecture ou d'écriture dans un premier secteur d'une banque de la mémoire flash tout en exécutant simultanément une seconde opération de lecture ou d'écriture dans un second secteur d'une autre banque de la mémoire flash. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle le premier circuit de redondance est consacré au stockage d'adresses de cellules de mémoire défectueuses et d'informations correctives de lecture associées, fournies pour des opérations de lecture dans l'une quelconque d'une pluralité de banques de la mémoire flash et dans lequel le second circuit de redondance est consacré au stockage d'adresses de cellules de mémoire défectueuses et d'informations correctives d'écriture associées, fournies pour des opérations d'écriture dans l'une quelconque d'une pluralité de banques de la mémoire flash. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle la mémoire flash comprend une mémoire flash de type NON OU ou NON ET. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle les informations correctives de lecture et les informations correctives d'écriture comprennent des informations identiques. Mémoire flash selon l'une quelconque des revendications précédentes, comprenant en outre une pluralité de banques, dans laquelle le premier circuit de redondance est configuré pour fournir les informations correctives de lecture pour les opérations de lecture dans l'une quelconque d'une pluralité de banques et dans laquelle le second circuit de redondance est configuré pour fournir les informations correctives d'écriture pour les opérations d'écriture dans l'une quelconque d'une pluralité de banques. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle le premier circuit de redondance fournit des informations correctives de lecture, pour des opérations de lecture, qui indiquent au moins une position de bit défectueux dans l'adresse à lire et dans laquelle le second circuit de redondance fournit des informations correctives d'écriture, pour des opérations d'écriture, qui indiquent au moins une position de bit défectueux dans l'adresse à écrire. Mémoire flash selon l'une quelconque des revendications précédentes, comprenant en outre : un circuit amplificateur de détection, couplé électriquement au premier circuit de redondance, les informations correctives de lecture étant fournies au circuit amplificateur de détection pendant l'opération de lecture, via des lignes correctives de lecture ; et un circuit d'attaque en écriture, couplé électriquement au second circuit de redondance, les informations correctives d'écriture étant fournies au circuit d'attaque en écriture via des lignes correctives d'écriture qui sont distinctes des lignes correctives de lecture. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle une adresse de lecture est fournie au premier circuit de redondance via des lignes d'adresse de lecture pendant l'opération de lecture et une adresse d'écriture est fournie au second circuit de redondance pendant l'opération d'écriture, via des lignes d'adresse d'écriture qui sont distinctes des lignes d'adresse de lecture. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle l'adresse stockée dans le premier circuit de redondance est utilisée pour l'accès d'une opération de lecture dans la cellule de mémoire défectueuse et n'est pas utilisée pour l'accès d'une opération d'écriture dans la cellule de mémoire défectueuse. Mémoire flash selon l'une quelconque des revendications précédentes, dans laquelle le premier circuit de redondance ne fournit pas l'adresse qu'il stocke pour une opération d'écriture dans la cellule de mémoire ; et dans laquelle le second circuit de redondance ne fournit pas l'adresse qu'il stocke pour une opération de lecture dans la cellule de mémoire. Mémoire flash selon la revendication 14,

dans laquelle la cellule de mémoire est incluse dans une première banque de la mémoire à circuits intégrés ;

dans laquelle une première rubrique du premier circuit de redondance contient une adresse d'une première cellule de mémoire défectueuse dans la première banque ; et

dans laquelle une seconde rubrique dans le premier circuit de redondance contient une adresse d'une seconde cellule de mémoire défectueuse dans une seconde banque de la mémoire flash qui est distincte de la première banque.
Procédé de fonctionnement d'une mémoire flash adaptée pour un fonctionnement en lecture pendant l'écriture, afin que des opérations de lecture et d'écriture puissent être exécutées simultanément sur des banques différentes de la mémoire, caractérisée par les étapes consistant à : stocker des informations correctives de lecture, associées à une première cellule de mémoire défectueuse dans un premier circuit de redondance ; stocker des informations correctives d'écriture associées à une seconde cellule de mémoire défectueuse dans un second circuit de redondance qui est distinct du premier circuit de redondance ; fournir les informations correctives de lecture, à partir du premier circuit de redondance, pour des opérations de lecture dans la cellule de mémoire, afin de corriger les données lues dans la première cellule de mémoire défectueuse ; et fournir les informations correctives d'écriture, à partir du second circuit de redondance, pour des opérations d'écriture dans la cellule de mémoire, afin d'éviter d'écrire des données dans la seconde cellule de mémoire défectueuse. Procédé selon la revendication 16, dans lequel une première opération de lecture ou d'écriture est exécutée dans un premier secteur d'une banque de la mémoire flash tout en exécutant simultanément une seconde opération de lecture ou d'écriture dans un second secteur d'une autre banque de la mémoire flash. Procédé selon la revendication 16 ou 17, dans lequel les informations correctives de lecture ne sont pas fournies par le premier circuit de redondance pour l'operation d'écriture et les informations correctives d'écriture ne sont pas fournies par le second circuit de redondance pour l'opération de lecture. Procédé selon l'une quelconque des revendications 16 à 18, dans lequel les informations correctives de lecture sont fournies par le premier circuit de redondance pour l'opération de lecture dans l'une quelconque d'une pluralité de banques de la mémoire flash et les informations correctives d'écriture sont fournies par le second circuit de redondance pour l'opération d'écriture dans l'une quelconque de la pluralité de banques.






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