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Dokumentenidentifikation EP1028432 11.01.2007
EP-Veröffentlichungsnummer 0001028432
Titel Logische Schaltung
Anmelder STMicroelectronics Ltd., Almondsbury, Bristol, GB
Erfinder Barnes, William Bryan, Bradley Stoke, Bristol BS32 9AR, GB
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 60032040
Vertragsstaaten DE, FR, GB, IT
Sprache des Dokument EN
EP-Anmeldetag 01.02.2000
EP-Aktenzeichen 003007853
EP-Offenlegungsdatum 16.08.2000
EP date of grant 29.11.2006
Veröffentlichungstag im Patentblatt 11.01.2007
IPC-Hauptklasse G11C 8/00(2006.01)A, F, I, 20051017, B, H, EP

Beschreibung[en]

The present invention relates to a CMOS logic circuit, and more particularly but not exclusively to a CMOS logic circuit for use as a line driver.

The well known problem when driving capacitive loads in integrated circuits, such as capacitive lines, is to provide a rapid transition in voltage on the line. One requirement for achieving this aim is to provide an output circuit having a high current capacity but it is also important to drive the output circuit itself with fast transitions in such a way as to enable the output circuit to behave optimally.

One of the problems with known driver circuits is that logic elements in the driver circuitry are required to respond rapidly to both positive-point and negative-going transitions to operate the output circuitry: fast circuitry tends to have small dimensions, and thus low current capacity.

It is an object of the present invention to at least partly overcome the problems of the prior art.

Document JP-10125798A describes a semiconductor logic device with approximately constant switching speed independent of the logic condition of input signals.

According to the present invention there is provided a CMOS logic circuit having plural inputs and a circuit output, the logic circuit having a first stage and a second stage, the first stage receiving said plural inputs and providing a first stage output, the second stage receiving a first stage output and providing a second stage output which is coupled to said circuit output, wherein the first stage comprises two input logic gates, each of said logic gates being configured to have a higher current capability in response to an input transition of one polarity than to an input transition of the opposite polarity, such that said transition of said one polarity causes said circuit output to assume a first logic value, and said second stage having a control input, the second stage being configured to have a higher current capability in response to a first polarity transition at said control input than to a second opposite polarity transition at said control input, wherein said first polarity transition causes said circuit output to assume a second logic value opposite to said first logic value.

Preferably the first stage output is coupled to an inverter for driving an output capacitive load.

Advantageously said second stage comprises two current paths connected between said second stage output and a reference voltage-receiving node, each of said current paths having a first transistor connected to said second stage output and a second transistor connected to a reference voltage-receiving node, wherein said first and second transistors are connected in series, and said first stage has two outputs each of said outputs being coupled to the control gates of a first transistor and a respective one of said current paths and a second transistor in a respective other current path, said control input comprising said reference voltage-receiving node.

Preferably said first stage comprises a plurality of CMOS logic gates, each of said gates having P conductivity transistors and N conductivity transistors, wherein the width of the P conductivity transistors is larger than the width of the N transistors.

Preferably the first and second transistors of the second stage are N conductivity transistors, and said second stage further comprises at least one P transistor wherein the width of the N conductivity transistors is substantially greater than that of the P transistor.

In a less preferred embodiment there is provided a CMOS logic circuit for driving a capacitive load, having an input circuit and an output circuit, the output circuit having an output to which, in use, said capacitive load is connected the input circuit having at least one CMOS logic gate comprising P and N conductivity transistors, wherein the width of the P conductivity transistors is substantially greater than that of the N conductivity transistors whereby said input stage provides transitions at the output of the output stage into said capacitive load which are faster in one sense than in the other sense and said output circuit comprises P conductivity and N conductivity transistors receiving an output from said input stage and further receiving a control input, whereby the dimensions of said P and N type transistors of said output stage are selected to provide faster output transitions into said capacitive load in said second sense than in said first sense.

The present invention will now be described with reference to two preferred embodiments in the following drawings in which:

  • Figure 1 shows a first embodiment of a line driver circuit in accordance with the present invention
  • Figure 2 shows a timing diagram for the embodiment of Figure 1. Figure 3 shows a second embodiment of a line driver circuit in accordance with the present invention.

In the various figures like reference numerals will refer to like parts.

Referring to Figure 1 a line driver circuit 1 consists generally of three stages, namely an input stage 2, a second stage 3 and an output stage 4. The output stage 4 consists of an output inverter 10 having an output terminal 11 which constitutes the circuit output and an input node 12. The input node 12 is the output node of the second stage 3 which consists of a P type transistor 20 coupled between the output node 12 and a positive supply VDD, and further comprises two parallel current paths 21, 22 connected between the output node 12 and a circuit node 24. The first current path 21 consists of a first N transistor 25 having its drain connected to the output node 12 and its source connected to the drain of a second N type transistor 26, the source of the second type transistor 26 being connected to the circuit node 24. Similarly the second circuit path 22 consists of a first N type transistor 27 having its drain connected to the output node 12 and its source connected to the drain of a second N type transistor 28, whose source is connected commonly to that of the second transistor 26 of the first current path to the circuit node 24. The N type transistors are substantially identical in width to one another and of greater width, for example four times greater, than the width of the P type transistor 20. The gate of the first transistor 25 of the first current path 21 is connected to the gate of the second transistor 28 of the second current path 22 and the gate of the first transistor 27 of the second current path 22 is connected to the gate of the second transistor 26 of the first current path 22.

The input stage comprises two input CMOS NOR gates 40 and 41. The first NOR gate 40 has two input nodes 42 and 43 and an output node 44 which is connected to the commoned gates of the first transistor 27 of the second current path 22 and the second transistor 26 of the first current path 21.

Similarly the second NOR gate 41 has two inputs 45 and 46 and an output 47 the output being connected to the commoned gates of the second transistor 28 of the second current path 22 and the first transistor 25 of the first current path 21.

As noted above, the NOR gates are CMOS devices, and thus comprise both P conductivity and N conductivity transistors. The width of the P transistor is greater, for example six times greater, than that of the N transistors.

Operation of the circuit of Figure 1 will now be described with additional reference to Figure 2. The embodiment is a wordline driver and output 11 shows the voltage on the wordline which is enabled in response to the latest-negative going transition of one of the inputs 42-46, in this case input 42. Disablement of the wordline, in other words transition from logic level 1 to logic level 0 occurs at time T1 in response to a transition at node 24 which must occur before the circuit inputs 42,43,45,46 have returned to logic 1.

It will be understood by those skilled in the art that for the output terminal to be at a logical high level, the output node 12 of the second stage must be at a low level. For this to occur both the NOR gates 40 and 41 must have high potentials at their output terminals 44 and 47, so that both current paths 21 and 22 are enabled, and circuit node 24 must be connected to a low voltage, for example reference voltage VSS.

If only one of the NOR gates 40, 41 has a high potential at its output then neither of the two current paths 21 and 22 will conduct since one transistor in each current path will be blocked.

For the output of the NOR gate to be at logic one, both of the inputs will be at logic zero.

Thus it will be understood that for all conditions where the inputs are other than logic zero the circuit output 11 will be at a low potential. The operation of the circuit will therefore be considered starting from the conditions where circuit inputs 43,45 and 46 are at logic zero but circuit input 42 is at logic one. In this state, the second NOR gate 41 has a high output at its output node 47 but the first NOR gate 40 has a low output at its output 44. If the first input 42 makes a transition from high to low, the relatively large P type transistors in the NOR gate 40 will cause the gate output node 44 to change in potential relatively rapidly from a logic zero to a logic one state. This will rapidly drive the first transistor 27 of the second current circuit 22 and the second transistor 26 of the first current path 21 to a saturated condition and cause the output node 12 to fall rapidly to logic zero. By contrast, at a later transition in the first input from logic one to logic zero, the output 44 of the first NOR gate 40 will change in potential relatively slowly from logic one to logic zero due to the relatively small current carrying capacity of the N type transistors in the NOR gate 40.

To ensure a fast rise in potential at second stage output node 12 the circuit node 24 is driven from a separately-derived disable potential which is at a logic low potential when the inputs to the NOR gates are required to switch the line connected to output terminal 11 and which is raised to logic one at times when it is required to disable the line connected to the terminal 1.

The fast rise on the output node 12 of the second stage will occur in part due to the fact that the rising potential on the circuit node 24 is conducted through the conductive N transistors 25-28 of the first and second current paths acting as source followers. Thus it is essential that the potential difference supplied to the circuit is sufficient to overcome the relevant threshold voltage of the transistors in this embodiment. Where a low voltage operation is intended, a modified circuit is required.

The symmetrical nature of the current paths 21 and 22 reduces the possibility of charge storing on the gates of the transistors. This in turn allows the width of the P transistor 20 to be relatively low.

Referring to the second embodiment, it will be noted that the circuit of Figure 3 is substantially similar to that of Figure 1 with the exception that circuit node 24 is now permanently connected to a reference potential and the control input for disabling the output at node 11 is provided by input node 124 supplied to the output inverter 116. This arrangement may under certain circumstances be advantageous with respect to the embodiments shown in Figure 1 because the control input which disables the output is provided as close as possible to the output itself.

In the inverter 110, it will be seen that the control input 124 forms the positive supply VDD to the P conductivity transistor of the inverter. In this case, the voltage applied to the control input 124 is the inverse of that provided to the control node 24 of the first embodiment so that node 124 is at a high potential during enabling operation and at a low potential during disabling operation.


Anspruch[de]
CMOS-Logikschaltkreis mit mehreren Eingängen (42, 43, 45, 46) und einem Schaltkreisausgang (11), wobei der Logikschaltkreis eine erste Stufe (2) und eine zweite Stufe (3) aufweist, wobei die erste Stufe (2) die mehreren Eingänge (42, 43, 45, 46) erhält und einen ersten Stufenausgang (44, 47) bereitstellt, wobei die zweite Stufe (3) den ersten Stufenausgang (44, 47) erhält und einen zweiten Stufenausgang (12) bereitstellt, der mit dem Schaltkreisausgang (11) verbunden ist,

wobei die erste Stufe (2) zwei Eingangslogikgatter (40, 41) umfasst, wobei jedes der Logikgatter (40, 41) konfiguriert ist, dass es in Antwort auf einen Eingangsübergang einer Polarität eine höhere Stromleistungsfähigkeit als auf einen Eingangsübergang der entgegengesetzten Polarität aufweist, so dass der Übergang der einen Polarität bewirkt, dass der Schaltkreisausgang (11) einen ersten logischen Wert annimmt, und die zweite Stufe (3) einen Steuereingang (24) aufweist, wobei die zweite Stufe (3) konfiguriert ist, dass sie in Antwort auf einen Übergang erster Polarität an dem Steuereingang (24) eine höhere Stromleistungsfähigkeit als auf einen Übergang zweiter entgegengesetzter Polarität an dem Steuereingang (24) aufweist, wobei der Übergang erster Polarität bewirkt, dass der Schaltkreisausgang (11) einen zweiten dem ersten logischen Wert entgegengesetzten logischen Wert annimmt.
CMOS-Logikschaltkreis nach Anspruch 1, bei dem der zweite Stufenausgang (12) mit einem Inverter (10) verbunden ist, um eine kapazitive Ausgangslast anzusteuern. CMOS-Logikschaltkreis nach einem der Ansprüche 1 bis 2, bei dem die zweite Stufe (3) zwei Strompfade umfasst, die zwischen dem zweiten Stufenausgang (12) und einem eine Referenzspannung erhaltenden Knoten (24) angeschlossen sind, wobei jeder der Strompfade einen ersten Transistor (25, 27), der mit dem zweiten Stufenausgang (12) verbunden ist, und einen zweiten Transistor (26, 28) aufweist, der mit einem eine Referenzspannung erhaltenden Knoten (24) verbunden ist, wobei die ersten und zweiten Transistoren in Reihe angeschlossen sind, und die erste Stufe (2) zwei Ausgänge (44, 47) aufweist, wobei jeder der Ausgänge mit den Steuer-Gates eines ersten Transistors (27, 28) in einem entsprechenden der Strompfade und eines zweiten Transistors (25, 26) in einem entsprechenden anderen Strompfad verbunden sind, wobei der Steuereingang den eine Referenzspannung erhaltenden Knoten (24) umfasst. CMOS-Logikschaltkreis nach einem der Ansprüche 1 bis 3, bei dem die erste Stufe (2) eine Mehrzahl an CMOS-Logikgattern umfasst, wobei jedes der Gatter Transistoren mit P-Leitfähigkeit und Transistoren mit N-Leitfähigkeit aufweist, wobei die Breite der Transistoren mit P-Leitfähigkeit größer als die Breite der N-Transistoren ist. CMOS-Logikschaltkreis nach einem vorherigen Anspruch, bei dem die ersten und zweiten Transistoren (25, 26, 27, 28) der zweiten Stufe (3) Transistoren mit N-Leitfähigkeit sind und die zweite Stufe (3) ferner wenigstens einen P-Transistor (20) umfasst, wobei die Breite der Transistoren mit N-Leitfähigkeit deutlich größer als die des P-Transistors ist.
Anspruch[en]
A CMOS logic circuit having plural inputs (42, 43, 45, 46) and a circuit output (11); the logic circuit having a first stage (2) and a second stage (3), the first stage (2) receiving said plural inputs (42, 43, 45, 46) and providing a first stage output (44, 47), the second stage (3) receiving said first stage output (44, 47) and providing a second stage output (12) which is coupled to said circuit output (11)

wherein the first stage (2) comprises two input logic gates (40, 41), each of said logic gates (40, 41) being configured to have a higher current capability in response to an input transition of one polarity than to an input transition of the opposite polarity, such that said transition of said one polarity causes said circuit output (11) to assume a first logic value, and said second stage (3) having a control input (24), the second stage (3) being configured to have a higher current capability in response to a first polarity transition at said control input (24) than to a second opposite polarity transition at said control input (24), wherein said first polarity transition causes said circuit output (11) to assume a second logic value opposite to said first logic value.
The CMOS logic circuit of claim 1 wherein the second stage output (12) is coupled to an inverter (10) for driving an output capacitive load. The CMOS logic circuit of any of claims 1-2 wherein said second stage (3) comprises two current paths connected between said second stage output (12) and a reference voltage-receiving node (24), each of said current paths having a first transistor (25, 27) connected to said second stage output (12) and a second transistor (26, 28) connected to a reference voltage-receiving node (24), wherein said first and second transistors are connected in series, and said first stage (2) has two outputs (44, 47) each of said outputs being coupled to the control gates of a first transistor (27, 28) in a respective one of said current paths and a second transistor (25, 26) in a respective other current path, said control input comprising said reference voltage-receiving node (24). The CMOS logic circuit of any of claims 1-3 wherein said first stage (2) comprises a plurality of CMOS logic gates, each of said gates having P conductivity transistors and N conductivity transistors, wherein the width of the P conductivity transistors is larger than the width of the N transistors. The CMOS logic circuit of any preceding claim wherein the first and second transistors (25, 26, 27, 28) of the second stage (3) are N conductivity transistors, and said second stage (3) further comprises at least one P transistor (20) wherein the width of the N conductivity transistors is substantially greater than that of the P transistor.
Anspruch[fr]
Circuit logique CMOS ayant une pluralité d'entrées (42, 43, 45, 46) et une sortie de circuit (11), le circuit logique comportant un premier étage (2) et un second étage (3), le premier étage (2) recevant la pluralité d'entrées (42, 43, 45, 46) et fournissant une sortie de premier étage (44, 47), le second étage (3) recevant la sortie du premier étage (44, 47) et fournissant une sortie de second étage (12) qui est couplée à la sortie (11) du circuit ;

dans lequel le premier étage (2) comprend deux portes logiques d'entrée (40, 41), chacune des portes logiques (40, 41) étant agencée pour avoir une plus forte capacité de courant en réponse à une transition d'entrée d'une première polarité qu'à une transition d'entrée de la polarité opposée, de sorte que ladite transition de la première polarité amène la sortie (11) du circuit à prendre une première valeur logique, et le second étage (3) ayant une entrée de commande (24), le second étage (3) étant agencé pour avoir une plus forte capacité en courant en réponse à une transition d'une première polarité sur l'entrée de commande (24) qu'en réponse à une transition de polarité opposée sur l'entrée de commande (24), dans lequel la transition de première polarité amène la sortie (11) du circuit à prendre une seconde valeur logique opposée à la première valeur logique.
Circuit logique CMOS selon la revendication 1, dans lequel la sortie (12) du second étage est couplée à un inverseur (10) pour piloter une charge de sortie capacitive. Circuit logique CMOS selon la revendication 1 ou 2, dans lequel le second étage 3 comprend deux trajets de courant connectés entre la sortie (12) du second étage et un noeud (24) de réception de tension de référence, chacun des trajets de courant comportant un premier transistor (25, 27) connecté à la sortie (12) de second étage et un second transistor (26, 28) connecté à un noeud de réception de tension de référence (24), dans lequel les premier et second transistors sont connectés en série et le premier étage (2) a deux sorties (44, 47), chacune des sorties étant couplée aux grilles de commande d'un premier transistor (27, 28) dans l'un respectif des trajets de courant et d'un second transistor (25, 26) dans un autre trajet de courant respectif, l'entrée de commande comprenant le noeud (24) de réception de tension de référence. Circuit logique CMOS selon l'une quelconque des revendications 1 à 3, dans lequel le premier étage (2) comprend une pluralité de portes logiques CMOS, chacune des portes comprenant des transistors à canal P et des transistors à canal N, la largeur des transistors à canal P étant plus grande que celle des transistors N. Circuit logique CMOS selon l'une quelconque des revendications précédentes, dans lequel les premier et second transistors (25, 26, 27, 28) du second étage (3) sont des transistors à canal N, et le second étage (3) comprend en outre au moins un transistor P (20), la largeur du transistor à canal N étant sensiblement supérieure à celle du transistor P.






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