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Dokumentenidentifikation EP1153475 22.02.2007
EP-Veröffentlichungsnummer 0001153475
Titel GATE-VORSPANNUNGSVORRICHTUNG
Anmelder Infineon Technologies AG, 81669 München, DE
Erfinder ERICSSON, Per, S-174 56 Sundbyberg, SE;
AFEKENSTAM, Nils, S-171 58 Solna, SE;
JOHANSSON, Jan, S-194 54 Upplands Väsby, SE;
SJÖDEN, Henrik, Morgan Hill, CA 95037, US
DE-Aktenzeichen 69934828
Vertragsstaaten DE, ES, FI, FR, GB, IT, NL, SE
Sprache des Dokument EN
EP-Anmeldetag 30.12.1999
EP-Aktenzeichen 999670508
WO-Anmeldetag 30.12.1999
PCT-Aktenzeichen PCT/SE99/02504
WO-Veröffentlichungsnummer 2000044089
WO-Veröffentlichungsdatum 27.07.2000
EP-Offenlegungsdatum 14.11.2001
EP date of grant 10.01.2007
Veröffentlichungstag im Patentblatt 22.02.2007
IPC-Hauptklasse H03F 1/30(2006.01)A, F, I, 20051017, B, H, EP

Beschreibung[en]
TECHNICAL FIELD

The invention relates generally to LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistors and more specifically to a gate biasing arrangement for an RF power LDMOS field effect transistor for temperature compensation of its quiescent current.

BACKGROUND OF THE INVENTION

The appended drawing, Fig. 1A illustrates a conventional way of biasing the gate G of an RF power LDMOS field effect transistor 1 to a gate voltage VG that gives a desired value of quiescent current IDQ of the transistor 1. The RF signal is supplied to the gate G via a terminal 2.

To bias the gate G of the transistor 1, a fixed resistor R1 is connected between the gate G and the source S, which normally is connected to ground, and a variable resistor R2 is connected between the gate G and a terminal at a positive voltage. By means of the resistor R2, the gate voltage VG is adjusted to a value that gives the desired quiescent current IDQ through the transistor 1.

The value of the quiescent current IDQ is commonly chosen to give a flat gain versus output power characteristic. Any deviation from this chosen IDQ value will degrade the linearity performance of the transistor.

For a given value of the gate voltage VG, the quiescent current IDQ is temperature dependent. Consequently, temperature changes will cause degradation of the performance of the transistor 1.

The temperature coefficient of the transistor's quiescent current is a function of the gate bias voltage. The relatively low values of the gate bias voltage VG that are normally used, gives a positive temperature coefficient, i.e. the quiescent current IDQ increases with temperature.

A common approach to reduce the variation of the quiescent current IDQ with changes in temperature is to introduce a discrete diode DI in series with the resistor R1 as shown in fig 1B. The voltage drop across the diode decreases as the temperature increases and thus partially eliminates the RF transistor's quiescent current temperature dependence.

There are however two apparent drawbacks of using a diode for temperature compensation. Firstly, the temperature characteristic of a diode does not exactly track the temperature characteristic of an RF LDMOS transistor. Secondly, it is hard to achieve a good thermal coupling between a discrete diode and the transistor, resulting in different temperatures for the two components.

EP 060094 discloses a monolithic microwave integrated circuit including a bias stabilizing circuit in accordance with the state of the art. The quiescent current through an active transistor is set by a resistor and a biasing transistor, whereby both the transistor as well as the resistor will be affected by chip temperature variations. Consequently, the quiescent current of the active transistor will vary with the chip temperature. Further, EP 060094 relates to GaAs transistors, which consume gate current.

SUMMARY OF THE INVENTION

The object of the invention is to eliminate the chip temperature dependency of the quiescent current of the power transistor.

This is attained by controlling the gate bias voltage of the power transistor by means of the output voltage of a biasing transistor residing on the same silicon chip as the power transistor, and by interconnecting the gate and drain of the biasing transistor and feeding it with a constant current from external circuitry.

Since the gate and drain of the biasing transistor are connected to each other, the gate voltage of the biasing transistor will automatically adjust to sustain the forced drain current. Due to the inherent temperature dependence of the biasing transistor, the gate bias voltage will decrease as temperature increases. Consequently, the gate bias voltage of the power transistor will decrease with increasing temperature resulting in a constant quiescent current IDQ.

The invention will also handle the case where the gate bias is higher, resulting in a negative temperature coefficient of the quiescent current.

BRIEF DESCRIPTION OF THE DRAWING

The invention will be described more in detail below with reference to the appended drawing on which Figs. 2 and 3 illustrate first and second embodiments, respectively, of a gate biasing arrangement according to the invention.

DETAILED DESCRIPTION

In Figs. 2 and 3, circuit elements that are identical to circuit elements in Figs. 1A and 1B described above are provided with the same reference characters.

In Fig. 2, a first gate biasing arrangement in accordance with the invention is illustrated for the RF power LDMOS transistor 1, which is identical to the transistor shown in Figs. 1A and 1B.

As in Figs. 1A and 1B, the RF signal is supplied to the gate G of the power transistor 1 via the terminal 2 in Fig. 2.

The gate biasing arrangement according to the invention, comprises a biasing LDMOS field effect transistor 3 which has its gate G3 and drain D3 interconnected, which is connected with its interconnected gate G3 and drain D3 to the gate G of the power transistor via an inductor L, and which is connected with its source S3 to the source S of the power transistor 1.

In accordance with the invention, the interconnected gate G3 and drain D3 of the biasing transistor 3 is to be supplied with a constant biasing DC current.

In Fig. 2, this constant biasing current IB is supplied by external circuitry (not shown) via the RF signal input terminal 2 together with incoming RF signals. The inductor L is used to isolate the incoming RF signals from the biasing transistor 3.

The output voltage from the biasing transistor 3 controls the gate biasing voltage VG of the power transistor 1.

The output voltage from the biasing transistor 3 will decrease as temperature increases since the input biasing current IB is fixed. Consequently, the gate bias voltage VG of the power transistor 1 will also decrease with increasing temperature to keep the quiescent current IDQ constant.

Thus, the temperature dependency of the quiescent current IDQ for the power transistor 1 will be eliminated.

The current value ratio IDQ/IB is a function of the difference in size between the power transistor 1 and the biasing transistor 3.

In accordance with the invention, the biasing transistor 3 resides on the same silicon chip (not shown) as the power transistor 1 to optimize temperature tracking, and the biasing transistor 3 is much smaller than the power transistor 1, e.g. more than 100 times smaller.

It should be pointed out that the current ratio will not be precisely equal to the ratio in transistor size since the biasing transistor 3 operates at a much lower drain-to-source voltage than the power transistor.

The inductor L for isolating the biasing transistor 3 from the RF signals in Fig. 2 can be integrated on the same chip as the transistors 2 and 3, but can also be a discrete element outside the chip .

Fig. 3 illustrates a second embodiment of a gate biasing arrangement in accordance with the invention.

The embodiment in Fig. 3 is almost identical to the embodiment in Fig. 2 in that a biasing LDMOS transistor 3 having its gate G3 and drain D3 interconnected, is connected with its interconnected gate G3 and drain D3 to the gate G of a power LDMOS transistor 1 via an RF signal isolating means which in this embodiment is a high impedance element Z, realized either as a resistor or an inductor. A resistor might be chosen for ease of integration with the transistor.

However, in the embodiment in Fig. 3, the interconnected gate G3 and drain D3 of the biasing transistor 3 are not supplied with the constant biasing current IB via the RF signal input terminal 2 of the power transistor 1. Instead, the interconnected gate G3 and drain D3 are supplied with the constant biasing current IB directly from an external current source (not shown).

From the above, it should be apparent that the temperature dependency of the quiescent current of a power transistor can be eliminated by controlling the gate bias voltage of the power transistor by means of the output voltage of a biasing transistor residing on the same silicon chip as the power transistor, the biasing transistor being smaller than the power transistor and by interconnecting the gate and drain of the biasing transistor and feeding it with a constant current from external circuitry.


Anspruch[de]
Gatevorspannungsanordnung für einen HF-LDMOS-Leistungstransistor (1), der sich auf einem Chip befindet, umfassend, auf dem gleichen Chip, einen LDMOS-Vorspannungstransistor (3), dessen Gateelektrode (G3) und Drainelektrode (D3) zusammengeschaltet sind, wobei der Zusammenschaltungspunkt zwischen der Gateelektrode (G3) und der Drainelektrode (D3) des Vorspannungstransistors (3) mit der Gateelektrode (G) des Leistungstransistors (1) über ein HF-Isolierungsmittel (L, R) verbunden ist, wobei die Sourceelektrode (S3) des Vorspannungstransistors (3) mit der Sourceelektrode (S) des Leistungstransistors (1) verbunden ist, dadurch gekennzeichnet, daß der Vorspannungstransistor (3) kleiner ist als der Leistungstransistor (1), und der Zusammenschaltungspunkt zwischen der Gateelektrode (G3) und der Drainelektrode (D3) des Vorspannungstransistors (3) dafür ausgelegt ist, mit einem extern erzeugten konstanten vorspannenden Strom (IB) versorgt zu werden, damit der Ruhestrom (IDQ) des Leistungstransistors (1) von Chiptemperaturvariationen unabhängig wird. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß der Vorspannungstransistor (3) um mehr als das 100fache kleiner ist als der Leistungstransistor (1). Anordnung nach einem der Ansprüche 1-2, wobei das HF-Isolierungsmittel eine Induktionsspule (L) ist, dadurch gekennzeichnet, daß der Zusammenschaltungspunkt zwischen der Gateelektrode (G3) und Drainelektrode (D3) des Vorspannungstransistors (3) dafür ausgelegt ist, mit dem konstanten vorspannenden Strom (IB) über die Induktionsspule (L) gespeist zu werden. Anordnung nach einem der Ansprüche 1-2, wobei das HF-Isolierungsmittel ein Widerstand (R) mit einem hohen Widerstandswert ist, dadurch gekennzeichnet, daß der Zusammenschaltungspunkt zwischen der Gateelektrode (G3) und der Drainelektrode (D3) des Vorspannungstransistors (3) dafür ausgelegt ist, direkt mit dem konstanten vorspannenden Strom (IB) versorgt zu werden.
Anspruch[en]
A gate biasing arrangement for an RF power LDMOS transistor (1) residing on a. chip, comprising, on the same chip, a biasing LDMOS transistor (3) having its gate (G3) and drain (D3) interconnected, the interconnection point between the gate (G3) and the drain (D3) of the biasing transistor (3) being connected to the gate (G) of the power transistor (1) via an RF isolating means (L, R), the source (S3) of the biasing transistor (3) being connected to the source (S) of the power transistor (1), characterized in that the biasing transistor (3) is smaller than the power transistor (1), and the interconnection point between the gate (G3) and the drain (D3) of the biasing transistor (3) is adapted to be supplied with an externally generated constant biasing current (IB) to make the quiescent current (IDQ) of the power transistor (1) independent of chip temperature variations. The arrangement as claimed in claim 1, characterized in that the biasing transistor (3) is more than 100 times smaller than the power transistor (1). The arrangement as claimed in any of claims 1 - 2, where said RF isolating means is an inductor (L), characterized in that the interconnection point between the gate (G3) and the drain (D3) of the biasing transistor (3) is adapted to be supplied with said constant biasing current (IB) via the inductor (L). The arrangement as claimed in any of claims 1 - 2, where said RF isolating means is a resistor (R) having a high resistance, characterized in that the interconnection point between the gate (G3) and the drain (D3) of the biasing transistor (3) is adapted to be directly supplied with said constant biasing current (IB).
Anspruch[fr]
Configuration de polarisation de grille pour un transistor LDMOS de puissance RF (1) implanté sur une puce, comportant, sur la même puce, un transistor LDMOS de polarisation (3) dont la grille (G3) et le drain (D3) sont interconnectés, le point d'interconnexion entre la grille (G3) et le drain (D3) du transistor de polarisation (3) étant relié à la grille (G) du transistor de puissance (1) via un moyen d'isolation des signaux RF (L, R), la source (S3) du transistor de polarisation (3) étant reliée à la source (S) du transistor de puissance, caractérisée en ce que le transistor de polarisation (3) est plus petit que le transistor de puissance (1), et en ce que le point d'interconnexion entre la grille (G3) et le drain (D3) du transistor de polarisation (3) est adapté pour être alimenté par un courant de polarisation constant (IB) généré extérieurement pour rendre le courant de repos (IDQ) du transistor de puissance (1) indépendant des variations de la température de la puce. Configuration selon la revendication 1, caractérisée en ce que le transistor de polarisation (3) est plus de 100 fois plus petit que le transistor de puissance (1). Configuration selon l'une quelconque des revendications 1 et 2, où ledit moyen d'isolation RF est une bobine inductrice (L), caractérisée en ce que le point d'interconnexion entre la grille (G3) et le drain (D3) du transistor de polarisation (3) est adapté pour être alimenté par ledit courant de polarisation constant (IB) via la bobine inductrice (L). Configuration selon l'une quelconque des revendications 1 et 2, où ledit moyen d'isolation RF est une résistance (R) présentant une résistance élevée, caractérisée en ce que le point d'interconnexion entre la grille (G3) et le drain (D3) du transistor de polarisation (3) est adapté pour être alimenté directement par ledit courant de polarisation constant (IB).






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