The invention relates to a battery or accumulator charger.
A problem which occurs in technologies where zener diodes
are not available, is driving an external FET (field effect transistor). FETs are,
for instance, used as current supply units in linear regulators or battery or accumulator
chargers as well as in a vast field of other applications.
In most such implementations, it is necessary to protect
the gate electrode of the FET from high voltages relative to the source electrode
potential. Gate voltage limitation is a necessity when FETs with low threshold voltages
are used, like in chargers for wireless applications (i.e. cellular or cordless
Beside the aspect of voltage limitation, it is desired
that the current outputted by the FET is controllable with high accuracy. Therefore,
the driving voltage for the FET is demanded to show a high degree of insensitivity
to variations of the operating voltage, often denoted as line variations.
Further, a very low minimum FET output current should be
Conventionally, operational amplifiers (opamps) are used
for driving an external FET. In the past, voltage protection has been accomplished
by adding an external clamping diode to the output of the opamp or by using an opamp
with an output stage provided with an integrated zener diode. These solutions, however,
suffer from low accuracy due to the fact that their null point (voltage output at
short-circuit input condition) is difficult to control. In order to design a regulator
with low minimum output current, an output FET with very small transconductance
and a driving opamp with a very high gain are required. The corresponding specifications
are difficult to meet.
The article "Stromverstärker mit MOSFETs", R. J. Horky,
Funkschau, DE, Franzis-Verlag K.G., München, Vol. 63, No. 21, describes a driver
circuit to be used as an audio line driver or an audio amplifier for headphones.
US 5,731,686 relates to a battery overtemperature protection
circuit which is used in a battery charger device.
US 5,774,021 relates to an operational transconductance
amplifier containing a differential pair of transistors. The operational transconductance
amplifier may be used in battery charges.
It is therefore an object of the invention, to provide
for an improved battery or accumulator charger equipped with a circuit for driving
an external FET which is insensitive to line variations. In particular, the invention
shall enable the implementation of a battery or accumulator charger with high accuracy
and low minimum output current. More particularly, the battery or accumulator charger
shall provide for an effective voltage limitation at the gate-source electrodes
of the external FET.
The object of the invention is solved by the battery or
accumulator charger according to the features of claim 1.
Thus, the battery or accumulator charger of the invention
includes a differential amplification stage, and a load resistor included in a current
flow path, the current flowing through the current flow path being controlled by
the voltage between two input terminals of the differential amplification stage
and being substantially independent of variations of either of the first or second
operating potential. As the load resistor being connected between the gate and source
electrodes of the FET, line variations do not result in voltage variations across
the gate and source electrodes of the FET.
Preferably, the resistance value of the load resistor is
chosen to provide a voltage across the gate and source electrodes of the FET near
or substantially equal to the threshold voltage of the FET in case the potentials
applied to the two input terminals of the differential amplification stage are set
to the same value. Then, the null point of the circuit is set to match with the
optimal low current operating condition of the FET. This increases the accuracy
of the battery or accumulator charger at very low source-drain currents of the FET.
According to a specifically advantageous aspect of the
invention, the differential amplification stage comprises a first and a second current
flow path, both thereof are biased by a common constant current source, the first
and second current flow paths are provided with a differential transistor pair the
control electrodes thereof are connected to the first and second input terminals,
respectively, and the current flow path of the output load resistor being either
the first or the second current flow path of the differential amplification stage.
In this embodiment, the load resistor is simply located in one of the flow paths
of the differential amplification stage. Thus, the common constant current source
feeding the differential amplification stage simultaneously supplies the current
flowing through the load resistor. As the maximum current flowing through one of
the first or second current flow paths of the differential amplification stage is
limited by the current outputted by the common constant current source, a built-in
limitation of the voltage across the load resistor is achieved.
Further preferred features and advantages of the invention
are described in the dependent claims.
The invention is illustrated in the accompanying drawings,
- Fig. 1
- is a schematic electrical diagram of a circuit in accordance with a preferred
embodiment of the invention;
- Fig. 2
- is a simplified block diagram for explanation of the null point of an opamp;
- Fig. 3
- is a pictorial representation of the output voltage of the circuit of Fig. 1
and of a conventional opamp versus the differential input voltage thereof; and
- Fig. 4
- is a schematic block diagram of a negative feedback control network applied
to an amplification circuit with a null point different from zero.
A schematic of an embodiment of the circuit for driving
an external FET is shown in Fig. 1. The driving circuit 1 has two current flow paths
2 and 3. The current flow path 2 includes a first bipolar npn transistor 4 and the
second current flow path 3 includes a second npn tranistor 5 connected in series
with a load resistor 6. The emitters of the first and second transistors 4, 5 are
connected to a common node 7.
A constant current source 8 is connected between an operating
potential Vss and the common node 7 to source a current Ibias to the two current
flow paths 2 and 3. On the other hand, the collector of the first transistor 4 and
a first terminal of the load resistor 6 are connected to another operating potential
Vdd. The second terminal of the load resistor 6 opposite to the first resistor terminal
is connected to the collector of the second transistor 5.
The constant current source 8, transistor pair 4 and 5,
and the load resistor 6 may be implemented in an integrated circuit (IC) which is
driven by the operating voltage Vdd-Vss.
Input terminals of the driving circuit 1 are represented
by lines 9 and 10 connected to the bases of the transistors 4 and 5, respectively.
An output terminal of the driving circuit 1 is denoted
by reference sign 11. The output terminal 11 is connected with the second current
flow path 3 at a point thereof between the collector of the second transistor 5
and the load resistor 6.
The external FET to be controlled by the driving circuit
1 is denoted by reference sign 12. In the arrangement shown in Fig. 1, the FET 12
is a PMOS FET. The source of the FET 12 is connected to Vdd whereas the gate of
the FET 12 is connected to the output terminal 11. The dash-dotted line represents
the boundary of the IC comprising the driving circuit 1.
Driving circuit 1 and FET 12 establish a linear regulator,
the output thereof is represented by the drain of the FET 12. This linear regulator,
for instance, may be a battery or accumulator charger. In this case, the battery
or accumulator to be charged is fed by the drain current Iload of the FET 12.
It is to be noted that the driving circuit 1, as concerns
the differential input transistor pair 4, 5 and the common current source 8, is
similar to a conventional opamp. However, a conventional opamp uses, as an input
stage, a symmetric differential amplifier whereas the two current flow paths 2,
3 are asymmetric due to the load resistor 6. Further, an opamp is equipped with
a transistor output amplification stage whereas the output stage of the circuit
according to Fig. 1 is represented by the load resistor 6, which is preferably realized
by a low ohmic polysilicon resistor.
In operation, the constant current source 8, which is controled
by a bandgap voltage (not shown), biases the two transistors 4, 5 by the total current
Ibias. Like the bandgap voltage, the current Ibias is independent of temperature
and parametric variations.
First, considering the voltage limitation aspect of the
driving circuit 1, the maximum voltage drop that can occur across the load resistor
6 is R*Ibias, where R denotes the resistance of the load resistor. Thus, irrespective
of the input voltages at lines 9 and 10, the maximum voltage between gate and source
of the FET 12 is limited to this specific value. Therefore, in the event of an over
voltage appearing at the source of the FET 12 (for instance due to a sudden increase
in Vdd), the potential at the gate of the FET 12 is automatically pulled up. This
protects the FET 12 from being damaged, provided that R*Ibias has a sufficient small
value, for instance 1,5 to 2,0 volts.
A further advantage of the driving circuit 1 is that it
is insensitive to line variations, i.e. variations of the operating potentials Vdd
or Vss. When a variation of Vdd or Vss occurs, the current flows through both branches
2 and 3 of the input amplification stage remain constant, because the currents depend
only on the voltage difference &Dgr;V = V1-V2 between the voltages V1 and V2 inputted
into the input amplification stage at lines 9 and 10, respectively. This implies
that the voltage across the load resistor 6 remains constant without requiring a
variation of input voltages V1 or V2 for balancing line variations. In fact, no
systematic error occurs due to line variations, thus maintaining the external PMOS
FET 12 always properly biased.
Still further, the driving circuit 1 fulfills the high
accuracy requirements imposed on regulators for the generation of very low source-drain
For explanation, assume that the two input terminals 9
and 10 are interconnected. In this case, the driving circuit 1 will have a DC output
voltage Vnp at 11 relative to ground. Vnp is denoted by the expression null point.
It is noted, that the existence of a null point unequal to zero is a fundamental
characteristic of the driving circuit 1 and even exists with ideal transistors 4
and 5. In case of ideal transistors 4 and 5, the null point amounts to Vnp=Vdd-R*Ibias/2.
Fig. 2 is a simplified block diagram for explanation of
the null point of an opamp. Analogously, the null point of an opamp is the output
voltage with respect to ground in case that the differential input terminals are
connected. As the ground is usually given by the mean of the operating potentials
(this is also the case for an asymmetric or even unipolar operating voltage), the
null point is the offset of the opamp. The offset of an opamp is usually adjusted
to zero in order to provide for full differential amplification of the input differential
Fig. 3 is a pictorial representation of the output voltage
Vout of the circuit of Fig. 1 at terminal 11 (curve C1) and of an exemplary opamp
(curve C2) versus the differential input voltage Vin=V1-V2. The output voltage Vout
is drawn on the y-axis and the differential input voltage Vin is drawn on the x-axis.
As apparent from fig. 3, curve C1 intersects the y-axis at Vnp different to zero,
whereas the curve C2 intersects the y-axis at zero output voltage. The slopes of
the curves C1 and C2 are given by the open circuit voltage gains of the respective
circuits, which, in this example, are chosen to be equal.
Now, let us assume that the opamp with zero null point
voltage is used in a closed loop system with a negative feedback network. Then,
according to basic control theory, the output voltage of the opamp is given by the
where A denotes the open circuit voltage gain and &bgr; denotes the feedback factor
of the feedback network. Basic control theory always assumes that the null point
is set to zero. Therefore, in order to achieve a certain output voltage different
from zero, a certain amount of voltage between the input terminals of the opamp
is required, and this voltage difference is reflected to the output voltage as a
Fig. 4 is a schematic block diagram of a negative feedback
amplifier control network for the case of a null point output voltage Vnp which
is or may be unequal to zero. A realization of this system is, for example, circuit
1 provided with a negative feedback network between output 11 and input terminal
The input of this circuit is realized by a non-inverting
input of a substracter 13. The amplification stage 14 provides for an open circuit
voltage gain A (corresponding to the amplification of circuit 1). The output of
the amplification stage 14 is connected to an input of an adder 15. The other input
of the adder 15 receives the null point voltage Vnp. The adder 15 output, multiplied
by the feedback factor &bgr; of the feedback network 16, is negatively fed back
to the amplification stage 14 via the inverting input of the substracter 15. Thus,
the system shown in Fig. 4 is a negative feedback amplifier with variable null point.
The output voltage of this negative feedback system becomes
For large values of A, Vout≈Vin/&bgr;. This is
equivalent to the usual case when using an opamp as amplification stage 14 with
zero null point voltage Vnp.
The steady state error at the output of this system is
given by the equation
According to the above equation, in case of Vnp=Vin/&bgr;,
the steady state error Ess becomes zero independent of the open circuit gain A.
On the other hand, as already mentioned, Vin/&bgr;≈Vout
for large values of A. Therefore, by setting the null point Vnp near to the desired
output voltage, the voltage Vin required becomes very small, thereby causing a very
small systematic error at the output.
Therefore, the null point of the circuit 1, namely Vnp
= Vdd-R*(Ibias/2), is set near to the threshold voltage of the external PMOS FET
12. This can be achieved by choosing appropriate values for R and/or Ibias. Then,
the PMOS FET 12 is driven near its threshold value, and the transconductance of
the PMOS FET 12 is very low for low output currents of the FET, where most accuracy