PatentDe  


Dokumentenidentifikation EP1200964 21.06.2007
EP-Veröffentlichungsnummer 0001200964
Titel VERFAHREN UND SCHALTUNG ZUR ZEITLICHEN ANPASSUNG DER STEUERSIGNALE IN EINEM SPEICHERBAUSTEIN
Anmelder Micron Technology, Inc., Boise, Id., US
Erfinder GANS, Dean, Boise, Idahoe 83713, US;
WILFORD, John R., Boise, ID 83713, US;
PAWLOWSKI, Joseph T., Boise, ID 83713, US
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 60034788
Vertragsstaaten AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE
Sprache des Dokument EN
EP-Anmeldetag 20.07.2000
EP-Aktenzeichen 009505652
WO-Anmeldetag 20.07.2000
PCT-Aktenzeichen PCT/US00/19992
WO-Veröffentlichungsnummer 2001008160
WO-Veröffentlichungsdatum 01.02.2001
EP-Offenlegungsdatum 02.05.2002
EP date of grant 09.05.2007
Veröffentlichungstag im Patentblatt 21.06.2007
IPC-Hauptklasse G11C 8/00(2006.01)A, F, I, 20051017, B, H, EP
IPC-Nebenklasse G11C 7/22(2006.01)A, L, I, 20051017, B, H, EP   

Beschreibung[en]
TECHNICAL FIELD

The present invention relates to a control signal timing circuit to be used in in an integrated circuit, to semiconductor memory devices, and more particularly to a method and apparatus for sensing the frequency of a clock signal.

BACKGROUND OF THE INVENTION

Semiconductor memory devices are used in a wide variety of applications. Such memory devices receive data for storage, in what is called a Write operation, and provide stored data to devices external to the memory, in what is called a Read operations. Typically, the memory device is accessed through a bus or multiple bus system by an external device or bus-master, such as a microprocessor, memory controller, or application specific integrated circuit (ASIC). The bus transfers address, data, and control signals between the memory device and the bus-master accessing the memory device.

Many of today's high speed memory devices, such as static random access memories (SRAMs), may operate at speeds greater than the capability of a bus-master accessing the SRAM. In a Read operation, for example, the SRAM may provide the data earlier than a time at which the bus-master is ready to retrieve such data. Bus contention may then result, in which data read from the SRAM is driven onto the bus while other data still resides on the bus. Consequently, two or more devices are sourcing/sinking relatively high currents for some conflicting period of time, thereby increasing risk of latchup effects, increasing system power consumption, increasing power and ground noise, and potentially resulting in erroneous data values.

To avoid such bus contention problems, designers of systems including high speed memories often insert idle time between successive data transfer operations, thereby reducing system speed to significantly less than optimal levels. Additionally, system designers often match speed specifications of various devices included within the system. As such, a system designer may not be able to use a readily available and inexpensive memory device in a system having other components too slow to match the speed of the memory device.

EP-A-0 697 768 discloses a control signal timing circuit as indicated in the preamble of claim 1. It discloses a circuitry for producing a control signal from in input control signal, wherein the duration of the control signal depends on the frequency of a clock signal. A phase locked loop generates a phase control signal and this phase control signal is used for controlling the amount of delay of both a first delay circuit and a second delay circuit. When the phase locked loop is in a stable condition, the pulse width of the clock signal is proportional to the frequency of the control signal.

US-A-5 179 438 discloses a clock sensing circuitry on the basis of a plurality of time delay circuits.

SUMMARY OF THE INVENTION

In accordance with the present invention, a control signal timing circuit to be used in an integrated circuit, such as a memory device, comprises the features of claim 1. The circuit receives a clock signal and performs internal operations including producing a control signal. Clock sensing circuitry receives the clock signal and responsively produces a speed signal having a value corresponding to the frequency of the clock signal. Control signal delay circuitry receives the control signal and the speed signal, and responsively produces a delayed control signal, with the time-delay relative to the control signal corresponding to the speed signal value.

The control signal may be any of a wide variety of control signals produced internal to a memory device and controlling the internal operations thereof. For example, the control signal may be a data output control signal controlling the timing of operations of data output circuitry included within the memory device. As another example, the control signal may be an address select control signal controlling the timing of access to an addressed location within the memory device.

The clock sensing circuitry may include a plurality of series-connected time-delay circuits, each able to receive a signal at its input and produce a corresponding time-delayed signal at its output. The clock signal is received at the input of a first of the time-delay circuits. The clock sensing circuitry may further include a plurality of latching circuits, each coupled with respective one of the time-delay circuits and latching the value of the respective time-delayed signal. The speed signal value may then correspond with the combination of latched values.

The control signal delay circuitry may include a plurality of time-delay circuits, each able to receive a signal at its input and produce a corresponding time-delay signal at its output with the control signal propagating through a selected number of these circuits. The control signal delay circuitry may further include delay select circuitry that receives the speed signal and correspondingly routes the memory control signal through a selected number of the time-delay circuits, with the selected number corresponding to the value of the speed signal.

By sensing the clock frequency and correspondingly adjusting control signal timing within the memory device, the speed of the memory device may be advantageously adjusted to match that of other components within the system. Among a number of advantages achieved in accordance with embodiments of the present invention, an SRAM device may be included within systems having operating speeds that would otherwise be too slow for the high speed access time of the SRAM device.

BRIEF DESCRIPTION OF THE DRAWINGS

  • Figure 1 is a part functional block, part logic circuit diagram depicting a clock sensing circuit in accordance with an embodiment of the present invention.
  • Figure 2 is a logic circuit diagram depicting a delay latch circuit included in the clock sensing circuit of Figure 1.
  • Figure 3 is a functional block circuit diagram depicting a memory device having an adjustable control signal delay circuit in accordance with an embodiment of the present invention.
  • Figure 4 is a part functional block, part logic circuit diagram depicting the control signal delay circuit of Figure 3.
  • Figure 5 is a part functional block, part logic circuit diagram depicting a delay stage circuit included in the control signal delay circuit of Figure 4.
  • Figure 6 is a functional block diagram depicting a computer system having a memory device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The following is a description of a method and apparatus for adjusting control signal timing in a memory device. In this description, certain details are set forth in order to provide a thorough understanding of various embodiments of the present invention. It will be clear to one skilled in the art, however, that the present invention may be practiced without these details. In other instances, well-known circuits, circuit components, and control signals and associated timing protocols have not been shown or described in detail in order to avoid unnecessarily obscuring the description of the various embodiments of the invention.

Figure 1 depicts a clock sensing circuit 10 in accordance with an embodiment of the present invention. The clock sensing circuit 10 receives a clock signal SYSCLK, senses the frequency of the clock signal, and produces a clock speed signal SLOW<0:1> having a value corresponding to the frequency of the clock signal. The clock signal SYSCLK may be a system clock signal, such as that used to control data transfer operations between a memory device and a processor, system controller, or other bus-master.

The clock sensing circuit 10 receives the clock signal SYSCLK at a toggle or divide-by-two circuit 12 that responsively produces a clock signal CLK having one-half the frequency of SYSCLK. The clock signal CLK is then routed through a plurality of series-connected time-delay circuits 14, which may be any of a wide variety of well-known circuits for delaying signal transmission. The time-delay circuits 14 may be of identical construction and may provide substantially the same time delay. Alternatively, the time-delay circuits 14 may vary, both in the particular circuit implementation and in the signal time-delay produced, as desired. One or more of the time-delay circuits 14 may include Reset inputs (not shown) to reset output signal states in response to, for example, a rising edge of the clock signal CLK.

The clock sensing circuit 10 also includes a plurality of delay latch circuits 16, each coupled with a respective one of the time-delay circuits 14. Each of the delay latch circuits 16 receives the delayed clock signal output by the respective one of the time-delay circuits 14 and passes this signal to the input of a next one of the time-delay circuits. Each of the delay latch circuits 16 also receives the undelayed clock signal CLK and its complement CLK , which serve as latching control signals to latch the value of the delayed clock signal output by the respective one of the time-delay circuits 14. The latched value of the delayed clock signal is provided at a latched output of the delay latch circuit 16 as part of a four line delay signal DELAY<0:3>. As desired, the delay latch circuits 16 may also include direct Latch, Reset, and/or Disable inputs and associated internal circuitry (not shown) to directly latch signal values, reset signal values, and/or disable the delay latch circuits independent of the state of the clock signal CLK.

The delayed clock signal propagates through the series of time-delay circuits 14 and respective delay latch circuits 16, with the time delay being progressively greater as determined by the number of time-delay circuits through which the signal propagates. The undelayed clock signal CLK and its complement CLK latch the state of the delayed clock signal in each of the delay latch circuits 16, thereby indicating how far the delayed clock signal has propagated through the series of time-delay circuits 14. Given the contemplated frequencies of the clock signal SYSCLK and the signal propagation delay provided by a first of the time-delay circuits 14, a high state of the delayed clock signal will reach at least a first of the delay latch circuits 16 prior to latching. The delay signal DELAY<0:3> then has four possible values (1000, 1100, 1110, or 1111), depending on how far the delayed clock signal has propagated through the time-delay circuits 14. The delay signal DELAY <0:3> is converted into a two bit clock speed signal SLOW<0:1> in a conventional fashion, such as by employing the particular conversion logic circuitry 18 shown in Figure 1.

As will be described in detail below, each of the delay latch circuits 16 has its delay signal output set to a logic low state (or zero) in response to a rising edge of the clock signal CLK. The clock signal propagates through the series of time-delay circuits 14 and delay latch circuits 16, with each of the delay latch circuits then latching the output signal of the respective time-delay circuit 14 in response to a falling edge of the clock signal CLK. Each of the component signals of the delay signal DELAY<0:3> is high or low depending on whether the delayed high state of the clock signal CLK has reached the corresponding delay latch circuit 16 when the falling edge of the clock signal CLK is applied to the delay latch. Because the clock signal CLK is one-half the frequency of the clock signal SYSCLK, those skilled in the art will appreciate that the signal latched by each of the delay latch circuits 16 indicates whether a first SYSCLK pulse has reached the corresponding delay latch at the time the next sequential SYSCLK pulse occurs. By latching in how far the first system clock pulse has propagated through the time-delay circuits 14, a functional measurement of system clock frequency is achieved, with the produced speed signal SLOW<0:1> having a binary value inversely corresponding to that frequency. The speed signal SLOW<0:1> may then be applied, as described in detail below, to adjust the timing of a variety of control signals used in data access and/or transfer operations.

While Figure 1 shows four time-delay circuits 14 and four associated delay latch circuits 16, those skilled in the art will appreciate that a greater number may be advantageously employed. In a currently preferred embodiment, eight delay latch circuits are used, together with respective time-delay circuits. The correspondingly produced speed signal SLOW is then a three bit signal. By using a larger number of delay latch circuits and time-delay circuits, the functional measurement of clock signal frequency can be performed with greater specificity than in the particular embodiment depicted in Figure 1.

Those skilled in the art will appreciate that the above-described clock sensing circuit 10 essentially compares the pulse-width or period of the clock signal SYSCLK to various time intervals. For example: if the pulse-width is greater than the time delay produced by a first of the time-delay circuits 14, then the respective first of the delay latch circuits 16 latches a logic high state delay signal; if the pulse-width is greater than the time delay produced by the first and a second of the time-delay circuits 14, then the respective first and second of the delay latch circuits 16 each latch a logic high state delay signal; etc.

Figure 2 shows one of many possible implementations of one of the delay latch circuits 16 shown in Figure 1. The depicted delay latch circuit 16 includes a transmit pass gate 22 and a reset pass gate 24. When the clock signal CLK has a logic low state (and hence CLK a logic high state), the transmit pass gate 22 isolates the output from the input, and the reset pass gate 24 pulls the output of the delay latch circuit 16 to a logic low state such as ground potential. When the clock signal CLK has a logic high state (and hence CLK a logic low state), the transmit pass gate 22 passes a signal from the input to the output of the delay latch circuit 16. The delay latch circuit 16 also includes a master-slave latch 26 that responds to the falling edge of the clock signal CLK to latch the state of the output signal as the DELAY signal.

The latch 26 is formed from inverters and pass gates in a conventional configuration. First and second inverters 28, 29 and a first pass gate 30 form a master latch 31. Third and fourth inverters 32, 33 and a second pass gate 34 form a slave latch 35. A third pass gate 36 is coupled between the master latch 31 and the slave latch 35 to selectively connect or isolate the slave latch from the master latch. A fourth pass gate 38 is coupled with the input of the master latch 31 to selectively transmit the output signal of the delay latch circuit 16 to the master latch. When the clock signal CLK has a logic high state, the second pass gate 34 and the fourth pass gate 38 are turned on, while the first pass gate 30 and the third pass gate 36 are off. Thus, the slave latch 35 is isolated from the master latch 31, and the feedback loop of the slave latch is closed, thereby latching its previous state. The feedback loop of the master latch 31 is open and the output of the master latch simply follows the complement of the output signal of the delay latch circuit 16. When the clock signal CLK transitions to a logic low state, the on or off states of the pass gates 30, 34, 36, and 38 switch. The master latch 31 is then disconnected from the output signal produced by the delay latch circuit 16, and the master latch feedback loop is closed, thereby latching the complement of the delay latch circuit output signal immediately prior to the falling edge of the clock signal CLK. This latched signal state is passed by the pass gate 36 to the slave latch 35. The feedback loop of the slave latch 35 is open, and its output correspondingly follows the complement of the signal latched by the master latch 31. Thus, upon the transition of the clock signal CLK from a logic high to a logic low state, the logic state of the DELAY signal takes on a value equal to that of the output signal produced by the delay latch circuit 16 immediately preceding the transition of the clock signal.

Figure 3 depicts one of many possible applications using the speed signal SLOW<0:1> produced by the clock sensing circuit 10 of Figure 1. Figure 3 depicts a memory device 40 that includes a memory cell array 42 and operates in accordance with a plurality of internal control signals produced by a memory control circuit 44. A device external to the memory device 40 applies a plurality of command signals to the memory control circuit 44, including well-known signals such as write-enable (WE), output enable (OE), chip enable (CE). The memory control circuit 44 also receives the system clock signal SYSCLK. Those skilled in the art will understand that each of the depicted control signals may itself represent a plurality of associated control signals, and that additional well-known control signals may be included depending on the particular type of memory device 40 (whether an SRAM, synchronous DRAM, etc.).

An address ADDR is applied to the memory device 40 on an address bus 46. The address ADDR may be a single applied address, as in the case of an SRAM, or maybe a time-multiplexed address, as in the case of a DRAM. In response to one or more control signals provided by the memory control circuit 44, address circuitry 48 decodes the address ADDR, selects corresponding locations within the memory cell array 42, and initiates access to these locations. As is known to those skilled in the art, the depicted address circuitry 48 includes a variety of functional components particular to the memory device type. For example, the address circuitry 48 might include address burst counter and multiplexer circuitry, together with activation and address select circuitry appropriate to the particular memory device type.

In response to one or more control signals provided by the memory control circuit 44, write circuitry 50 writes data to addressed locations within the memory cell array 42. Those skilled in the art know that the depicted write circuitry 50 includes a variety of functional components particular to the memory device type. For example, the write circuitry 50 might include byte enable circuitry and write driver circuitry. In response to one or more control signals provided by the memory control circuit 44, read circuitry 52 retrieves data stored in the address locations within the memory cell array 42. Those skilled in the art know that the depicted read circuitry 52 includes a variety of functional circuit components particular to the memory device type. For example, the read circuitry 52 might include sense amplifier circuitry and I/O gating circuitry.

In response to one or more control signals provided by the memory control circuit 44, data input and data output circuits 54 and 56 are selectively connected to a data bus 58 to input and output data D and Q to and from the memory device 40, all respectively. The data input circuitry 54 receives data from the data bus 58 and provides it to the write circuitry 50 for storage in an addressed location of the memory cell array 42. The data output circuitry 56 receives data retrieved by the read circuitry 52 and provides this data to external devices via the data bus 58. Those skilled in the art know that the depicted data input and out circuits 54 and 56 may include a variety of functional circuit components, such as buffering and register circuitry.

In accordance with an embodiment of the present invention, an adjustable control signal delay circuit 60 is included within the memory device 40. In the particular depiction of Figure 3, the control signal delay circuit 60 couples the memory control circuit 44 with the data output circuit 56. The control signal delay circuit 60 receives the speed signal SLOW<0:1> and adjusts the time delay of the control signal corresponding to the particular value of the speed signal. As one example, the timing of data transfer from the read circuitry 52 to the data output circuitry 56 may be controlled by adjusting the timing of the internally generated data clock signal that clocks read data into the output circuitry. As another example, the control signal delay circuit 60 may selectively adjust the timing of the internally generated output enable signal applied to the data output circuitry 56, to selectively control the timing of the low impedance connection to the data bus 58. Of course, those skilled in the art will appreciate that the control signal delay circuit 60 may be used to adjust timing of a wide variety of control signals within the memory device 40, and not just those associated with the depicted data output circuitry 56.

Figure 4 shows one possible embodiment of the control signal delay circuit 60. A signal input to the control signal delay circuit 60 is output after passing through a pass gate 61 and a selected number of a plurality of time-delay stages 62, with the selected number being determined by the value of the speed signal SLOW<0:1>. Logic circuitry 64 samples the signal state of the various components of the speed signal SLOW<0:1> and applies corresponding delay control and complement signals DELAY n and DELAY n , respectively, to the time-delay stages 62. Each of the time-delay stages 62 also receives the delay control signal applied to the immediately preceding time-delay stage at a delay-n-minus-1 input DELAYnm1. Depending on the states of these signals, and as will be described in detail below, each of the time-delay stages does one of two things: passes an input signal directly to an output OUT to bypass subsequent time-delay stages; or delays the input signal and passes it to a delay output DELAYOUT for provision to the input IN of a next of the time-delay stages 62. Depending on whether the decimal value of the speed signal SLOW<0:1> is 0, 1, 2, or 3, the signal input to the control signal delay circuit 60 will correspondingly be delayed not at all by the pass gate 61 and a first of the time-delay stages 62, be delayed by the first of the time-delay stages, be delayed by the first and a second of the time-delay stages, or be delayed by the first, the second and a third of the time-delay stages.

As discussed in connection with Figure 1, those skilled in the art will appreciate that the frequency of the clock signal SYSCLK may be functionally measured with higher specificity, and the timing of control signals may be correspondingly adjusted. As discussed above, the presently preferred embodiment includes circuitry that provides a three bit speed signal SLOW. Correspondingly, the control signal delay circuit 60 would then include seven time-delay stages instead of the three time-delay stages 62 depicted in Figure 4.

Figure 5 shows one possible implementation of the time-delay stage 62. The delay control and complement signal DELAY n and DELAY n are each applied to an input pass gate 70 and a delay output pass gate 72. A time-delay circuit 74 is coupled between the input pass gate 70 and the delay output pass gate 72. The time-delay circuit 74 may be any of a wide variety of well-known circuits for delaying signal transmission. If the logic state of DELAY n is high (and its complement DELAY n therefore low), the pass gates 70 and 72 are enabled and the signal input to the time-delay stage 62 is routed through the time-delay circuit 74 and provided as a delayed output signal DELAYOUT.

If the logic state of DELAY n is low (and its complement DELAY n therefore high), the pass gates 70, 72 are disabled. Logic circuitry consisting of a NAND gate 78 and an inverter 80 selectively enables or disables an output pass gate 76. If the logic state of DELAYn is low and the logic state of DELAYnm1 is high, the output pass gate 76 is enabled to directly route the signal input to the time-delay stage 62 to an output without a time delay. If the logic state of DELAYn is low and the logic state of DELAYnm1 is low, the pass gate 76 is disabled. To summarize: (i) if DELAYn is high, the signal input to the time-delay state 62 is routed to through the time-delay circuit 74 and provided as a delayed output signal DELAYOUT; (ii) if DELAYn is low and DELAYnm1 is high, the signal input to the time-delay stage is routed (without delay) to the output OUT; (iii) if DELAYn is low and DELAYnm1 is low, no signal path through the time-delay stage exists, with the time-delay stage, then being bypassed as described above in connection with Figure 4.

Figure 6 is a functional block diagram depicting a computer system 90 which includes a memory device 100 constructed in accordance with the present invention. For example, the memory device 100 could be of configuration similar to the memory device 40 and equivalents described above in connection with Figure 3. The computer system 90 includes computer circuitry 92 for performing such functions as executing software to accomplish desired calculations and tasks. The computer circuitry 92 includes at least one processor (not shown) and the memory device 100, as shown. A data input device 94 is coupled to the computer circuitry 92 to allow an operator to manually input data thereto. Examples of data input devices 94 include a keyboard and a pointing device. A data output device 96 is coupled to the computer circuitry 92 to provide data generated by the computer circuitry to the operator. Examples of data output devices 96 include a printer and a video display unit. A data storage device 98 is coupled to the computer circuitry 92 to store data and/or retrieve data from external storage media. Examples of storage devices 98 and associated storage media include drives that accept hard and floppy disks, magnetic tape recorders, and compact-disc read-only memory (CD-ROM) drives.

It will be appreciated that, although specific embodiments of the present invention have been described above for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. As just one example, a number of alternative circuit implementations may be functionally substituted for the particularly described delay latch circuits 16 and time-delay stages 62. Indeed, those skilled in the art will understand that a number of suitable circuits. can be adapted and combined to implement selective adjustment of control signal timing in a memory device or other integrated circuit. Accordingly, the invention is not limited by the disclosed embodiments, but instead the scope of the invention is determined by the following claims.


Anspruch[de]
Steuersignal-Zeitgeberschaltung, ausgebildet zur Verwendung in einer integrierten Schaltung, die dazu dient, ein Taktsignal zu empfangen und interne Operationen einschließlich der Erzeugung eines Steuersignals (IN) auszuführen, wobei die Steuersignal-Zeitgeberschaltung aufweist: eine Taktleseschaltung (14, 16, 18), betreibbar zum Empfangen des Taktsignals (CLK) und ansprechend darauf zum Erzeugen eines Geschwindigkeitssignals (SLOW <0:1>) entsprechend der Frequenz des Taktsignals, und eine Steuersignal-Verzögerungsschaltung (60), betreibbar zum Empfangen des Steuersignals (IN) und des Geschwindigkeitssignals (SLOW <0:1>), wobei die Steuersignal-Verzögerungsschaltung darauf ansprechend ein verzögertes Steuersignal (OUT) erzeugt, welches gegenüber dem Steuersignal um einen Zeitverzögerungswert zeitlich verzögert ist, welcher dem Geschwindigkeitssignalwert (SLOW <0:1>) entspricht, wobei die Taktleseschaltung aufweist: eine Mehrzahl von in Reihe geschalteten Zeitverzögerungsschaltungen (14), jeweils betreibbar zum Empfangen eines Signals an ihrem Eingang und zum Erzeugen eines entsprechenden, zeitlich verzögerten Signals an ihrem Ausgang, wobei das Taktsignal (CLK) am Eingang einer ersten der Zeitverzögerungsschaltungen empfangen wird und sequenziell durch die mehreren in Reihe geschalteten Zeitverzögerungsschaltungen gekoppelt wird; dadurch gekennzeichnet, dass das Geschwindigkeitssignal (SLOW <0:1>) eine Mehrzahl von Bits umfasst, und dass eine Mehrzahl von Zwischenspeicherschaltungen (16) vorgesehen ist, jeweils mit einer zugehörigen der Zeitverzögerungsschaltungen gekoppelt und betreibbar zum Zwischenspeichern eines Werts (DELAY <0:3>) des zugehörigen zeitlich verzögerten Signals, wobei die mehreren Zwischenspeicherschaltungen die betreffenden Werte der zeitlich verzögerten Signale ansprechend auf eine Flanke des Taktsignals (CLK) zwischenspeichern, so dass die Anzahl von Zeitverzögerungsschaltungen (14), durch die das Taktsignal (CLK) sequentiell gekoppelt wurde, dann, wenn die Werte der jeweiligen zeitlich verzögerten Signale von den Zwischenspeicherschaltungen zwischengespeichert sind, der Frequenz des Taktsignals (CLK) entspricht, die Werte (DELAY <0:3>) der zeitlich verzögerten Signale, die von den Zwischenspeicherschaltungen zwischengespeichert wurden, als der Geschwindigkeitssignalwert (SLOW <0:1>) ausgegeben werden. Schaltung nach Anspruch 1, bei der das Taktsignal in die erste der Zeitverzögerungsschaltungen ansprechend auf eine erste Flanke des Taktsignals (CLK) eingegeben wird, wobei jede der Zwischenspeicherschaltungen den betreffenden zeitlich verzögerten Signalwert ansprechend auf eine zweite Flanke des Taktsignals (CLK) zwischenspeichert, wobei die zweite Flanke sich von der ersten Flanke unterscheidet. Schaltung nach Anspruch 1, bei der die Steuersignal-Verzögerungsschaltung (60) aufweist: eine Mehrzahl von Zeitverzögerungsschaltungen (62), jeweils betreibbar zum Empfangen eines Signals an ihrem Eingang und zum Erzeugen eines entsprechenden, zeitlich verzögerten Signals an ihrem Ausgang; und eine Verzögerungsauswahlschaltung (64), betreibbar zum Empfangen des Geschwindigkeitssignals und zum Leiten des Steuersignals durch eine ausgewählte Anzahl der Zeitverzögerungsschaltungen, wobei die ausgewählte Anzahl dem Wert des Geschwindigkeitssignals entspricht. Speicherbauelement, betreibbar zum Transferieren von Daten von einem bezüglich des Speicherbauelements externen Gerät und umgekehrt, wobei das Speicherbauelement ein Taktsignal empfängt, welches die zeitliche Lage der Datentransferoperationen steuert, und das Speicherbauelement aufweist: ein Speicherarray (42), betreibbar zum Speichern von Daten; eine Dateneingangsschaltung (54), betreibbar zum Empfangen von Daten von dem externen Gerät; eine Datenausgangsschaltung (56), betreibbar zum Liefern von Daten an das externe Gerät; eine Array-Zugriffsschaltung (50, 52), die mit dem Speicherarray und mit dem Dateneingangs- und -ausgangsschaltungen gekoppelt ist, wobei die Array-Zugriffsschaltung betreibbar ist, um Daten von der Dateneingangsschaltung zu dem Speicherarray zwecks dortiger Speicherung zu transferieren, und die Array-Zugriffsschaltung weiterhin betreibbar ist zum Transferieren von in dem Speicherarray gespeicherten Daten zu der Datenausgangsschaltung; eine Speichersteuerschaltung (44), betreibbar zum Erzeugen einer Mehrzahl von Steuersignalen, von denen jedes an eine der Array-Zugriffsschaltungen, Dateneingangsschaltungen und Datenausgangsschaltungen anlegbar ist, um deren Betrieb zu steuern; und eine Steuersignal-Zeitgeberschaltung nach einem der Ansprüche 1 bis 3, wobei die Steuersignal-Verzögerungsschaltung (60) zwischen der Speichersteuerschaltung (44) und eine von den Array-Zugriffsschaltungen (50, 52), der Dateneingangsschaltung (54) und der Datenausgangsschaltung (56) gekoppelt ist, die Steuersignal-Verzögerungsschaltung betreibbar ist zum Empfangen des Geschwindigkeitssignals (SLOW <0:1 >) und - ansprechend darauf - zum Verzögern eines der Steuersignale, die an eine der Array-Zugriffsschaltungen, der Dateneingangsschaltung und der Datenausgangsschaltung gelegt wird. Speicherbauelement nach Anspruch 4, bei dem die Array-Zugriffsschaltung aufweist: eine Adressenschaltung, betreibbar zum Empfangen einer Adresse, um ansprechend darauf einen Zugriff zu einer entsprechenden Stelle innerhalb des Speicherarrays einzuleiten; eine Schreibschaltung zum Transferieren der Daten von der Dateneingangsschaltung zu der Zugriffsstelle innerhalb des Speicherarrays; und eine Leseschaltung zum Transferieren der in der Zugriffsstelle gespeicherten Daten innerhalb des Speicherarrays zu der Datenausgangsschaltung. Speicherbauelement nach Anspruch 4, bei dem eine von den Speicherarray-Dateneingangs- und Datenausgangsschaltungen die Datenausgangsschaltung ist, wobei das eine von den Steuersignalen ein Datenausgabe-Steuersignal ist. Speicherbauelement nach Anspruch 6, bei dem das Datenausgabe-Steuersignal ein Datentaktsignal zum Takten von in dem Speicherarray gespeicherten Daten in die Datenausgabeschaltung ist. Speicherbauelement nach Anspruch 6, bei dem das Datenausgabe-Steuersignal ein Ausgabe-Freigabesignal ist, und das die Datenausgangsschaltung ansprechend darauf eine Verbindung niedriger Impedanz zu dem externen Gerät schafft. Computersystem, umfassend: ein Dateneingabegerät; ein Datenausgabegerät; und eine Computerschaltung, die mit den Dateneingabe- und Datenausgabegeräten gekoppelt ist und ein Speicherbauelement nach einem der Ansprüche 4 bis 8 enthält. Computersystem nach Anspruch 9, weiterhin umfassend ein Datenspeicherbauelement, welches mit der Computerschaltung gekoppelt ist. Verfahren zum Lesen der Frequenz eines Taktsignals, umfassend folgende Schritte: Vergleichen der Periodendauer des Taktsignals (CLK) mit einer Mehrzahl von Zeitintervallen (14); für jedes der Zeitintervalle (14), welches die Periodendauer des Taktsignals überschreitet, Erstellen eines aus einer Mehrzahl von Intervall-Kennzeichnungssignalen (DELAY <0:3>); und Erzeugen eines Taktgeschwindigkeitssignals (SLOW <0:1>) mit einem Wert entsprechend der Kombination der Intervallkennzeichnungssignale. Verfahren nach Anspruch 11, bei dem der Schritt des Vergleichens der Periodendauer des Taktsignals mit einer Mehrzahl von Zeitintervallen folgende Schritte beinhaltet: Durchleiten des Taktsignals durch eine Reihe von Zeitverzögerungsschaltungen; und Bestimmen der Anzahl von Zeitverzögerungsschaltungen, durch die das Taktsignal innerhalb eines gegebenen Zeitintervalls gelaufen ist. Verfahren nach Anspruch 11, bei dem der Schritt des Erzeugens des Taktgeschwindigkeitssignals den Schritt des Erzeugens eines Mehrfachbitsignals beinhaltet, von dem jedes Bit einen Wert hat, der einem der Intervallkennzeichnungssignalvverte entspricht.
Anspruch[en]
A control signal timing circuit adapted to be used in an integrated circuit adapted to receive a clock signal and to perform internal operations including producing a control signal (IN), said control signal timing circuit comprising: clock sensing circuitry (14, 16, 18) operable to receive the clock signal (CLK) and to responsively produce a speed signal (SLOW<0:1>) corresponding to the frequency of the clock signal (CLK) and control signal delay circuitry (60) operable to receive the control signal (IN) and the speed signal (SLOW<0:1>), the control signal delay circuitry responsively producing a delayed control signal (OUT) that is time-delayed relative to the control signal by a time-delay value corresponding to the speed signal value (SLOW<0:1>), the clock sensing circuitry comprising: a plurality of series-connected time-delay circuits (14), each operable to receive a signal at its input and produce a corresponding time-delayed signal at its output, the clock signal (CLK) being received at the input of a first of the time-delay circuits and being sequentially coupled through the plurality of series-connected time-delay circuits; characterized in that the speed signal (SLOW<0:1>) has a plurality of bits and that a plurality of latching circuits (16) is provided each coupled with a respective one of the time-delay circuits and operable to latch a value (DELAY<0:3>) of the respective time-delayed signal, the plurality of latching circuits latching the respective values of the time-delayed signals in response to an edge of the clock signal (CLK) so that the number of time-delay circuit (14) through which the clock signal (CLK) has been sequentially coupled when the values of the respective time-delayed signals are latched by the latching circuits corresponds to the frequency of the clock signal (CLK), the values (DELAY<0:3>) of the time-delayed signals latched by the latching circuits being output as the speed signal value (SLOW <0:1>). The circuit according to claim 1 wherein the clock signal is input to the first of the time-delay circuits in response to a first edge of the clock signal (CLK), and wherein each of the latching circuits latches the respective time-delayed signal value in response to a second edge of the clock signal (CLK), the second edge being different from the first edge. The circuit according to claim 1 wherein the control signal delay circuitry (60) comprises: a plurality of time-delay circuits (62), each operable to receive a signal at its input and produce a corresponding time-delayed signal at its output; and delay select circuitry (64) operable to receive the speed signal and to route the control signal through a selected number of the time-delay circuits, the selected number corresponding to the value of the speed signal. A memory device operable to transfer data to and from a device external to the memory device, the memory device receiving a clock signal controlling timing of data transfer operations, the memory device comprising: a memory array (42) operable to store data; a data input circuit (54) operable to receive data from the external device; a data output circuit (56) operable to provide data to the external device; an array access circuit (50, 52) coupled with the memory array and with the data input and output circuits, the array access circuit operable to transfer data from the data input circuit to the memory array for storage therein, the array access circuit further operable to transfer data stored in the memory array to the data output circuit; a memory control circuit (44) operable to produce a plurality of control signals, each applied to a corresponding one of the array access, data input, and data output circuits to control operation thereof; and a control signal timing circuit according to any of claims 1-3 wherein said control signal delay circuitry (60) is coupled between the memory control circuit (44) and one of the array access (50, 52) data input (54), and data output (56) circuits, the control signal delay circuitry operable to receive the speed signal (SLOW<0:1>) and to responsively delay one of the control signals applied to the one of the array access, data input, and data output circuits. A memory device according to claim 4 wherein the array access circuit comprises: an address circuit operable to receive an address and responsively initiate access to a corresponding location within the memory array; a write circuit for transferring the data from the data input circuit to the accessed location within the memory array; and a read circuit for transferring the data stored in the accessed location within the memory array to the data output circuit. A memory device according to claim 4 wherein the one of the array access, data input, and data output circuits is the data output circuit, and wherein the one of the control signals is a data output control signal. A memory device according to claim 6 wherein the data output control signal is a data clock signal for clocking data stored in the memory array into the data output circuitry. A memory device according to claim 6 wherein the data output control signal is an output enable signal, the data output circuitry responsively providing a low impedance connection to the external device. A computer system, comprising: a data input device; a data output device; and computer circuitry coupled with the data input and data output devices and including a memory device according to any of claims 4 to 8. A computer system according to claim 9, further comprising a data storage device coupled with the computer circuitry. A method of sensing the frequency of a clock signal, comprising the steps of: comparing the period of the clock signal (CLK) to a plurality of time intervals (14); for each of the time intervals (14) that the period of the clock signal exceeds, producing a respective one of a plurality of interval indicating signals (DELAY<0:3>); and producing a clock speed signal (SLOW<0:1>) having value corresponding with the combination of interval indicating signals. A method according to claim 11 wherein the step of comparing the period of the clock signal to a plurality of time intervals includes the steps of: propagating the clock signal through a series of time-delay circuits; and determining a number of the time-delay circuits through which the clock signal has propagated in a given time interval. A method according to claim 11 wherein the step of producing the clock speed signal includes the step of producing a multi-bit signal, each bit having a value corresponding with a respective one of the interval indicating signal values.
Anspruch[fr]
Circuit de synchronisation de signal de contrôle apte à être utilisé dans un circuit intégré étudié pour recevoir un signal d'horloge et à effectuer des opérations internes comprenant la production d'un signal de contrôle (IN), ledit circuit de synchronisation de signal de contrôle comprenant : une circuiterie de détection d'horloge (14, 16, 18) pouvant fonctionner pour recevoir le signal d'horloge (CLK) et pour produire en réponse un signal de vitesse (SLOW <0 : 1 >) correspondant à la fréquence du signal d'horloge (CLK) et une circuiterie de retard de signal de contrôle (60) pouvant fonctionner pour recevoir le signal de contrôle (IN) et le signal de vitesse (SLOW <0 : 1>), la circuiterie de retard de signal de contrôle produisant en réponse un signal de contrôle retardé (OUT) qui est retardé dans le temps par rapport au signal de contrôle par une valeur de retard de temps correspondant à la valeur de signal de vitesse (SLOW <0: 1>), la circuiterie de détection d'horloge comprenant : une pluralité de circuits de retard de temps connectés en série (14), chacun pouvant fonctionner pour recevoir un signal au niveau de son entrée et pour produire un signal retardé dans le temps correspondant au niveau de sa sortie, le signal d'horloge (CLK) étant reçu à l'entrée d'un premier des circuits de retard de temps et étant couplé de manière séquentielle par la pluralité de circuits de retard de temps connectés en série ; caractérisé en ce que le signal de vitesse (SLOW <0 : 1>) comporte une pluralité de bits et en ce qu'une pluralité de circuits de verrouillage (1b) est prévue, chacun couplé avec un, respectif, des circuits de retard de temps et pouvant fonctionner pour verrouiller une valeur (DELAY <0 : 3>) du signal retardé dans le temps respectif, la pluralité de circuits de verrouillage verrouillant les valeurs respectives des signaux retardés dans le temps en réponse à un bord du signal d'horloge (CLK) de telle sorte que le nombre de circuits de retard de temps (14) à travers lesquels le signal d'horloge (CLK) a été couplé de manière séquentielle lorsque les valeurs des signaux retardés dans le temps respectifs sont verrouillées par les circuits de verrouillage correspond à la fréquence du signal d'horloge (CLK), les valeurs (DELAY <0 : 3>) des signaux retardés dans le temps verrouillés par les circuits de verrouillage étant sorties comme la valeur de signal de vitesse (SLOW <0 : 1>). Circuit selon la revendication 1 dans lequel le signal d'horloge est entré vers le premier des circuits de retard de temps en réponse à un premier bord du signal d'horloge (CLK) et dans lequel chacun des circuits de verrouillage verrouille la valeur de signal retardé dans le temps respectif en réponse à un deuxième bord du signal d'horloge (CLK), le deuxième bord étant différent du premier bord. Circuit selon la revendication 1 dans lequel la circuiterie de retard de signal de contrôle (60) comprend : une pluralité de circuits de retard de temps (62), chacun pouvant fonctionner pour recevoir un signal au niveau de son entrée et produire un signal retardé dans le temps correspondant au niveau de sa sortie ; et une circuiterie de sélection de retard (64) pouvant fonctionner pour recevoir le signal de vitesse et pour router le signal de contrôle à travers un nombre sélectionné de circuits de retard de temps, le nombre sélectionné correspondant à la valeur du signal de vitesse. Dispositif de mémoire pouvant fonctionner pour transférer des données vers et depuis un dispositif externe au dispositif de mémoire, le dispositif de mémoire recevant un signal d'horloge contrôlant la synchronisation d'opérations de transfert de données, le dispositif de mémoire comprenant : un réseau de mémoire (42) pouvant fonctionner pour stocker des données ; un circuit d'entrée de données (54) pouvant fonctionner pour recevoir des données du dispositif externe ; un circuit de sortie de données (56) pouvant fonctionner pour produire des données vers le dispositif externe ; un circuit d'accès au réseau (50, 52) couplé avec le réseau de mémoire et avec les circuits d'entrée et de sortie de données, le circuit d'accès au réseau pouvant fonctionner pour transférer les données depuis le circuit d'entrée de données vers le réseau de mémoire pour un stockage dans celui-ci, le circuit d'accès au réseau pouvant en outre fonctionner pour transférer des données stockées dans le réseau de mémoire vers le circuit de sortie de données ; un circuit de contrôle de mémoire (44) pouvant fonctionner pour produire une pluralité de signaux de contrôle, chacun appliqué à un, correspondant, des circuits d'accès au réseau, d'entrée de données et de sortie de données pour contrôler 1 fonctionnement de celui-ci ; et une circuiterie de synchronisation de signal de contrôle selon l'une quelconque des revendications 1-3 dans lequel ladite circuiterie de retard de signal de contrôle (60) est couplée entre le circuit de contrôle de mémoire (44) et un des circuits d'accès au réseau (50, 52), d'entrée de données (54) et de sortie de données (56), la circuiterie de retard de signal de contrôle pouvant fonctionner pour recevoir le signal de vitesse (SLOW <0 : 1>) et pour retarder en réponse un des signaux de contrôle appliqués à un des circuits d'accès au réseau, d'entrée de données et de sortie de données. Dispositif de mémoire selon la revendication 4 dans lequel le circuit d'accès au réseau comprend : un circuit d'adresse pouvant fonctionner pour recevoir une adresse et initier en réponse un accès à un emplacement correspondant à l'intérieur du réseau de mémoire ; un circuit d'écriture pour transférer les données depuis le circuit d'entrée de données vers l'emplacement accédé à l'intérieur du réseau de mémoire ; et un circuit de lecture pour transférer les données stockées dans l'emplacement accédé à l'intérieur du réseau de mémoire vers le circuit de sortie de données. Dispositif de mémoire selon la revendication 4 dans lequel l'un des circuits d'accès au réseau, d'entrée de donnés et de sortie de données est le circuit de sortie de données et dans lequel l'un des signaux de contrôle est un signal de contrôle de sortie de données. Dispositif de mémoire selon la revendication 6 dans lequel le signal de contrôle de sortie de données est un signal d'horloge de données pour fournir une horloge des données stockées dans le réseau de mémoire dans la circuiterie de sortie de données. Dispositif de mémoire selon la revendication 6 dans lequel le signal de contrôle de sortie de données est un signal d'activation de sortie, la circuiterie de sortie de données produisant en réponse une connexion à impédance faible au dispositif externe. Système informatique, comprenant : un dispositif d'entrée de données ; un dispositif de sortie de données ; et une circuiterie informatique couplée avec les dispositifs d'entrée de données et de sortie de données et comprenant un dispositif de mémoire selon l'une quelconque des revendications 4 à 8. Système informatique selon la revendication 9, comprenant en outre un dispositif de stockage de données couplé avec la circuiterie informatique. Procédé de détection de la fréquence d'un signal d'horloge, comprenant les étapes consistant à ;

comparer la période du signal d'horloge (CLK) à une pluralité d'intervalles de temps (14) ;

pour chacun des intervalles de temps (14) que la période du signal d'horloge dépasse, produire un, respectif, d'une pluralité de signaux indiquant l'intervalle (DELAY <0 : 3>); et

produire un signal de vitesse d'horloge (SLOW <0 : 1>) ayant une valeur correspondante avec la combinaison de signaux indiquant l'intervalle.
Procédé selon la revendication 11 dans lequel l'étape de comparaison de la période du signal d'horloge à une pluralité d'intervalles de temps comprend les tapes consistant à ;

propager le signal d'horloge à travers une série de circuits de retard de temps ; et

déterminer un nombre de circuits de retard de temps à travers lesquels le signal d'horloge s'est propagé dans un intervalle de temps donné.
Procédé selon la revendication 11 dans lequel l'étape de production du signal de vitesse d'horloge comprend l'étape consistant à produire un signal à bits multiples, chaque bit ayant une valeur correspondant avec une, respective, des valeurs de signaux indiquant l'intervalle.






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