PatentDe  


Dokumentenidentifikation EP1246200 09.08.2007
EP-Veröffentlichungsnummer 0001246200
Titel Halbleiterspeicheranordnung
Anmelder Fujitsu Ltd., Kawasaki, Kanagawa, JP
Erfinder Yagishita, Yoshimasa, Kawaski-shi, Kanagawa 211-8588, JP;
Uchida, Toshiya, Kawaski-shi, Kanagawa 211-8588, JP
Vertreter W. Seeger und Kollegen, 81369 München
DE-Aktenzeichen 60129104
Vertragsstaaten DE, FR, GB
Sprache des Dokument EN
EP-Anmeldetag 05.12.2001
EP-Aktenzeichen 013102017
EP-Offenlegungsdatum 02.10.2002
EP date of grant 27.06.2007
Veröffentlichungstag im Patentblatt 09.08.2007
IPC-Hauptklasse G11C 29/00(2006.01)A, F, I, 20070529, B, H, EP

Beschreibung[en]
BACKGROUND OF THE INVENTION (1) Field of the Invention

This invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a shift redundancy function.

(2) Description of the Related Art

If there is a defective line in a semiconductor memory device manufactured, it can be returned to normal by substituting other lines including a redundant line for the defective line by the use of a technique called shift redundancy.

Fig. 9 is a view for giving an overview of shift redundancy. In Fig. 9, a memory array 2 includes an ordinary line 2a and redundant line 2b. How to connect them is managed by a decoder 1.

As shown in Fig. 10, it is assumed that a defective line is detected in the middle area of this semiconductor memory device. Then the decoder 1 can substitute other lines including the redundant line for the defective line by shifting all of the lines being on the right-hand side of the defective line to the right.

Fig. 11 is a circuit diagram for realizing this shift redundancy. In Fig. 11, an address latch circuit 20 latches an address signal input from the outside and provides it to a decoding circuit 21.

The decoding circuit 21 decodes an address signal latched by the address latch circuit 20, generates a selection signal for selecting a predetermined line in a memory array, and provides it to a word driver circuit 22.

The word driver circuit 22 drives the memory array in compliance with a selection signal supplied from the decoding circuit 21.

A fuse circuit 23 includes fuses the number of which corresponds to that of word lines in the memory array. If tests run after manufacture show that a predetermined word line in the memory array is defective, information showing the defective line will be stored by blowing fuses corresponding to the position (address) of the defective line by the use of an external unit.

A decoding circuit 24 decodes information showing a defective line held in the fuse circuit 23, generates an indicating signal that indicates the defective line from among word lines, and provides it to a redundant circuit 25.

The redundant circuit 25 controls the word driver circuit 22 in compliance with an indicating signal and substitutes other lines including a redundant line for a defective line.

Operation in the above known semiconductor memory device will now be described.

If tests run after manufacture show that a predetermined word line in the memory array is defective, a fuse in the fuse circuit 23 corresponding to the defective line will be blown.

It is assumed that a semiconductor memory device in which fuses corresponding to a defective line have been blown in this way is mounted in a predetermined circuit and that power is applied to it. First, the fuse circuit 23 generates a signal corresponding to how fuses are blown (address signal showing the defective line) and provides it to the decoding circuit 24.

The decoding circuit 24 decodes the signal supplied from the fuse circuit 23, generates an indicating signal, and provides it to the redundant circuit 25.

The redundant circuit 25 refers to the indicating signal supplied from the decoding circuit 24, shifts word lines by controlling the word driver circuit 22, and substitutes other lines including a redundant line for the defective line (see Fig. 10).

When the shift redundancy is completed, the semiconductor memory device begins to accept an address signal and the address latch circuit 20 latches an address signal input.

The decoding circuit 21 decodes the address signal latched by the address latch circuit 20, generates a selection signal, and provides it to the word driver circuit 22.

The word driver circuit 22 has performed shift redundancy on the basis of instructions from the redundant circuit 25, so the word driver circuit 22 properly shifts the selection signal supplied from the decoding circuit 21 and provides it to the memory array. This can exclude the defective line from lines to be accessed and substitute the redundant line for the defective line.

Fig. 12 is a view for giving an overview of a circuit pattern formed in the case of the circuit shown in Fig. 11 being mounted on a semiconductor substrate. In this example, the decoding circuit and fuse circuit are located along a side of the memory array. Hatched areas in the decoding circuit are the redundant circuits. Each of the right and left halves of the memory array is a redundancy unit. If a defective line exists in each unit, the operation in each unit of substituting a redundant line for a defective line will be performed independently.

As stated above, if there is a one-to-one relationship between a memory array on which shift redundancy is performed and a fuse circuit, the only thing to do is to newly add a block corresponding to a redundant line. Shift redundancy therefore can be realized easily.

As shown in Fig. 11, to realize shift redundancy, selection wirings for shift redundancy must be formed separately from ordinary selection wirings. There are many wirings especially after the decoding circuit 21 and redundant circuit 25, so wiring penalties, problems in accommodating the wires, can arise depending on a circuit layout.

Furthermore, as shown in Fig. 13, with a semiconductor memory device, such as a fast cycle random access memory (FCRAM), consisting of a plurality of subblocks, there is a technique in which the plurality of subblocks share a fuse. In this case, "subblock" is a memory array unit including one redundant line. In this example, hatched areas are redundant circuits, so there are two subblocks in the horizontal and vertical directions respectively. That is to say, this semiconductor memory device consists of a total of 4 (=2x2) subblocks.

In this example, two subblocks located in the vertical direction share one fuse circuit. Therefore, as shown in Fig. 14, if there is a defective line in one of the two subblocks located in the vertical direction, shift redundancy is performed on both of them. In this example, the fourth line from the left and the rightmost line are defective ones. The leftmost redundant lines in the left and right subblocks are substituted for these defective lines.

If a plurality of subblocks located in the vertical direction share the same fuse circuit in this way, a decoding circuit in each subblock and the fuse circuit must be connected with a wiring. Therefore, as shown in Figs. 13 and 14, some of these wirings must pass over a subblock, resulting in a stronger probability of the penalties of wirings arising and difficulty in a decoder layout.

With a memory layout of a spread type, memory arrays located in the vertical direction can share a fuse circuit. In this case, there is no need to locate lines over a memory array. However, this technique is not applicable to cases where more than two memory arrays exist.

Patent Abstract of Japan Vol 2000 No 19 (2001-06-05) and JP 2001 052 496A discloses a semiconductor memory. This device is provided with a memory cell array provided with word lines of n+1 (n: positive integer) lines, a register section holding an encoded defective address specifying a defective word line, a defective address decoder decoding the defective address from the register section and specifying the defective word line, selecting means S1-Sn selecting either of the (i)th word line or (i+1)th word line for an (i)th (1≤i≤n) output signal line of a row decoder and connecting it, and control means C1-Cn controlling each selecting means Sl-Sn so that the word lines excluding the defective word lines are selected conforming to the order of arrangement for an output of the row decoder based on the output of the defective address decoder.

Patent Abstract of Japan Vol 2000, No 10, 17 (2000-11-17) and JP 2000 187 620A describes a semiconductor memory device. The defective address (the address of the defective memory cell) of a main memory is fetched in a register, and an address appearing in an address bus is compared with an address stored in the register by a comparator, and when they are made coincident, switch parts are switched according to the output of the comparator, and the address of a preliminary memory address outputting part is supplied to the driver of the main memory and the driver of a preliminary memory. At that time, the driver of the main memory is turned into an operation inhibiting state, and the driver of the preliminary memory is turned into an operation enabling state (enable) by a common control line. Thus, the destination of access is switched from the main memory to the preliminary memory according to the output of the defective address.

US-A-5446692 wherein the preamble of claim 1 is based describes an SRAM including a plurality of memory blocks each having a redundancy memory cell to be shared. In redundancy row decoders provided in each memory block, a memory block to be remedied is programmed. Accordingly, a redundancy memory cell row corresponding to each redundancy row decoder can be used for remedy of a defect memory cell in another memory block.

The present invention is defined in the attached independent claim to which reference should now be made. Further, preferred features my be found in the sub-claims appended thereto.

In order to address such problems, the present invention was made. Embodiments of the present invention aim to reduce the probability of the penalties of wirings arising and to make the arrangements of decoders easy, especially in a semiconductor memory device having a plurality of subblocks.

Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which:

  • Fig. 1 is a view for describing the operative principles of the present invention.
  • Fig. 2 is a view showing the structure of a first embodiment of the present invention.
  • Fig. 3 is a view for describing operation in the first embodiment shown in Fig. 2.
  • Fig. 4 is a view for describing operation in the first embodiment shown in Fig. 2.
  • Fig. 5 is a view showing the structure of a second embodiment of the present invention.
  • Fig. 6 is a view for describing operation in the second embodiment shown in Fig. 5.
  • Fig. 7 is a view showing the structure of a third embodiment of the present invention.
  • Fig. 8 is a view showing the detailed structure of an area enclosed with a dashed line in Fig. 7.
  • Fig. 9 is a view for giving an overview of known shift redundancy.
  • Fig. 10 is a view for giving an overview of known shift redundancy.
  • Fig. 11 is a view showing the structure of a known semiconductor memory device.
  • Fig. 12 is a view for giving an overview of a circuit pattern formed in the case of the circuit shown in Fig. 11 being mounted on a semiconductor substrate.
  • Fig. 13 is a view for describing an example of shift redundancy in a semiconductor memory device consisting a plurality of subblocks.
  • Fig. 14 is a view for describing an example of shift redundancy in a semiconductor memory device consisting a plurality of subblocks.

Fig. 1 is a view for describing the operative principles of the present invention. As shown in Fig. 1, a semiconductor memory device according to the present invention comprises an address input circuit 30, a drive circuit 31, a signal line 32, a redundant circuit 33, a defective line information store circuit 34, a supply circuit 35, and a memory array 36.

The address input circuit 30 receives an address signal input from the outside and provides it to the drive circuit 31 via the signal line 32.

The drive circuit 31 drives the memory array 36 in compliance with an address signal supplied via the signal line 32.

The signal line 32 electrically connects the address input circuit 30 and drive circuit 31 to transmit an address signal.

The redundant circuit 33 is located near the drive circuit 31 and performs the process of substituting other lines including a redundant line for a defective line in the memory array 36.

The defective line information store circuit 34 stores information showing a defective line in the memory array 36.

The supply circuit 35 supplies information showing a defective line, which is stored in the defective line information store circuit 34, to the redundant circuit 33 via the signal line 32.

Now, operation in Fig. 1 will be described.

If tests show that there exists a defective line in the memory array 36, information for specifying the defective line is stored in the defective line information store circuit 34 by another device. The defective line information store circuit 34 has a plurality of fuses. Information regarding the defective line is stored by blowing a fuse corresponding to the position of the defective line.

It is assumed that information showing a defective line is stored in the defective line information store circuit 34 in this way and that the semiconductor memory device is mounted in a predetermined circuit.

In this state of things, it is assumed that power is applied to that circuit. Then the supply circuit 35 in the semiconductor memory device reads information regarding the defective line from the defective line information store circuit 34 and provides it to the redundant circuit 33 via the signal line 32. At this time, the operation of the address input circuit 30 will be stopped and the inputting of an address signal will be stopped.

The redundant circuit 33 performs the process of substituting other lines including a redundant line for the defective line in the memory array 36 on the basis of the information supplied via the signal line 32.

Moreover, the redundant circuit 33 has a memory circuit therein and can store information regarding a defective line. Therefore, after the information is supplied from the supply circuit 35, the redundant circuit 33 can perform the redundant process continuously on the basis of the information it stored.

When the redundant process is completed, the address input circuit 30 will begin to receive an address signal input from the outside. An address signal input from the address input circuit 30 is provided to the drive circuit 31 via the signal line 32.

The drive circuit 31 drives the memory array 36 on the basis of the address signal supplied via the signal line 32. Shift redundancy has been completed then by the redundant circuit 33, so the defective line will be excluded from lines to be accessed.

As described above, in the present invention, information regarding a defective line is supplied from the defective line information store circuit 34 to the redundant circuit 33 at the time of a semiconductor memory device being started by the use of the signal line 32 for supplying an address signal to the drive circuit 31. This enables a reduction in the number of wirings and the probability of the penalties of wirings arising in comparison to known semiconductor memory devices.

Furthermore, at the time of a semiconductor memory device being started, information is supplied from the defective line information store circuit 34 to the redundant circuit 33 and is stored there. Therefore, it is enough just to provide information to the redundant circuit 33 once after a semiconductor memory device being started. This will lead to simple operation of a semiconductor memory device.

Fig. 2 is a view showing the structure of an embodiment of the present invention. As shown in Fig. 2, a semiconductor memory device according to the present invention comprises an address latch circuit 50, a fuse circuit 51, a switching circuit 52, a selecting circuit 53, a decoding circuit 54, a switching circuit 55, a redundant circuit 56, a word driver circuit 57, and a memory array (not shown).

The address latch circuit 50 latches an address signal supplied from the outside and provides it to the switching circuit 52.

The fuse circuit 51 consists of a plurality of fuses. Information showing whether a defective line exists and information for specifying a defective line are held by these fuses.

The switching circuit 52 selects output from the address latch circuit 50 or output from the fuse circuit 51 under the control of the selecting circuit 53 and provides it to the decoding circuit 54.

At the time of the semiconductor memory device being started, the selecting circuit 53 provides a signal that instructs to select output from the fuse circuit 51 to the switching circuit 52 and switching circuit 55. After a redundant process is completed, the selecting circuit 53 provides a signal that instructs to select output from the address latch circuit 50 to the switching circuit 52 and switching circuit 55.

The decoding circuit 54 decodes an address signal supplied from the address latch circuit 50 or fuse circuit 51, generates a selection signal for selecting a word line, and outputs it.

The switching circuit 55 provides output from the decoding circuit 54 to the word driver circuit 57 or redundant circuit 56 in compliance with instructions given by the selecting circuit 53.

The redundant circuit 56 has a latch circuit therein and stores information obtained by the decoding circuit 54 decoding a signal output from the fuse circuit 51. Moreover, the redundant circuit 56 controls the word driver circuit 57 on the basis of this information and performs the redundant process of substituting other lines including a redundant line for a defective line.

The word driver circuit 57 performs a redundant process under the control of the redundant circuit 56 and controls the memory array in compliance with a selection signal obtained by the decoding circuit 54 decoding a signal output from the address latch circuit 50.

Now, operation in the above embodiment will be described.

If tests etc. before shipping show that there is a defective line in a memory array, a predetermined fuse in the fuse circuit 51 corresponding to the position of the defective line will be blown. The fuse circuit 51 includes a fuse showing whether there exists a defective line and a group of fuses for specifying the address of a defective line. If a defective line is detected, then the above word line showing whether there exists a defective line is blown and the above group of fuses are blown according to a predetermined pattern corresponding to the position of the defective line (pattern corresponding to a binary number which represents an address value, for example).

In this state of things, it is assumed that the semiconductor memory device is mounted in a predetermined circuit and that power is applied to that circuit. Then the selecting circuit 53 instructs the switching circuit 52 and switching circuit 55 to select output from the fuse circuit 51.

As a result, output from the fuse circuit 51 is selected by the switching circuit 52, is provided to the decoding circuit 54, is decoded there to convert into a selection signal, and is provided to the redundant circuit 56 by the switching circuit 55. This is shown in Fig. 3 by thick lines.

The redundant circuit 56 latches and holds the selection signal for redundancy supplied from the switching circuit 55 in the internal latch circuit. The selection signal latched in this way in the latch circuit will remain held until power is turned off.

After the selection signal is provided to the redundant circuit 56, the selecting circuit 53 instructs the switching circuit 52 and switching circuit 55 to select output from the address latch circuit 50.

As a result, the address latch circuit 50 latches an address signal supplied from the outside and provides it to the decoding circuit 54 via the switching circuit 52. This is shown in Fig. 4 by thick lines.

The decoding circuit 54 decodes the address signal to generate a selection signal and outputs it to the switching circuit 55.

The switching circuit 55 provides the output from the decoding circuit 54 to the word driver circuit 57 in compliance with instructions from the selecting circuit 53.

By the way, the word driver circuit 57 has performed a redundant process under the control of the redundant circuit 56, so other lines including the redundant line have been substituted for the defective line. As a result, if a selection signal that selects the defective line is input, a substitute line for the defective one will be accessed.

As described above, when a semiconductor memory device according to the present invention is started, information regarding a defective line stored in the fuse circuit 51 is provided to the redundant circuit 56 by the use of a path along which an ordinary address is transmitted. This enables to reduce the number of wirings, resulting in a lower probability of the penalties of wirings arising.

Furthermore, in the above embodiment, the redundant circuit 56 includes a latch circuit and information regarding a defective line is latched in it. Therefore, reading data from the fuse circuit 51 only once after the semiconductor memory device being started enables to perform a redundant process continuously without reading the data again.

A second embodiment of the present invention will now be described.

Fig. 5 is a view for giving an overview of a second embodiment of the present invention. As shown in Fig. 5, a semiconductor memory device according to the second embodiment comprises memory arrays 60a and 61a, decoding circuits 60b and 61b, fuse circuits 60c and 61c, and wirings 60d and 61d.

The first through fifth columns from the left of the memory array 60a, decoding circuit 60b, fuse circuit 60c, and wiring 60d form a subblock and the sixth through tenth columns from the left of them form another one.

Moreover, the first through fifth columns from the left of the memory array 61a, decoding circuit 61b, fuse circuit 61c, and wiring 61d form a subblock and the sixth through tenth columns from the left of them form another one.

In this example, only four subblocks are shown to simplify the description, but in practice more than four subblocks can exist.

The memory arrays 60a and 61a include a plurality of memory cells arranged like a matrix.

The decoding circuits 60b and 61b include a decoding circuit and redundant decoding circuit (hatched area). These decoding circuits generate a selection signal by inputting and decoding an address signal and make a word line corresponding to the selection signal active. Each of these redundant decoding circuits reads information regarding a defective line stored in the fuse circuit 60c or 61c, decodes it, and performs a shift redundancy process.

The fuse circuits 60c and 61c include, for example, a fuse showing whether a defective line exists and a plurality of fuses showing the position of a defective line. The fuse circuit 60c is located very near to a side of the memory array 60a parallel to the word lines. The fuse circuit 61c is located very near to a side of the memory array 61a parallel to the word lines.

The wiring 60d connects the decoding circuit 60b with the fuse circuit 60c and transmits information between them. The wiring 61d connects the decoding circuit 61b with the fuse circuit 61c and transmits information between them.

Fig. 6 is a view for describing operation in the second embodiment shown in Fig. 5.

As shown in Fig. 6, in this embodiment, subblocks located in the vertical direction include different fuse circuits, but subblocks located in the horizontal direction share a fuse circuit. Shift redundancy in upper and lower subblocks therefore can be performed independently.

In Fig. 6, areas marked by the "X" indicate the faulty point. In this example, the faulty points exist in the fourth column from the left in the right subblock and the third column from the left in the left subblock.

It is assumed that the fourth column from the left in the left subblock in the upper memory array 60a is a defective line. Then in the left subblock, the leftmost redundant line is substituted for the defective line. In addition, the leftmost redundant line is substituted in the same way in the right subblock.

Moreover, it is assumed that the third column from the left in the left subblock in the memory array 60b is a defective line. Then in the left subblock, the leftmost redundant line is substituted for the defective line. In addition, the leftmost redundant line is substituted in the same way in the right subblock.

As stated above, subblocks located in the vertical direction include different fuse circuits, so there is no need to locate signal lines over memory cells (see Fig. 13). This enables a reduction in the probability of the penalties of wirings arising.

In this example, subblocks located in the horizontal direction share a fuse circuit. However, they may include different fuse circuits.

Moreover, a fuse circuit is located very near to a side of a subblock parallel to the word lines. Therefore, even if a plurality of subblocks share a fuse circuit, for example, there is no need to locate wirings over a memory array. This enables a reduction in the probability of the penalties of wirings arising.

A third embodiment of the present invention will now be described.

Fig. 7 is a view showing the structure of a third embodiment of the present invention. The third embodiment is a synthesis of the first and second embodiments. In this example, a semiconductor memory device according to the third embodiment comprises a subblock 65 and subblock 66. As shown in Fig. 5, two or more subblocks may exist in the horizontal direction.

Fig. 8 is an enlarged view of an area enclosed with a dashed line in Fig. 7. In this example, the area includes an address latch circuit 70, a fuse circuit 71, a selecting circuit 72, a switching circuit 73, decoding circuits 74a and 75a, switching circuits 74b and 75b, latch circuits 74c and 75c, redundant circuits 74d and 75d, word driver circuits 74e and 75e, and memory cells 74f and 75f.

The address latch circuit 70, fuse circuit 71, selecting circuit 72, switching circuit 73, decoding circuits 74a and 75a, switching circuits 74b and 75b, redundant circuits 74d and 75d and word driver circuits 74e and 75e, and latch circuits 74c and 75c correspond to the address latch circuit 50, fuse circuit 51, selecting circuit 53, switching circuit 52, decoding circuit 54, switching circuit 55, word driver circuit 57, and redundant circuit 56 respectively.

The address latch circuit 70 is located very near to a side of the subblock 65 parallel to the word lines. The address latch circuit 70 latches an address signal supplied from the outside and provides it to the switching circuit 73.

The fuse circuit 71 is located very near to a side of the subblock 65 parallel to the word lines. This is the same with the address latch circuit 70. The fuse circuit 71 includes a plurality of fuses. Information showing whether a defective line exists and information for specifying a defective line (if it exists) are held by these fuses.

The switching circuit 73 is located so that wirings from the decoding circuits 74a and 75a will be straight. The switching circuit 73 selects output from the address latch circuit 70 or output from the fuse circuit 71 under the control of the selecting circuit 72 and provides it to the decoding circuits 74a and 75a.

At the time of the semiconductor memory device being started, the selecting circuit 72 provides a signal that instructs to select output from the fuse circuit 71 to the switching circuit 73 and switching circuits 74b and 75b. After a redundant process is completed, the selecting circuit 72 provides a signal that instructs to select output from the address latch circuit 70 to the switching circuit 73 and switching circuits 74b and 75b.

The decoding circuits 74a and 75a are located at the top of the subblock 65. The decoding circuits 74a and 75a decode an address signal supplied from the address latch circuit 70 or fuse circuit 71, generate a selection signal for selecting a word line, and output it.

The switching circuits 74b and 75b are located under the decoding circuits 74a and 75a respectively. The switching circuit 74b provides output from the decoding circuit 74a to the word driver circuit 74e or latch circuit 74c in compliance with instructions given by the selecting circuit 72. The switching circuit 75b provides output from the decoding circuit 75a to the word driver circuit 75e or latch circuit 75c in compliance with instructions given by the selecting circuit 72.

The latch circuits 74c and 75c are located under the switching circuits 74b and 75b respectively. The latch circuits 74c and 75c latch and store information supplied from the fuse circuit 71 and provide it to the redundant circuits 74d and 75d respectively.

The word driver circuits 74e and 75e are located under the redundant circuits 74d and 75d respectively. The word driver circuits 74e and 75e perform a redundant process on the basis of information latched by the latch circuits 74c and 75c respectively.

The memory cells 74f and 75f are formed by arranging a plurality of memory elements in the vertical direction.

Now, operation in the above embodiment will be described.

If tests etc. before shipping show that there is a defective line in one of the memory cells 74f, 75f, and so on, a predetermined fuse in the fuse circuit 71 corresponding to the position of the defective line will be blown. The work of blowing a fuse will be performed according to subblocks.

The fuse circuit 71 includes a fuse showing whether there exists a defective line and a group of fuses for specifying the address of a defective line in a memory array. If a defective line is detected, then the above word line showing whether there exists a defective line is blown and the above group of fuses are blown according to the position of the defective line. This is the same with the above case.

In this state of things, it is assumed that the semiconductor memory device is mounted in a predetermined circuit and that power is applied to that circuit. Then a selecting circuit in each subblock gives instructions to select output from the fuse circuit. In the example shown in Fig. 8, for example, the selecting circuit 72 instructs the switching circuit 73 and switching circuits 74b and 75b to select output from the fuse circuit 71.

As a result, output from the fuse circuit 71 is selected by the switching circuit 73 and is provided to the decoding circuits 74a and 75a. The decoding circuit 74a decodes the output from the fuse circuit 71 to convert into a selection signal, which is supplied to the latch circuit 74c by the switching circuit 74b. The decoding circuit 75a decodes the output from the fuse circuit 71 to convert into a selection signal, which is supplied to the latch circuit 75c by the switching circuit 75b.

The latch circuit 74c latches and holds the information supplied from the switching circuit 74b and provides it to the redundant circuit 74d. The latch circuit 75c latches and holds the information supplied from the switching circuit 75b and provides it to the redundant circuit 75d.

The redundant circuit 74d latches and holds the selection signal for redundancy supplied from the switching circuit 74b. The redundant circuit 75d latches and holds the selection signal for redundancy supplied from the switching circuit 75b. The information latched in this way will remain held until power is turned off.

After the selection signals are provided to the redundant circuits 74d and 75d, the selecting circuit 72 instructs the switching circuit 73 and switching circuits 74b and 75b to select output from the address latch circuit 70.

As a result, the address latch circuit 70 latches an address signal supplied from the outside and provides it to the decoding circuits 74a and 75a via the switching circuit 73.

The decoding circuit 74a and 75a decode the address signal to generate a selection signal and output it to the switching circuits 74b and 75b respectively.

The switching circuit 74b provides the output from the decoding circuit 74a to the word driver circuit 74e in compliance with instructions from the selecting circuit 72. The switching circuit 75b provides the output from the decoding circuit 75a to the word driver circuit 75e in compliance with instructions from the selecting circuit 72.

By the way, the word driver circuits 74e and 75e have performed a redundant process under the control of the redundant circuits 74d and 75d respectively. Another line therefore has been substituted for the defective line. As a result, if a selection signal that selects the defective line is input, the substitute line for the defective one will be accessed. To be concrete, if the memory cell 74f is a defective line and a request to access the memory cell 74f is made, another line, that is to say, another memory cell (not shown) will be accessed.

As described above, in the present invention, subblocks located in the direction parallel to the word lines (in the vertical direction) include different fuse circuits and are controlled independently of each other. Therefore, there is no need to locate wirings over memory cells (see Fig. 13) and the penalties of wirings can be prevented from arising.

Moreover, wirings which transmit an address signal also transmit redundancy information. The penalties of wirings therefore can be prevented from arising by reducing the number of wirings. This is the same with the above case.

Furthermore, a latch circuit is included and information regarding a defective line is latched in it. Therefore, reading data from a fuse circuit only once after a semiconductor memory device being started enables to perform a redundant process continuously without reading the data again.

In the above embodiment, each subblock includes an independent fuse circuit. However, a plurality of subblocks located in the direction perpendicular to word lines may share a fuse circuit. In that case, wirings should be located outside a memory array. That is to say, unlike prior semiconductor memory devices, there is no need to locate wirings over a memory array. Even such a structure therefore enables to prevent the penalties of wirings from arising.

If wirings of a spread type, for example, are formed in subblocks located in the direction parallel to word lines, the wirings which do not pass over memory cells can be formed. This can prevent the penalties of wirings from arising. As described above, in this case, the number of subblocks located in the vertical direction which can be controlled without wirings passing over word lines is two at the most.

Furthermore, in the above embodiments, a redundant process on a word line has been described as an example. It is, however, a matter of course that the present invention is applicable not only to word lines but also to column lines etc.

Finally each circuit described above is a simple example . It is a matter of course that the present invention is not limited to such cases.

The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.


Anspruch[de]
Eine Halbleiterspeichervorrichtung mit einer Mehrzahl von Teilblöcken, wobei jeder eine Treiberschaltung und ein Speicherarray (60a, 61a) umfasst, wobei die Vorrichtung umfasst: eine Speicherschaltung (60c, 61c) für Information über defekte Leitungen zum Speichern von Information, die defekte Leitungen im Teilblock anzeigt; und eine Redundanzschaltung (60b, 61b) zum Substituieren anderer Leitungen, einschließlich einer redundanten Leitung für eine defekte Leitung in jedem der Mehrzahl von Teilblöcken, basierend auf Information, die in der Speicherschaltung für Information über defekte Leitungen gespeichert ist, dadurch gekennzeichnet, dass Teilblöcke, die parallel zu den Leitungen angeordnet sind, verschiedene Speicherschaltungen für Information über defekte Leitungen umfassen, und dass Teilblöcke, die senkrecht zu den Leitungen angeordnet sind, eine Speicherschaltung für Information über defekte Leitungen teilen, und wobei die Speicherschaltung für Information über defekte Leitungen sehr nahe an einer Seite eines der Mehrzahl von Teilblöcken parallel zur Leitung angeordnet ist. Die Halbleiterspeichervorrichtung nach Anspruch 1, wobei jeder der Mehrzahl von Teilblöcken in eine Mehrzahl von Abschnitten unterteilt ist, und wobei die Redundanzschaltung einen Redundanzprozess in jedem der Mehrzahl von Abschnitten ausführt. Die Halbleiterspeichervorrichtung nach Anspruch 1, wobei die Redundanzschaltung nahe an einem der Mehrzahl von Teilblöcken angeordnet ist, wobei die vorrichtung des Weiteren umfasst: eine Adresseingabeschaltung zum Empfangen einer Adresssignaleingabe; eine Treiberschaltung zum Steuern der Mehrzahl von Teilblöcken gemäß dem Adresssignal; eine Signalleitung zum Verbinden der Adresseingabeschaltung und der Treiberschaltung; und eine Zuführschaltung zum Zuführen von Information, die in der Speicherschaltung für Information über defekte Leitungen gespeichert ist, an die Redundanzschaltung über die Signalleitung. Die Halbleiterspeichervorrichtung nach Anspruch 3, wobei die Treiberschaltung entlang einer Seite eines der Mehrzahl von Teilblöcken angeordnet ist, und wobei die Signalleitung parallel zu der Treiberschaltung angeordnet ist.
Anspruch[en]
A semiconductor memory device with a plurality of subblocks each including a drive circuit and a memory array (60a, 61a), the device comprising: a defective line information store circuit (60c, 61c), for storing information showing defective lines in the subblock; and a redundant circuit (60b, 61b) for substituting other lines including a redundant line for a defective line in each of the plurality of subblocks on the basis of information stored in the defective line information store circuit, characterised in that subblocks arranged in parallel to the lines include different defective line information store circuits, and subblocks arranged perpendicularly to the lines share a defective line information store circuit, and wherein the defective line information store circuit is located very near to a side of one of the plurality of subblocks parallel to the line. The semiconductor memory device according to claim 1, wherein each of the plurality of subblocks is divided into a plurality of sections, further wherein the redundant circuit performs a redundant process in each of the plurality of sections. The semiconductor memory device according to claim 1, wherein the redundant circuit is located near to one of the plurality of subblocks, the device further comprising: an address input circuit for receiving an address signal input; a drive circuit for driving the plurality of subblocks in compliance with the address signal; a signal line for connecting the address input circuit and the drive circuit; and a supply circuit for supplying information stored in the defective line information store circuit to the redundant circuit via the signal line. The semiconductor memory device according to claim 3, wherein the drive circuit is located along a side of one of the plurality of subblocks, further wherein the signal line is located parallel to the drive circuit.
Anspruch[fr]
Dispositif de mémoire à semiconducteur muni d'une pluralité de sous-blocs dont chacun inclut un circuit de pilotage et un réseau de mémoire (60a, 61a), le dispositif comprenant : un circuit de stockage d'information de ligne défectueuse (60c, 61c) pour stocker une information représentant des lignes défectueuses dans le sous-bloc ; et un circuit redondant (60b, 61b) pour substituer d'autres lignes incluant une ligne redondante à une ligne défectueuse dans chacun de la pluralité de sous-blocs sur la base d'une information stockée dans le circuit de stockage d'information de ligne défectueuse, caractérisé en ce que des sous-blocs agencés en parallèle aux lignes incluent des circuits de stockage d'information de ligne défectueuse différents, et des sous-blocs agencés perpendiculairement aux lignes partagent un circuit de stockage d'information de ligne défectueuse, et dans lequel : le circuit de stockage d'information de ligne défectueuse est localisé très près d'un côté de l'un de la pluralité de sous-blocs parallèlement à la ligne. Dispositif de mémoire à semiconducteur selon la revendication 1, dans lequel chacun de la pluralité des sous-blocs est divisé selon une pluralité de sections, dans lequel en outre le circuit redondant réalise un processus redondant dans chacune de la pluralité de sections. Dispositif de mémoire à semiconducteur selon la revendication 1, dans lequel le circuit redondant est localisé à proximité de l'un de la pluralité de sous-blocs, le dispositif comprenant en outre : un circuit d'entrée d'adresse pour recevoir une entrée de signal d'adresse ; un circuit de pilotage pour piloter la pluralité de sous-blocs en conformité avec le signal d'adresse ; une ligne de signal pour connecter le circuit d'entrée d'adresse et le circuit de pilotage ; et un circuit d'alimentation pour appliquer une information stockée dans le circuit de stockage d'information de ligne défectueuse sur le circuit redondant via la ligne de signal. Dispositif de mémoire à semiconducteur selon la revendication 3, dans lequel le circuit de pilotage est localisé le long d'un côté de l'un de la pluralité de sous-blocs, dans lequel en outre la ligne de signal est localisée parallèlement au circuit de pilotage.






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