PatentDe  


Dokumentenidentifikation EP1563510 13.09.2007
EP-Veröffentlichungsnummer 0001563510
Titel 2T2C SIGNAL MARGIN TEST UNTER VERWENDUNG EINES DEFINIERTEN LADUNGSAUSTAUSCHS ZWISCHEN KOMPLEMENTÄREN BITLEITUNGEN
Anmelder Infineon Technologies AG, 81669 München, DE
Erfinder JOACHIM, Hans-Oliver, 9500 Villach Carinthia, AT;
JACOB, Michael, 9500 Villach, AT
DE-Aktenzeichen 60315340
Vertragsstaaten DE, FR, GB
Sprache des Dokument EN
EP-Anmeldetag 11.11.2003
EP-Aktenzeichen 037702172
WO-Anmeldetag 11.11.2003
PCT-Aktenzeichen PCT/SG03/00262
WO-Veröffentlichungsnummer 2004047115
WO-Veröffentlichungsdatum 03.06.2004
EP-Offenlegungsdatum 17.08.2005
EP date of grant 01.08.2007
Veröffentlichungstag im Patentblatt 13.09.2007
IPC-Hauptklasse G11C 29/00(2006.01)A, F, I, 20070703, B, H, EP
IPC-Nebenklasse G11C 11/22(2006.01)A, L, I, 20070703, B, H, EP   

Beschreibung[en]
Related Applications

The present disclosure is related to the following concurrently filed applications, all of which are to be assigned to Infineon Technologies AG.

"2T2C Signal Margin Test Mode Using Resistive Element" to Michael Jacob et al., publication number WO 2004/047118 A1 , attorney reference number FP1783; "2T2C Signal Margin Test Mode Using Different Pre-Charge Levels for BL and /BL" to Michael Jacob et al., publication number WO 2004/047116 A1 , attorney reference number FP 1806; and "2T2C Signal Margin Test Mode Using a Defined Charge and Discharge of BL and /BL" to Hans-Oliver Joachim et al., Publication number WO 2004/04 7115 A1 , attorney reference number FP1808.

Field of the Invention

The present invention relates to the implementation of circuits for testing signal margin in memory cells operating in a 2T2C configuration.

Background of the Invention

In semiconductor memories, reliability issues have become more complicated with increasing memory sizes, smaller feature sizes and lower operating voltages. It has become more important to understand the cell signal sensing operation, the signal of memory cells and the limiting factors. One particularly important characteristic in reliability determinations of semiconductor memories is the signal margin. In a 2T2C memory cell configuration, the signal margin is a measure of the zero-versus-one signal measured by the sense amplifier. It is particularly useful to be able to measure the signal margin at product level. The results of product-level signal-margin tests can be used to optimize reliability and as well as the sense amplifier design and the bit line architecture to optimize dynamic memory cell readout. Moreover, a product level test sequence for signal margin can help ensure full product functionality over the entire component lifetime taking all aging effects into account.

Among the more recent semiconductor memories, Ferroelectric Random Access Memories (FeRAMs) have attracted much attention due to their low-voltage and high-speed operation in addition to their non-volatility. Figure 1 shows a typical prior art FeRAM memory cell in a 2T2C configuration. The 2T2C configuration utilizes two transistors and two capacitors per bit. The 2T2C configuration is beneficial because it allows for noise cancellation between the transistors. Two storage capacitors (Cferro) are connected to a common plate line (PL) on one side and to a pair of bit lines (BL, /BL) on the other side via two select transistors (TS). The two transistors are selected simultaneously by a common word line (WL). A dedicated bit line capacitance (CBL) is connected to each bit line. This bit line capacitance is required for the read operation of the memory cell. The differential read signal on the bit line pair is evaluated in a connected sense amplifier. The polarization is always maintained in directly opposed states in the two storage capacitors of one 2T2C memory configuration.

The signals on the bit lines during a read access are shown in Figure 2. Figs. 2 and 4 of the present disclosure all include a plot of the read signals on BL /BL vs. time. In these plots, one of the lines represents the read signal on BL and one represents the read signal on /BL. Which signal is represented by which of the lines depends on whether the read signal on BL or the read signal on /BL is larger. First, both bit lines BL and /BL are pre-charged to the same level (e.g. 0V in the figure). At time t0 the plate is activated and a read signal appears on the bit lines according to the capacitance ratio Cferro/CBL. The effective capacitance of a ferroelectric capacitor depends on its polarization state prior to the read operation. At time t1 the full read signals are developed on the two bit lines. At t2 the sense amplifier is activated and the bit line signals are boosted to the full bit line voltages. At t3 the sense amplifier is deactivated and the access cycle ends at t4.

A good solution for determining signal margin in FeRAM memory cells utilizing a single transistor and capacitor (1T1C) is to sweep the reference bit line voltage. A prior art method for determining signal margin in 2T2C FeRAM memory cells is to shift the bit line level by capacitor coupling. However, this method is unsatisfactory because it requires an additional capacitor.

It would therefore be desirable to provide a circuit with a test mode section for facilitating a worst case product test sequence for signal margin. It would also be desirable to design such a circuit for use with semiconductor memories in a 2T2C configuration without requiring additional capacitors in the circuit.

Summa of the invention

The present invention provides a semiconductor memory test mode configuration according to claim 1 and a method according to claim 11 for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. The invention works well with semiconductor memories having a 2T2C configuration.

Brief Description of the Figures

Further preferred features of the invention will now be described for the sake of example only with reference to the following figures, in which:

  • Fig. 1 illustrates a 2T2C memory configuration of the prior art.
  • Fig. 2 plots the signals on the bit lines during a read access cycle in the prior art circuit of Fig. 1.
  • Fig. 3 shows a memory configuration of the present invention having a transistor for exchanging charge between BL and /BL.
  • Fig. 4 plots the signals on the bit lines along with the signal VCE during a read access cycle for the circuit of Fig. 3.

Detailed Description of the Embodiments

Fig. 3 shows a circuit schematic of a memory cell 10 according to the invention. The circuit of Fig. 3 differs from the prior art circuit of Fig. 1 in that a transistor TCE 24. connects bit line /BL 16' with bit line BL 16. The transistor TCE 24 attaches to the bit lines /BL 16' and BL 16 at points such that the bit line capacitors CBL 14', 14 are between the connection points and ground.

The transistor is activated at it's gate by a signal input VCE 20. The signal input VCE 20 is kept at non-active (wherein the transistor VCE 20 is off) during normal operation and the circuit is electrically similar to the circuit shown in Fig. 1. During testing, the signal VCE 20 can be activated thereby transferring charge between the bit lines BL 16 and /BL 16'.

The memory cell 10 of Fig. 3 provides a test mode circuit for testing for signal margin. In order to test the memory cell 10, data is first written into the memory cell 10.and afterwards the data is read and compared to the expected (i.e. written) data. 2T2C signal margin can be tested by selectively reducing the difference between a "0" signal on one bit line and a "1" signal on the other bit line. This is achieved by the present invention in a way that a defined charge exchange is performed between the bit lines BL 16 and /BL 16' after the read signals have developed. In one implementation, the transistor TCE 24 connects BL 16 and /BL 16' as illustrated in Fig. 3. By adjusting the control signal VCE 20 (gate-source voltage) and the time the gate is opened, a defined amount of charge is allowed to flow from the bit line with the "1" signal to the bit line with the "0" signal, thereby reducing the "1" and increasing the "0" simultaneously as illustrated in Fig. 4.

The effect of this test mode is that after signal development on the bit lines (following the activation of a common plate line PL 18 and just before sense amplifier 21 activation) the difference between the "0" signal on the bit line /BL 16' (see Figure 3) and the "1" signal on the bit line BL 16 (again, see Figure 3) is smaller than in the normal read operation. The result of this test mode is a reduced differential read signal (i.e. the difference between the two bit-line signals) which tightens the margin for a save operation of the chip (the worst case test condition).

The corresponding bit-line 16, 16' signals are shown in Fig. 4. The trace 30 represents the signal VCE 30 for activating the transistor TCE 24. The traces 32 and 34 represent the signal levels on the bit lines BL 16 and /BL 16', respectively. In this example, the bit line /BL 16' is assumed to be the bit line with the lower read signal. The bit lines BL 16 and /BL 16' are pre-charged to a certain level (e.g. 0V in the figure) and at time t0 the common plate line (PL) 18 is activated and a read signal appears on the bit lines according to the capacitance ratio Cferro/CBL. Here, Cferro is the capacitance of storage capacitors Cferro 17 and Cferro 17' which are connected to the plate 18 on one side and to the pair of bit lines (BL 16, /BL 16') on the other side via two select transistors (TS) 19, 19'. CBL is the capacitance of dedicated bit line capacitances (CBL) 14, 14' connected to each bit line. At time t1 the full read signals are developed on the two bit lines 16, 16'. The signal VCE 30 is activated switching on the transistor TCE 24 and opening up a charge transfer path between the bit lines BL 16 and /BL 16'. The signal VCE 30 can be, in general, activated during the time after signal development on the bit lines (soon after activation of a common plate line PL 18) and can be deactivated just before sense amplifier 21 activation. The activation period of the signal VCE 30 and the corresponding on-time of the transistor TCE 24 should at least partially overlap the period of time between activation of the common plate line PL 18 at time t0 and the sense amplifier 21 activation time t2. The charge on the bit line with the higher read signal is decreased while the charge on the bit line with the lower read signal is increased resulting in a decreased signal on this bit lines at t2 when a sense amplifier 21 is activated and the bit line signals are boosted to the full bit line voltages. As a result, the differential read signal, i.e. the difference between the two bit-line signals, is decreased accordingly, which tightens the margin for a save operation of the chip (the worst case test condition). At t3 the sense amplifier is deactivated and the access cycle ends at t4.

The higher signal, on bit line BL 16, is therefore reduced while the lower signal, on bit line /BL 16', is increased, and the difference between the higher and lower bit line signals becomes smaller for this test. The amount of "signal margin" can be controlled by the time window during which the transistor TCE 24 is switched on.

One example of the procedure to test for the analog value of the signal margin is illustrated by the following steps:

  1. 1. Write data to and then read data from the memory cell in normal operation (without activating the transistor TSM 24). If the differential read signal is too small, then a comparison of the read data with the write data fails, thereby indicating that the circuit has no signal margin. If the differential read signal is sufficiently large then step 2 is performed.
  2. 2. Write data to and then read data from the memory cell with the time window of the transistor 24 set to a small value signal margin (SMO) to drain some of the charge from the bit lines. If the differential read signal is too small, then a comparison of the read data with the write data fails, thereby indicating that the circuit has no signal margin. If the differential read signal is sufficiently large then step 3 is performed.
  3. 3. Write data to and then read data from the memory cell with the time window of the transistor 24 set to a slightly larger value corresponding to first signal margin (SM1) to drain some of the charge from the bit lines. If the differential read signal is too small, then a comparison of the read data with the write data fails, thereby indicating that the circuit has a signal margin corresponding to SM0. If the differential read signal is sufficiently large then step 4 is performed.
  4. 4. Write data to and then read data from the memory cell with the time window of the transistors 24 set to an even larger value corresponding to second signal margin (SM2) to drain more of the charge from the bit lines. If the differential read signal is too small, then a comparison of the read data with the write data fails, thereby indicating that the circuit has a signal margin corresponding to SM1. If the differential read signal is sufficiently large then the test is continued until the failure of the comparison.

In an alternative embodiments, the potential VCE 20 is generated chip internally (on the same chip) or is provided externally.

In another alternative embodiment, a more sophisticated constant current sink/source is implemented instead of a transistor TCE, providing more accurate control of the amount of charge that is exchanged between BL and /BL.

Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to a skilled reader.


Anspruch[de]
Eine Testmoduskonfiguration für Halbleiterspeicher, bestehend aus: einem ersten Kondensator (17) zur Speicherung digitaler Daten, welcher eine Zellenzuleitung (18) mit einer ersten Bitleitung (16) über einen ersten Auswahltransistor (19) verbindet, wobei der erste Auswahltransistor (19) durch eine Verbindung zu einer Wortleitung (WL) aktiviert wird; einem zweiten Kondensator (17') zur Speicherung digitaler Daten, welcher die Zellenzuleitung mit einer zweiten Bitleitung (16') über einen zweiten Auswahltransistor (19') verbindet, wobei der zweite Auswahltransistor durch eine Verbindung zu der Wortleitung aktiviert wird; einen Leseverstärker (21), verbunden mit der ersten und zweiten Bitleitung, zur Messung eines Differentiallesesignals auf der ersten und zweiten Bitleitung; ein Ladungspfad (24) für die Übertragung einer Ladung zwischen der ersten und der zweiten Bitleitung, um das Differentiallesesignal zu reduzieren; und dadurch charakterisiert, dass Hilfsmittel zur Aktivierung des Ladungspfades für die Übertragung der Ladung zwischen der ersten und zweiten Bitleitung angeordnet sind, für einen Zeitraum, der sich zumindest teilweise mit dem Zeitraum zwischen der Aktivierung der Zuleitung in einem Zugriffstakt während eines Tests und der Aktivierung des Leseverstärkers in dem vorgenannten Zugriffstakt überschneidet. Die Testmoduskonfiguration für Halbleiterspeicher nach Anspruch 1, in der die erste Bitleitung ein niedrigeres Lesesignal hat als die zweite Bitleitung und in der eine Ladung über einen Ladungspfad von der zweiten Bitleitung zu der ersten Bitleitung übertragen wird. Die Testmoduskonfiguration für Halbleiterspeicher nach Anspruch 1, in der der Ladungspfad eine Ladung überträgt und die Übertragung einer Ladung in Reaktion auf ein für den vorgenannten Zeitraum aktiviertes Signal beendet. Die Testmoduskonfiguration für Halbleiterspeicher nach Anspruch 1, in der der Ladungspfad ein dritter Transistor ist, der in Reaktion auf ein Signal ein- und ausgeschaltet wird. Die Testmoduskonfiguration für Halbleiterspeicher nach Anspruch 4, in der das Signal intern im Chip generiert wird. Die Testmoduskonfiguration für Halbleiterspeicher nach Anspruch 4, in der das Signal in ein Gate des dritten Transistors eingespeist wird und in der der Transistor einen Drain-Anschluss hat und eine Quelle, die mit der ersten und der zweiten Bitleitung verbunden ist. Ein Ferroelektrischen Random Access Speicher, der die Testmoduskonfiguration für Halbleiterspeicher des Anspruches 1 besitzt. Die Testmoduskonfiguration für Halbleiterspeicher des Anspruches 1, in dem der erste und der zweite Kondensator ferroelektrische Kondensatoren sind. Die Testmoduskonfiguration für Halbleiterspeicher des Anspruches 4, die des Weiteren einen Bitleitungskondensator einschließt, angeschlossen zwischen dem dritten Transistor und der Erdung. Die Testmoduskonfiguration für Halbleiterspeicher des Anspruches 1, in der der Ladungspfad eine konstante Stromsenke oder -quelle ist. Eine Methode zum Testen eines Halbleiterspeichers, bestehend aus den Schritten: Voraufladung der ersten und zweiten Bitleitung (16, 16'); Aktivierung einer Zellenzuleitung (18) zur Produzierung eines Lesesignals auf der ersten und zweiten Bitleitung, welches digitale Daten repräsentiert, die von einem mit der Zuleitung verbundenen Paar Kondensatoren (17, 17') gespeichert werden, wobei jeder der besagten Kondensatoren mit jeweils einer der besagten ersten und zweiten Bitleitungen über einen der ersten und zweiten Transistoren (19, 19') verbunden sind; Aktivierung eines dritten Transistors (24), der für eine Zeitspanne zwischen der ersten und zweiten Bitleitung verbunden ist, um eine Ladung zwischen der ersten und der zweiten Bitleitung zu übertragen; Aktivierung eines Leseverstärkers (21), der mit der ersten und er zweiten Bitleitung verbunden ist, und dadurch die Lesesignale auf der ersten und auf der zweiten Bitleitung verstärkt; und die Bestimmung eines reduzierten Differentiallesesignals auf der ersten und der zweiten Bitleitung auf Grund des veränderten Betrages der Ladung auf der ersten und der zweiten Bitleitung; charakterisiert dadurch, dass die besagte Zeitspanne zumindest teilweise einen Zeitraum zwischen der besagten Aktivierung der Zellenzuleitung in einem Zugriffstakt während des Tests überschneidet und der besagten Aktivierung des Leseverstärkers während des besagten Zugriffstaktes.
Anspruch[en]
A semiconductor memory test mode configuration, comprising: a first capacitor (17) for storing digital data connecting a cell plate line (18) to a first bit line (16) through a first select transistor (19), the first select transistor activated through a connection to a word line (WL). a second capacitor (17') storing digital data connecting the cell plate line to a second bit line (16') through a second select transistor (19'), the second select transistor activated through a connection to the word line; a sense amplifier (21) connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines; a charge path (24) for transferring charge between the first and second bit lines to reduce the differential read signal; and characterised by means arranged to activate the charge path to transfer charge between the first and second bit lines for a time interval at least partially overlapping a period of time between activation of the plate line in an access cycle during a test and activation of the sense amplifier in said access cycle. The semiconductor memory test mode configuration of Claim 1, wherein the first bit line has a lower read signal than the second bit line and charge is passed from the second bit line to the first bit line through the charge path. The semiconductor memory test mode configuration of Claim 1, wherein the charge path transfers charge and ends the transfer of charge in response to a signal activated for said time interval. The semiconductor memory test mode configuration of Claim 1, wherein the charge path is a third transistor turned on and off in response to a signal. The semiconductor memory test mode configuration of Claim 4, wherein the signal is generated chip-internally. The semiconductor memory test mode configuration of Claim 4, wherein the signal is input into a gate of the third transistor and the transistor has a drain and a source connected to the first and second bit lines. A Ferroelectric Random Access Memory having the semiconductor memory test mode configuration of Claim 1. The semiconductor memory test mode consignation of Claim 1, wherein the first and second capacitors are ferroelectric capacitors. The semiconductor memory test mode configuration of Claim 4, further comprising a bit line capacitor connected between the third transistor and ground. The semiconductor memory test mode configuration of Claim 1, wherein the charge path is a constant current sink or source. A method for testing a semiconductor memory comprising the steps of: pre-charging first and second bit lines (16,16'), activating a cell plate line (18) to produce a read signal on the first and second bit lines representing digital data stored by a pair of capacitors (17,17') connected to the cell plate line, each of said capacitors connected to a corresponding one of said first and second bit lines through one of first and second transistors (19,19'); activating a third transistor (24), connected between the first and second bit lines, for a time interval to transfer charge between the first and second bit lines, activating a sense amplifier (21), connected to the first and second bit line thereby boosting read signals on the first and second bit lines ; and determining a reduced differential read signal on the first and second bit lines due to the changed amount of charge on the first and second bit lines; characterised by said time interval at least partially overlapping a period of time between said activating the cell plate line in an access cycle during the test and said activating the sense amplifier in said access cycle.
Anspruch[fr]
Configuration de mode d'essai de mémoire à semi-conducteurs, comportant : un premier condensateur (17) permettant d'enregistrer des données numériques connectant une ligne de plaques de cellule (18) sur une première ligne de bits (16) par le biais d'un premier transistor de sélection (19), le premier transistor de sélection étant activé par le biais d'une connexion sur une ligne de mots (WL) ; un deuxième condensateur (17') permettant d'enregistrer des données numériques connectant la ligne de plaques de cellule sur une deuxième ligne de bits (16') par le biais d'un deuxième transistor de sélection (19'), le deuxième transistor de sélection étant activé par le biais d'une connexion sur la ligne de mots ; un amplificateur de détection (21) connecté sur la première ligne de bits et sur la deuxième ligne de bits permettant de mesurer un signal de lecture différentiel sur la première ligne de bits et sur la deuxième ligne de bits ; un trajet de charge (24) permettant de transférer une charge entre la première ligne de bits et la deuxième ligne de bits afin de réduire le signal de lecture différentiel ; et caractérisée par un moyen arrangé pour activer le trajet de charge pour transférer une charge entre la première ligne de bits et la deuxième ligne de bits pendant un intervalle de temps chevauchant au moins partiellement une période de temps entre l'activation de la ligne de plaques dans un cycle d'accès pendant un essai et l'activation de l'amplificateur de détection dans ledit cycle d'accès. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 1, dans laquelle la première ligne de bits a un signal de lecture plus faible par rapport à la deuxième ligne de bits et dans laquelle une charge est passée de la deuxième ligne de bits à la première ligne de bits par le biais du trajet de charge. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 1, dans laquelle le trajet de charge transfère une charge et met fin au transfert de charge en réponse à un signal activé pour ledit intervalle de temps. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 1, dans laquelle le trajet de charge est un troisième transistor mis sous tension et mis hors tension en réponse à un signal. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 4, dans laquelle le signal est généré de manière interne dans la puce. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 4, dans laquelle le signal est entré dans une grille du troisième transistor et dans laquelle le transistor a un drain et une source en connexion sur la première ligne de bits et sur la deuxième ligne de bits. Mémoire vive ferroélectrique ayant la configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 1. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 1, dans laquelle le premier condensateur et le deuxième condensateur sont des condensateurs ferroélectriques. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 4, comportant par ailleurs un condensateur de ligne de bits connecté entre le troisième transistor et la terre. Configuration de mode d'essai de mémoire à semi-conducteurs selon la revendication 1, dans laquelle le trajet de charge est une source ou un collecteur de courant constant. Procédé d'essai d'une mémoire à semi-conducteurs comportant les étapes consistant à: précharger la première ligne de bits et la deuxième ligne de bits (16, 16') ; activer une ligne de plaques de cellule (18) afin de produire un signal de lecture sur la première ligne de bits et sur la deuxième ligne de bits représentant les données numériques enregistrées par une paire de condensateurs (17, 17') connectés sur la ligne de plaques de cellule, chacun desdits condensateurs étant connecté sur l'une correspondante de ladite première ligne de bits et de ladite deuxième ligne de bits par le biais de l'un du premier transistor et du deuxième transistor (19, 19') ; activer un troisième transistor (24) connecté entre la première ligne de bits et la deuxième ligne de bits, pendant un intervalle de temps afin de transférer une charge entre la première ligne de bits et la deuxième ligne de bits ; activer un amplificateur de détection (21) connecté sur la première ligne de bits et sur la deuxième ligne de bits pour, de ce fait, amplifier les signaux de lecture sur la première ligne de bits et sur la deuxième ligne de bits ; et déterminer un signal de lecture différentiel réduit sur la première ligne de bits et sur la deuxième ligne de bits en raison de la quantité changée de charge sur la première ligne de bits et sur la deuxième ligne de bits ; et caractérisé par ledit intervalle de temps chevauchant au moins partiellement une période de temps entre ladite activation de la ligne de plaques de cellule dans un cycle d'accès au cours de l'essai et ladite activation de l'amplificateur de détection dans ledit cycle d'accès.






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