PatentDe  


Dokumentenidentifikation EP1396863 15.11.2007
EP-Veröffentlichungsnummer 0001396863
Titel Halbleiterspeichereinrichtung und Prüfungsverfahren
Anmelder Fujitsu Ltd., Kawasaki, Kanagawa, JP
Erfinder Nakagawa, Yuji, Kasugai-shi, Aichi 487-0013, JP
Vertreter W. Seeger und Kollegen, 81369 München
DE-Aktenzeichen 60316647
Vertragsstaaten DE, FR
Sprache des Dokument EN
EP-Anmeldetag 24.07.2003
EP-Aktenzeichen 030168777
EP-Offenlegungsdatum 10.03.2004
EP date of grant 03.10.2007
Veröffentlichungstag im Patentblatt 15.11.2007
IPC-Hauptklasse G11C 29/00(2006.01)A, F, I, 20070904, B, H, EP
IPC-Nebenklasse G11C 11/406(2006.01)A, L, I, 20070904, B, H, EP   G11C 7/10(2006.01)A, L, I, 20070904, B, H, EP   G11C 7/22(2006.01)A, L, I, 20070904, B, H, EP   G11C 8/18(2006.01)A, L, I, 20070904, B, H, EP   

Beschreibung[en]

The present invention relates to a semiconductor memory device and a method for testing a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having functions for processing external and internal accesses, and to a method for testing such a semiconductor memory device.

A semiconductor memory device according to the preamble of claim 1 is known from US 2001/017811 A1 .

Electronic information devices incorporate semiconductor memory devices having large memory capacities (i.e., dynamic random access memory (DRAM)). A DRAM has a self-refreshing function to refresh the data of a memory cell in accordance with a counting operation performed by an internal circuit. The DRAM does not require an external device to perform refreshing. This decreases power consumption and simplifies the design of circuits in the periphery of the DRAM.

In a DRAM provided with the self-refreshing function, a timer of an internal circuit generates refresh requests (internal access) at predetermined time intervals. Further, a main controller of an external device generates write/read requests (external access) at certain timings. In other words, internal and external accesses are generated asynchronously. Accordingly, there is a demand for evaluating a DRAM having two asynchronous access modes.

Fig. 1 is a schematic block circuit diagram illustrating the input section of a prior art semiconductor memory device (DRAM) 50 provided with a self-refreshing function.

The DRAM 50 receives a plurality of control signals CTL and a plurality (only two bits shown in Fig. 2) of external address signals ADD via external terminals. The control signals CTL include a chip enable signal /CE, a write enable signal /WE, and an output enable signal /OE. The external address signals ADD include address signals A0 and A1. The signals /CE, /WE, /OE, A0, and A1 are input to a transition detection signal generation circuit 70 via input buffers 61, 62, 63, 64, and 65, respectively. The input buffers 61 to 65 function as initial input stage circuits, which convert an input signal to a signal having a level corresponding to the internal voltage of the device. Further, the input buffers 61 to 65 are each configured by a CMOS inverter or a C/M differential amplifier.

The transition detection signal generation circuit 70 includes a plurality (five in Fig. 1) of transition detectors (TD) 71 to 75 and a pulse synthesizing circuit 76.

The transition detectors 71, 72, and 73 respectively detect the transition (transition between a high level and a low level) of the control signals CTL (/CE, /WE, and /OE) to generate input detection signals ceb, web, and oeb. The transition detectors 74 and 75 respectively detect the transition of the states (change of each bit) of the input external address signal ADD (A0 and A1) to generate address detection signals ad0 and ad1. The detection signals ceb, web, oeb, ad0, and ad1 are provided to the pulse synthesizing circuit 76.

The pulse synthesizing circuit 76 generates a transition detection signal mtd in accordance with the detection signals ceb, web, oeb, ad0, and ad1 and provides the transition detection signal mtd to a memory control circuit 77. In accordance with the transition detection signal mtd, the memory control circuit 77 generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of a memory cell corresponds to a predetermined read/write address, which is assigned by the external address signal ADD. The timing signal wl.-timing is provided to a memory core 79.

A refresh timer 78 is connected to the memory control circuit 77. The refresh timer 78 generates a refresh request signal ref-req at predetermined time intervals and provides the refresh request signal ref-req to the memory control circuit 77. In accordance with the refresh request signal ref-req, the memory control circuit 77 generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of a memory cell corresponds to a predetermined refresh address, which is generated by an internal address counter (not shown).

The memory control circuit 77 further receives a test signal test from a test circuit (not shown) to conduct a test in a test mode in accordance with the test signal test.

Fig. 2 is a schematic block circuit diagram of the memory control circuit 77. The memory control circuit 77 includes a refresh determination circuit 81, an internal command generation circuit 82, and a timing generator 83.

The refresh determination circuit 81 receives the transition detection signal mtd, the refresh request signal ref-req, and the test signal test. In response to the refresh request signal ref-req, the refresh determination circuit 81 generates a refresh start signal ref-start, which starts refreshing (internal access), and a refresh state signal ref-state. The refresh start signal ref-start is provided to the timing generator 83, and the refresh state signal ref-state is provided to the internal command generation circuit 82.

When receiving the transition detection signal mtd before the refresh request signal ref-req, the refresh determination circuit 81 suspends refreshing and does not generate a refresh signal.

In this state, the refresh determination circuit 81 gives priority to read/write operations (external accesses) and starts refreshing after the read/write operations are completed. More specifically, after a read/write state signal rw-state, which is provided from the timing generator 83, is reset, the refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state.

The refresh determination circuit 81 determines the input timings of the refresh request signal ref-req and the transition detection signal mtd, which are asynchronously input, and determines which one of the refreshing operation and the read/write operation has priority when there is more than one access.

In response to the transition detection signal mtd, the internal command generation circuit 82 generates the read/write start signal rw-start, which starts read/write operations, and provides the read/write start signal rw-start to the timing generator 83. When the internal command generation circuit 82 receives the refresh state signal ref-state, the internal command generation circuit 82 provides the read/write start signal rw-start to the timing generator 83 after the refresh state signal ref-state is reset.

The timing generator 83 receives the refresh start signal ref-start and the read/write start signal rw-start. In response to the refresh start signal ref-start, the timing generator 83 generates the word-line activation timing signal wl-timing in correspondence with the refresh address. In response to the read/write start signal rw-start, the timing generator 83 generates the read/write state signal rw-state and generates the word-line activation timing signal wl-timing in correspondence with the predetermined read/write address.

In addition to the word line activation timing signal wl-timing, the timing generator 83 generates other internal operation signals, such as a sense amplifier activation timing signal for activating a sense amplifier. Only the word line activation timing signal wl-timing will be discussed below.

The operation of the DRAM 50 will now be discussed. Fig. 3 is a waveform diagram illustrating the operation of the transition detection signal generation circuit 70.

For example, when the chip enable signal /CE goes low, the transition detector 71 generates the input detection signal ceb (pulse signal). The pulse synthesizing circuit 76 generates the transition detection signal mtd in accordance with the transition signal mtd. Then, for example, when the address signal A0 goes high (1), the transition detector 74 generates an address detection signal ad0 (pulse signal). In accordance with the detection signal ad0, the pulse synthesizing circuit 76 generates the transition detection signal mtd.

In the transition detection signal generation circuit 70, the pulse synthesizing circuit 76 generates the transition detection signal mtd when a transition occurs in any one of the control signals (/CE, /WE, and /OE) and the address signals ADD (A0 and A1).

Figs. 4 and 5 are waveform charts illustrating the operation of the memory control circuit 77. Fig. 4 illustrates an example in which there is more than one access at the same time and the transition detection signal mtd is provided to the memory control circuit 77 before the refresh request signal ref-req.

Among the control signal CTL and the external address signal ADD, the pulse synthesizing circuit 76 detects the signal that has undergone a transition (i.e., shifting of levels between high and low) and generates the transition detection signal mtd. Then, the refresh timer 78 generates the refresh request signal ref-req. Thus, the refresh operation is performed after the read/write operation.

More specifically, the internal command generation circuit 82 generates the read/write start signal rw-start in accordance with the transition detection signal mtd. The timing generator 83 generates the read/write state signal rw-state and the word line activation timing signal wl-timing in accordance with the read/write start signal rw-start. In this state, a word line corresponding to the predetermined read/write address is activated to read or write cell data.

When the read/write operation is completed and the read/write state signal rw-state is reset, the refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state. In accordance with the refresh start signal ref-start, the timing generator 83 generates the word line activation timing signal wl-timing. This activates the word line corresponding to a predetermined refresh address and refreshes the cell data.

Fig. 5 illustrates an example in which the refresh request signal ref-req is provided to the memory control circuit 77 before the transition detection signal mtd. Contrary to the operations illustrated in Fig. 4, the read/write operation is performed after the refresh operation.

The refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state in accordance with the refresh request signal ref-req. The timing generator 83 generates the word line activation timing signal w1-timing in accordance with the refresh start signal ref-start. This activates the word line corresponding to a predetermined refresh address and refreshes the cell data.

When the refresh operation is completed and the refresh state signal ref-state is reset, the internal command generation circuit 82 generates the read/write start signal rw-start in response to the transition detection signal mtd. In accordance with the read/write start signal rw-start, the timing generator 83 generates the read/write state signal rw-state and the word line activation timing signal wl-timing. In this state, the reading or writing of the cell data is performed.

When there is more than one access at the same time and the read/write operation (external access) is performed after the refreshing operation (internal access), the speed of the read/write operation becomes slowest. That is, the external access time becomes longest. Thus, to evaluate the characteristics of the DRAM 50, which has two access modes (i.e., external access mode and internal access mode), the operation pattern when the external access time becomes maximum (i.e., worst pattern) must be checked.

Fig. 6 is a waveform chart illustrating a test mode. More specifically, Fig. 6 is a waveform chart simulating an operation pattern when a read/write operation is performed after a refresh operation.

In the test mode, the refresh determination circuit 81 receives a test signal test from a test circuit (not shown). When the refresh determination circuit 81 receives the test signal test, the refresh determination circuit 81 generates the refresh start signal ref-start in accordance with the transition detection signal mtd.

The refresh determination circuit 81 asynchronously receives the refresh request signal ref-req and the transition detection signal mtd. Thus, when performing refreshing in response to the refresh request signal ref-req during the test mode, the desired operation pattern is not repeated. Accordingly, in the test mode, the refresh determination circuit 81 generates the refresh start signal ref-start and the refresh state signal ref-state in accordance with the transition detection signal mtd. When the refresh operation is completed and the refresh state signal ref-state is reset, the internal command generation circuit 82 generates the read/write start signal rw-start in accordance with the transition detection signal mtd.

In the test mode, using the generation of the transition detection signal mtd as a trigger, the refresh operation is started to simulate and reproduce the worst pattern so that the external access time can be measured to evaluate the read/write operation.

However, the prior art DRAM 50 has the problems described below.

[1: Problem When Detecting a Deficient Mode]

One problem (deficient mode) of the DRAM 50, for example, when there are successive external accesses, is an operation delay in the device (resulting from process fluctuation, temperature fluctuation, or insufficient voltage margin) that prolongs the cycle length. As a result, the DRAM 50 may not be able to shift to the read/write operation for the next cycle.

Fig. 7 is a waveform chart illustrating such a deficient mode. Fig. 7 illustrates an example in which the transition detection signal mtd is generated when the chip enable signal /CE goes low, the output enable signal /OE goes high, or the address signal ADD (A0 and A1) changes.

When the chip enable signal /CE goes low, the transition detection signal mtd is generated. In accordance with the transition detection signal mtd, the read/write start signal rw-start and the read/write state signal rw-state are generated. This performs the read/write operation.

Then, when the output enable signal /OE goes high, the transition detection signal mtd is generated. In this state, for example, when there is an operation delay in the device, the next cycle cannot be entered. Thus, the read/write start signal rw-start and the read/write state signal rw-state are not generated (the broken lines in Fig. 7 illustrate normal operation).

When there is a deficient mode such as in Fig. 7 and if the address signal ADD changes after the output enable signal /OE goes high as shown in Fig. 8, the read/write start signal rw-start and the read/write state signal rw-state are generated in accordance with the transition detection signal mtd.

In this case, since the read/write operation is started, a deficiency may not be detected even if there actually is a deficient mode. Thus, device evaluation cannot be performed accurately in the prior art.

[Deficiency Related With Test Mode]

In the test mode, the refresh start signal ref-start is generated in accordance with the transition detection signal mtd to start the refresh operation. Thus, during the test mode, a test in the desired operation pattern may not be performed since the refresh operation is not performed during the normal mode.

Fig. 9 is a waveform diagram illustrating an example of an operation pattern during the normal mode. Fig. 9 shows the operation pattern when there is an external request for the write operation and an internal request for the refresh operation and the refresh operation is performed first (worst pattern). In this example, the transition detection signal mtd is generated when the chip enable signal /CE goes low and the write enable signal /WE goes high. In the example of Fig. 9, the write operation is performed when the chip enable signal /CE goes low.

Fig. 10 is a waveform diagram illustrating an example in which the operation pattern of Fig. 9 is performed in the test mode.

In the example of Fig. 10, the transition detection signal mtd is generated when the chip enable signal /CE goes low. The refresh start signal ref-start is generated and the refresh operation is started in accordance with the transition detection signal mtd. When the refresh operation is completed, the read/write start signal rw-start (more specifically, write start signal) is generated and the write operation is started in accordance with the transition detection signal mtd.

Subsequent to the completion of the write operation, when the write enable signal /WE goes high and the transition detection signal mtd is generated in accordance with the write enable signal /WE, the refresh operation is performed for the second time in accordance with the transition detection signal mtd. Accordingly, in the prior art test mode, since the second refresh operation is performed unintentionally, the operation pattern in the normal mode of Fig. 9 cannot be reproduced.

Fig. 11 is a waveform diagram illustrating an example of a further operation pattern in the normal mode. Fig. 11 shows an operation pattern when there are requests for the write operation and the refresh operation at the same time, and the read operation is performed after the write operation. In this example, the transition detection signal mtd is generated when the chip enable signal /CE goes low, the write enable signal /WE goes high, and the output enable signal /OE goes high (not shown). In the example of Fig. 11, the write operation is started when the chip enable signal /CE goes low, and the read operation is started when the output enable signal /OE goes low.

Fig. 12 is a waveform chart illustrating an example when the operation of Fig. 11 is performed in the test mode. The transition detection signal mtd is generated when the chip enable signal /CE goes low. The refresh start signal ref-start is generated and the refresh operation is started in accordance with the signal mtd. When the refresh operation is completed, the read/write start signal rw-start (more specifically, write start signal) is generated and the write operation is started in accordance with the transition detection signal mtd, which functions as a trigger for starting the refresh operation.

Subsequent to the completion of the write operation, when the write enable signal /WE goes high, the transition detection signal mtd is generated in accordance with the write enable signal /WE. The refresh operation is performed for the second time when the refresh start signal ref-start is generated in accordance with the transition detection signal mtd. When the refresh operation is completed, the read/write start signal rw-start (more specifically, read start signal) is generated in accordance with the transition detection signal mtd, which is the trigger of the second refresh operation, to start the read operation.

Accordingly, in the example of Fig. 12, since the second refresh operation is performed unintentionally, the operation pattern in the normal mode of Fig. 11 cannot be reproduced in the test mode.

In the prior art, when an unintentional refresh operation is performed during the test mode, the characteristic evaluation is conducted with an operation pattern differing from the actual pattern. Thus, the device cannot be properly evaluated. When the test mode is performed, power draw increases since an unnecessary refresh operation is performed. Therefore, in accordance with the test result, the guaranteed operation may be over-evaluated or normal functioning may be erroneously determined as abnormal functioning. In other words, in the prior art, the testing cannot be performed with the intended operation pattern, and the device evaluation cannot be performed properly.

According to one aspect of the present invention there is a semiconductor memory device including first and second access modes, a test mode, and an entry signal generation circuit for generating a first entry signal used to enter the first access mode using a plurality of input signals, the first access mode being an external access mode and the second access mode being an internal refresh mode, and a control circuit connected to the entry signal generation circuit to generate a first mode trigger signal in response to the first entry signal,

and when the control circuit receives a second entry signal to enter the second access mode, the control circuit generates a second mode trigger signal in response to the second entry signal, the semiconductor memory device characterized in that the entry signal generation circuit receives a selection control signal in the test mode and invalidates at least one of said input signals in a selective manner in accordance with the selection control signal, thereby inhibiting the generation of the first entry signal.

According to an embodiment of the present invention there is a semiconductor memory device characterized in that the entry signal generation circuit generates the first entry signal used to enter the first access mode or the second access mode using the plurality of input signals, and the control circuit generates the first mode trigger signal, which is used to start the first access mode, in response to the first entry signal and generates the second mode trigger signal, which is used to start the second access mode, in response to the first entry signal.

According to an embodiment of the present invention there is a semiconductor memory device characterized in that the entry signal generation circuit generates the first entry signal used to enter the first access mode and a third entry signal used to enter the second access mode using the plurality of input signals,

the control circuit generates the first mode trigger signal, which is used to start the first access mode, in response to the first entry signal and generates the second mode trigger signal, which is used to start the second access mode, in response to the third entry signal.

According to further aspect of the present invention there is a method for testing a semiconductor memory device having a first access mode, a second access mode, and a test mode, the first access mode being an external access mode and the second access mode being an internal refresh mode, the method comprising the steps of:

  • receiving a plurality of input signals;
  • generating an entry signal used to enter the first access mode or the second access mode using the input signals;
  • characterised by the steps of:
    • receiving a selection control signal in the test mode; and
    • invalidating at least one of said input signals in a selective manner in accordance with the selection control signal, thereby inhibiting the generation of the entry signal.

According to an embodiment of the present invention there is a method for testing a semiconductor memory device further characterized in that:

  • said generating the entry signal includes:
    • generating a first entry signal used to enter the first access mode using the input signals, and
    • generating a second entry signal used to enter the second access mode using the input signals;
and said invalidating at least one of said input signals in a selective manner in accordance with the selection control signal inhibits the generation of the first entry signal or the second entry signal.

According to an embodiment of the present invention there is a method for testing a semiconductor memory device characterized in that:

  • said generating the entry signal includes selecting at least one of the input signals and detecting transition of the selected at least one of the input signals to generate the entry signal for starting one of the access modes.

The invention and preferred objects and advantages thereof, may best be understood by reference to the following description of the certain exemplifying embodiments together with the accompanying drawings in which:

  • Fig. 1 is a schematic block circuit diagram of a prior art semiconductor memory device;
  • Fig. 2 is a schematic block circuit diagram of a memory control circuit incorporated in the semiconductor memory device of Fig. 1;
  • Fig. 3 is a waveform chart illustrating the operation principle of a transition detector of the semiconductor memory device of Fig. 1;
  • Figs. 4 and 5 are waveform charts illustrating the operation principle of the memory control circuit of Fig. 2;
  • Fig. 6 is a waveform chart illustrating a test mode of the semiconductor memory device of Fig. 1;
  • Fig. 7 is a waveform chart illustrating an example of a deficient mode of the semiconductor memory device of Fig. 8;
  • Fig. 8 is a waveform chart illustrating an example of an operation pattern in the prior art;
  • Fig. 9 is a waveform chart illustrating an example of an operation pattern in the prior art;
  • Fig. 10 is a waveform chart illustrating a prior art test mode for the operation pattern of Fig. 9;
  • Fig. 11 is a waveform diagram illustrating an example of an operation pattern in the prior art;
  • Fig. 12 is a waveform chart illustrating a prior art test mode for the operation pattern of Fig. 11;
  • Fig. 13 is a schematic block circuit diagram of a semiconductor memory device according to a first embodiment of the present invention;
  • Fig. 14 is a schematic circuit diagram of a transition detector in the semiconductor memory device of Fig. 13;
  • Fig. 15 is a schematic circuit diagram of a refresh determination circuit in the semiconductor memory device of Fig. 13;
  • Fig. 16 is a waveform diagram illustrating deficient mode detection in the first embodiment;
  • Fig. 17 is a waveform diagram illustrating a test mode in the first embodiment;
  • Fig. 18 is a schematic block circuit diagram of a semiconductor memory device according to a second embodiment of the present invention;
  • Fig. 19 is a schematic block circuit diagram of a memory control circuit of the semiconductor memory device of Fig. 18;
  • Fig. 20 is a schematic circuit diagram of a transition detector in the semiconductor memory device of Fig. 18;
  • Fig. 21 is a schematic circuit diagram of a further transition detector in the semiconductor memory device of Fig. 18;
  • Fig. 22 is a waveform diagram illustrating deficient mode detection in the second embodiment; and
  • Figs. 23 and 24 are waveform diagrams illustrating a test mode in the second embodiment.

In the drawings, like numerals are used for like elements throughout.

Fig. 13 is a schematic block circuit diagram of an input circuit section of a semiconductor memory device (DRAM) 100 according to a first embodiment of the present invention. The DRAM 100 is provided with a self-refreshing function.

The DRAM 100 receives a plurality of control signals CTL and a plurality (only two bits shown in Fig. 13) of external address signals ADD via external terminals. The control signals CTL include a chip enable signal /CE, a write enable signal /WE, and an output enable signal /OE. The external address signals ADD include address signals A0 and A1. The signals /CE, /WE, /OE, A0, and A1 are input to a transition detection signal generation circuit 20 via input buffers 11, 12, 13, 14, and 15, respectively. The input buffers 11 to 15 function as initial input stage circuits, which convert an input signal to a signal having a level corresponding to the internal voltage of the device. Further, the input buffers 11 to 15 are each configured by a CMOS inverter or a C/M differential amplifier.

The transition detection signal generation circuit 20 includes a plurality of (five in Fig. 13) transition detectors (TD) 21 to 25 and a pulse synthesizing circuit 26.

The transition detectors 21, 22, and 23 respectively detect the transition (transition between a high level and a low level) of the control signals CTL (/CE, /WE, and /OE) to generate input detection signals ceb, web, and oeb. The transition detectors 24 and 25 respectively detect the transition of the states (change of each bit) of the input external address signal ADD (A0 and A1) to generate address detection signals ad0 and ad1. The detection signals ceb, web, oeb, ad0, and ad1 are provided to the pulse synthesizing circuit 26.

The pulse synthesizing circuit 26 logically synthesizes the detection signals ceb, web, oeb, ad0, and ad1 to generate a transition detection signal mtds (first entry signal) for performing a read/write process, or an external access (first access mode). The transition detection signal mtds is provided to the memory control circuit 27.

A code generation circuit 30 is connected to the pulse synthesizing circuit 26. In accordance with a test signal, which is provided from a test circuit (not shown), the code generation circuit 30 provides a pulse generation control code (selection control signal) en-code, which is prestored in an internal register (not shown), to a pulse synthesizing circuit 26. The pulse generation control code en-code represents code information set by an input signal (not shown) provided from a plurality of external terminals.

More specifically, the pulse generation control code en-code masks the detection signals ceb, web, oeb, ad0, and ad1, which are provided from a pulse synthesizing circuit 26, when necessary. That is, among the detection signals ceb, web, oeb, ad0, and ad1, the pulse synthesizing circuit 26 selects the signal used for the logic synthesizing in accordance with the pulse generation control code en-code. The signal invalidated by the pulse generation control code en-code does not generate the transition detection signal mtds.

The memory control circuit 27 receives the transition detection signal mtds from the pulse synthesizing circuit 26 and generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of an activated memory cell corresponds to a predetermined read/write address, which is assigned by the external address signal ADD. The timing signal wl-timing is provided to a memory core 29.

A refresh timer 28 is connected to the memory control circuit 27. The refresh timer 28 generates a refresh request signal ref-req (second entry signal) for performing a refresh process, or an internal access (second access mode) at predetermined time intervals and provides the refresh request signal ref-req to the memory control circuit 27.

The memory control circuit 27 receives the refresh request signal ref-req and generates a word line activation timing signal wl-timing to activate a word line of a memory cell. The word line of an activated memory cell corresponds to a predetermined refresh address, which is output from an internal address counter (not shown). The memory control circuit 27 further receives a test signal test from a test circuit (not shown) to conduct a test in a test mode in accordance with the test signal test.

The configuration of the memory control circuit 27 is similar to that of the memory control circuit 77 of Fig. 2 and includes a refresh determination circuit 81, an internal command generation circuit (mode trigger generation circuit) 82, and a timing generator (signal generation circuit) 83. For the sake of brevity, elements used in the memory control circuit 77 will not be described below.

In the first embodiment, the refresh determination circuit 81 receives the refresh request signal ref-req from the refresh timer 28 and the transition detection signal mtds from the pulse synthesizing circuit 26. The refresh determination circuit 81 determines the input timing of the refresh request signal ref-req and the transition detection signal mtds, which are asynchronously input, to determine the level of priority of the refresh operation and the read/write operation. In accordance with the priority level, the refresh determination circuit 81 generates a refresh start signal ref-start (second mode trigger signal).

In this state, the refresh determination circuit 81 receives the test signal test from the test circuit. When receiving the transition detection signal mtds, the refresh determination circuit generates a refresh start signal ref-start in response to a transition detection signal mtds.

Fig. 15 shows an example of the refresh determination circuit 81, which receives the transition detection signal mtds generated in accordance with the pulse generation control code en-code.

The internal command generation circuit 82 receives the transition detection signal mtds from the pulse synthesizing circuit 26. The internal command generation circuit 82 generates the read/write start signal rw-start (first mode trigger signal) in response to the transition detection signal mtds.

The timing generator 83 receives the refresh start signal ref-start from the refresh determination circuit 81 and the read/write start signal rw-start from the internal command generation circuit 82. The timing generator 83 generates the word line activation timing signal wl-timing (internal operation signal) in correspondence with each of the signals ref-start and rw-start.

Fig. 14 is a schematic circuit diagram illustrating an example of the transition detection signal generation circuit 20.

For example, when the chip enable signal /CE goes low, the transition detector 21 generates a one shot pulse, the pulse width of which depends on the delay time of a delay circuit. The transition detectors 22 and 23 generate a one shot pulse when the write enable signal /WE and the output enable signal /OE go high, respectively.

The transition detector 24 generates a one shot pulse when the address signal A0 goes high or low. Transition detectors including the transition detector 25 that detect changes in address signals have the same configuration as the transition detector 24.

The pulse synthesizing circuit 26 includes, for example, a plurality of signal selection circuits (in Fig. 14, NAND circuits 26a, 26b, 26c, and 26d) and a signal synthesizing circuit (in Fig. 14, a NAND circuit 26e). The signal selection circuits 26a to 26d are respectively provided for the transition detectors 21 to 24. The signal synthesizing circuit 26e logically synthesizes the output signals of the signal selection circuits and outputs the logically synthesized signal.

More specifically, the NAND circuits 26a-26d respectively receive the detection signals ceb, web, oeb, and ad0 from the transition detectors 21 to 24 and pulse generation control codes en-code (in Fig. 14, en-ceb, en-web, en-oeb, and en-ad0), which include the corresponding code information.

For example, when the pulse generation control code en-ceb goes low, the NAND circuit 26a invalidates the detection signal ceb of the transition detector 21. That is, when the NAND circuit 26a receives the low pulse generation control code en-ceb, the output of the NAND circuit 26a is fixed at a high level. In the same manner, when the pulse generation control codes en-web, en-oeb, en-ad0 go low, the NAND circuits 26b to 26d respectively invalidate the detection signals web, oeb, and ad0 from the transition detectors 22 to 24.

In this manner, the pulse synthesizing circuit 26 logically synthesizes the detections signals ceb, web, oeb, and ad0 in a selective manner in accordance with the pulse generation control code to generate the transition detection signal mtds.

The operation of the DRAM 100 in the first embodiment will now be discussed. Fig. 16 is a waveform chart illustrating an example in which a deficient mode is detected.

In the example of Fig. 16, the transition detection signal mtds is generated when the chip enable signal /CE goes low and the output enable signal /OE goes high, and the transition detection signal mtds is not generated when the external address signals ADD (A0, A1) change. That is, in the transition detection signal generation circuit 20, the address detection signals ad0 and ad1, which are provided to the pulse synthesizing circuit 26, are invalidated by the pulse generation control code en-code.

In Fig. 16, the transition detection signal mtds is generated when the chip enable signal /CE goes low. The read/write start signal rw-start and the read/write state signal rw-state are generated in accordance with the transition detection signal mtds to perform the read/write operation.

Then, the transition detection signal mtds is generated when the output enable signal /OE goes high. In this state, when an operational delay occurs in the device due to noise, process fluctuation, temperature fluctuation, and insufficient voltage margin, the read/write operation cannot be entered in the next cycle. In other words, the read/write start signal rw-start and the read/write state signal rw-state are not generated (the single-dot broken lines in Fig. 16 indicate normal operation).

After the output enable signal /OE goes high, the external address signal ADD (address value) changes. However, the address detection signals ad1 and ad1 are invalidated by the pulse generation control code en-code. That is, the transition detection signal mtds (double-dot broken lines in Fig. 16) is not generated even if the external address signal ADD changes. Thus, the read/write start signal rw-start and the read/write state signal rw-state are not generated.

Accordingly, even if such a deficient mode exists (deficiency in which a read/write operation that should be performed is not performed), the recurrence of an operation pattern in a deficient mode is enabled in the first embodiment. Thus, a deficiency of the device is accurately detected. When the control signals shift, the generation of the transition detection signal mtds may be stopped to detect the existence of a deficient mode.

Fig. 17 is a waveform chart illustrating an example of the test mode. In the example of Fig. 17, the operation pattern when the write operation is performed after the refresh operation (worst pattern) is repeated in the test mode (refer to Fig. 9). In this example, the pulse generation control code en-code inhibits the generation of the transition detection signal mtds when the write enable signal /WE goes high.

The transition detection signal mtds is generated when the chip enable signal /CE goes low. The transition detection signal mtds generates the refresh start signal ref-start and starts the refresh operation. When the refresh operation is completed, the read/write start signal rw-start (more specifically, the write start signal) is generated in accordance with the transition detection signal mtds, which functions as a trigger that starts the refresh operation. The read/write start signal rw-start starts the write operation.

After the write operation is completed, the write enable signal /WE goes high. In this state, the pulse generation control code en-code invalidates the detection signal web of the transition detector 22. That is, the transition detection signal mtds (double-dot broken lines in Fig. 17) is not generated even if the write enable signal /WE is shifted. Thus, the refresh start signal ref-start is not generated, and the refresh operation is not performed.

In the first embodiment, the refresh operation is performed only, for example, when the chip enable signal /CE goes low in accordance with the pulse generation control code en-code. Accordingly, in the test mode, an unintentional refresh operation is not performed and the worst pattern of Fig. 9 is simulated and repeated. Thus, the desired pattern, such as the worst pattern, is repeated in the test mode and the device evaluation is accurately performed.

The DRAM 100 of the first embodiment has the advantages described below.

  1. (1) The pulse synthesizing circuit 26 generates the transition detection signal mtds by logically synthesizing the input detection signals ceb, web, and oeb and the address detection signals ad0 and ad1 in accordance with the pulse generation control code en-code in a selective manner. This enables facilitated and accurate detection of the existence of a deficient mode.
  2. (2) When performing the test mode, the pulse synthesizing circuit 26 generates the transition detection signal mtds by logically synthesizing the detection signals ceb, web, oeb, ad0, and ad1 in accordance with the pulse generation control code en-code in a selective manner. This prevents an unnecessary refresh operation from being performed. Thus, the desired pattern, such as the worst pattern, is simulated and repeated. Accordingly, the device evaluation is performed more accurately.
  3. (3) The pulse generation control code en-code controls the transition detection signal mtds, which is generated by the pulse synthesizing circuit 26. Thus, the circuit scale is not increased from the prior art configuration.

Fig. 18 is a block circuit diagram of an input circuit section of a semiconductor memory device (DRAM) 200 according to a second embodiment of the present invention. In the DRAM 200 of the second embodiment, the pulse synthesizing circuit 26 and the memory control circuit 27 in the transition detection signal generation circuit 20 of the first embodiment are partially modified.

In the second embodiment, a transition detection signal generation circuit 31 includes a plurality of (in Fig. 18, five) transition detectors 21 to 25 and a pulse synthesizing circuit 32.

The pulse synthesizing circuit 32 uses detection signals ceb, web, oeb, ad0, and ad1 of the transition detectors 21 to 25 to generate a command transition detection signal mtdcs (first entry signal) and a refresh transition detection signal mtdrs (second or third entry signal). More specifically, the pulse synthesizing circuit 32 logically synthesizes the detection signals ceb, web, oeb, ad0, and ad1 in a selective manner in accordance with the pulse generation control code en-code to generate the command transition detection signal mtdcs and the refresh transition detection signal mtdrs.

Fig. 19 is a schematic block circuit diagram of the memory control circuit 33 of Fig. 18. The memory control circuit 33 includes a refresh determination circuit 41, an internal command generation circuit (mode trigger generation circuit) 42, and a timing generator (internal operation signal generation circuit) 43.

The refresh determination circuit 41 receives the refresh transition detection signal mtdrs from the pulse synthesizing circuit 32, the refresh request signal ref-req from the refresh timer 28, and the test signal test from a test circuit (not shown).

When there is more than one request, the refresh determination circuit 41 determines the priority level of the refresh operation and the read/write operation from the input timing of the refresh request signal ref-req and the transition detection signal mtdrs, which are asynchronously input.

More specifically, the refresh determination circuit 41 generates the refresh start signal ref-start and the refresh state signal ref-state in response to the refresh request signal ref-req. When receiving the transition detection signal mtdrs before the refresh request signal ref-req, the refresh determination circuit 41 generates the refresh start signal ref-req and the refresh state signal ref-state after the read/write state signal rw-state are reset.

The internal command generation circuit 42 receives the transition detection signal mtdcs from the pulse synthesizing circuit 32. In response to the transition detection signal mtdcs, the internal command generation circuit 42 generates the read/write start signal rw-start. When receiving the refresh state signal ref-state from the refresh determination circuit 41, the internal command generation circuit 42 generates the read/write start signal rw-start after the refresh state signal ref-state is reset.

The timing generator 43 receives the refresh start signal ref-start from the refresh determination circuit 41 and the read/write start signal rw-start from the internal command generation circuit 42. The timing generator 43 generates the word line activation timing signal wl-timing, which activates the word line corresponding to a predetermined refresh address, in response to the refresh start signal ref-start. The activated word line corresponds to the predetermined refresh address generated by an internal address counter (not shown).

In response to the read/write start signal rw-start, the timing generator 43 generates the read/write state signal rw-state and the word line activation timing signal wl-timing, which activates a word line. The activated word line corresponds to a predetermined read/write address assigned by the external address signal ADD.

In addition to the word line activation timing signal wl-timing, the timing generator 43 generates various internal operation signals including a sense amplifier activation timing signal, which activates a sense amplifier. Only the word line activation timing signal wl-timing will be discussed below.

Fig. 20 is a circuit diagram showing an example of the transition detection signal generation circuit 31. The pulse synthesizing circuit 32 includes a plurality of signal selection circuits (NAND circuits 32a to 32d), which generate the command transition detection signal mtdcs, and a signal synthesizing circuit (NAND circuit 32e). Further, the pulse synthesizing circuit 32 includes a plurality of signal selection circuits (NAND circuits 32f to 32i), which generate the refresh transition detection signal mtdrs, and a signal synthesizing circuit (NAND circuit 32j).

The signal selection circuits are provided in correspondence with each transition detector of the transition detection signal generation circuit 31. In Fig. 20, for the sake of brevity, the NAND circuits 32a to 32d and 32f to 32i are shown corresponding to the transition detectors 21 to 24, respectively. The NAND circuits 32a-32d respectively receive the detection signals ceb, web, oeb, and ad0 from the transition detectors 21 to 24 and pulse generation control codes en-code (en-ceb1, en-web1, en-oeb1, and en-ad01), which include the corresponding code information.

For example, when the pulse generation control code en-ceb1 goes low, the NAND circuit 32a invalidates the detection signal ceb of the transition detector 21. That is, when the NAND circuit 32a receives the low pulse generation control code en-ceb1, the output of the NAND circuit 32a is fixed at a high level. In the same manner, when the pulse generation control codes en-web1, en-oeb1, and en-ad01 go low, the NAND circuits 32b to 32d respectively invalidate the detection signals web, oeb, and ad0 from the transition detectors 22 to 24.

The NAND circuits 32f-32i respectively receive the detection signals ceb, web, oeb, and ad0 from the transition detectors 21 to 24 and pulse generation control codes en-code (en-ceb2, en-web2, en-oeb2, and en-ad02), which include the corresponding code information. For example, when the pulse generation control codes en-ceb2, en-web2, en-oeb2, en-ad02 go low, the associated NAND circuits 32f to 32i respectively invalidate the detection signals ceb, web, oeb, and ad0 from the transition detectors 21 to 24.

The pulse synthesizing circuit 32 logically synthesizes the detection signals ceb, web, oeb, and ad0 in a selective manner in accordance with the pulse generation control codes en-code (en-ceb1, en-web1, en-oeb1, en-ad01, en-ceb2, en-web2, en-oeb2, and en-ad02) to generate the command transition detection signal mtdcs and the refresh transition detection signal mtdrs.

The operation of the DRAM 200 will now be discussed. Fig. 22 is a waveform chart illustrating an example in which a deficient mode is detected. Fig. 22 illustrates an example in which the transition detection signal mtdcs is not generated in accordance with changes in the external address signal ADD (A0 and A1) In this case, the pulse generation control code en-code invalidates the detection signals ad0 and ad1 input to the pulse synthesizing circuit 32.

Further, the refresh transition detection signal mtdrs is not generated when one of the chip enable signal /CE, the output enable signal /OE, and the external address signal ADD (A0 and A1) shifts levels. In this case, the pulse generation control code en-code invalidates the detection signals ceb, web, oeb, ad0, and ad1.

When the chip enable signal /CE goes low, the command transition detection signal mtdcs is generated, and the read/write start signal rw-start and the read/write state signal rw-state are generated in accordance with the detection signal mtdcs. This performs the read/write operation.

Then, the command transition detection signal mtdcs is generated when the output enable signal /OE goes high. In this state, when an operational delay occurs in the device, the read/write operation cannot be entered in the next cycle. That is, when an operational delay occurs, the read/write start signal rw-start and the read/write state signal rw-state, which are normally generated, are not generated (the single-dot broken lines in Fig. 22 indicate normal operation).

After the output enable signal /OE goes high, the external address signal ADD (address value) changes. However, the address detection signals ad0 and ad1 are invalidated by the pulse generation control code en-code. Thus, the command transition detection signal mtdcs (double-dot broken lines in Fig. 22) is not generated even if the external address signal ADD changes. As a result, the read/write start signal rw-start and the read/write state signal rw-state are not generated.

Accordingly, in the second embodiment, even if a deficient mode exists, the recurrence of an operation pattern in a deficient mode is enabled. Thus, a deficiency of the device is accurately detected. When the control signals CTL (/CE, /WE, /OE) shift levels, the generation of the command transition detection signal mtdcs may be stopped to detect the existence of a deficient mode.

Fig. 23 is a waveform chart illustrating an example of the test mode. In the example of Fig. 23, the worst pattern is repeated in the test mode (refer to Fig. 9). In the example of Fig. 23, the command transition detection signal mtdcs is generated when the chip enables signal /CE goes low or when the write enable signal /WE goes high. The refresh transition detection signal mtdrs is generated only when the chip enable signal /CE goes low. When the write enable signal /WE goes high, the pulse generation control code en-code inhibits the generation of the refresh transition detection signal mtdrs.

The transition detection signals mtdcs and mtdrs are generated when the chip enable signal /CE goes low, and the refresh start signal ref-start is generated (refresh operation is started) in accordance with the refresh transition detection signal mtdrs. When the refresh operation ends, the read/write start signal rw-start (write start signal) is generated in accordance with the command transition detection signal mtdcs, which is generated when the chip enable signal /CE goes low, to start the write operation.

After the write operation ends, the write enable signal /WE goes high. Then, the pulse generation control code en-code invalidates the detection signal web of the transition detector 22. Thus, the refresh detection signal mtdrs (shown by double-dot broken lines in Fig. 23) is not generated even when the write enable signal /WE is shifted. As a result, the refresh start signal ref-start is not generated and the refresh operation is not performed.

In the second embodiment, the refresh operation is performed only when the chip enable signal /CE goes low. Accordingly, the worst pattern of Fig. 9 is simulated and repeated in the test mode, and the device is accurately evaluated.

Fig. 24 is a waveform diagram illustrating a further example of a test mode. Fig. 24 shows an example of the worst pattern in which the read operation is performed after the write operation is completed. The worst pattern is repeated in the test mode (refer to Fig. 11).

In Fig. 24, the command transition detection signal mtdcs, for example, is generated when the chip enable signal /CE goes low, when the write enable signal /WE goes high, or when the output enable signal /OE goes high (not shown). The refresh transition detection signal mtdrs is generated when the chip enable signal /CE goes low or when the output enable signal /OE goes high (not shown). The pulse generation control code en-code inhibits the generation of the refresh transition detection signal mtdrs when the write enable signal /WE goes high.

The transition detection signals mtdcs and mtdrs are generated when the chip enable signal /CE goes low, and the refresh start signal ref-start is generated (refresh operation is started) in accordance with the refresh transition detection signal mtdrs. When the refresh operation ends, the read/write start signal rw-start (write start signal) is generated in accordance with the command transition detection signal mtdcs, which is generated when the chip enable signal /CE goes low, to start the write operation.

After the write operation ends, the write enable signal /WE goes high. In this state, the pulse generation control code en-code invalidates the detection signal web of the transition detector 22. Thus, the refresh detection signal mtdrs (shown by double-dot broken lines in Fig. 24) is not generated even when the write enable signal /WE is shifted. As a result, the refresh start signal ref-start is not generated and the refresh operation is not performed.

Then, when the output enable signal /OE goes low, the read/write start signal rw-start (more specifically, read start signal) is generated in accordance with the command transition detection signal mtdcs, which is generated when the write enable signal /WE goes high. The read operation is started in accordance with the start signal rw-start.

In the test mode of the second embodiment, the read operation is performed by the command transition detection signal mtdcs while inhibiting unnecessary refresh operations. Accordingly, the operating pattern of Fig. 11 (the write operation performed successively after the refresh operation when there is more than one access request at the same time and the read operation performed successively after the write operation) is simulated and repeated in the test mode.

The DRAM 200 of the second embodiment has the advantages described below.

  1. (1) The pulse synthesizing circuit 32 logically synthesizes the detection signals ceb, web, oeb, ad0, and ad1 from the associated transition detector 21 to 25 in a selective manner in accordance with the pulse generation control code en-code to generate the command transition detection signal mtdcs and the refresh transition detection signal mtdrs. The command transition detection signal mtdcs is used to process an external access (read/write operation). The refresh transition detection signal mtdrs is used to process an internal access. Since unnecessary refresh operations are not performed in the test mode, the intended operating pattern (read/write operation) is performed in a desirable manner.

It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms. Particularly, it should be understood that the present invention may be embodied in the following forms.

In each of the above embodiments, the worst pattern, in which the write operation is performed after the refresh operation, is repeated in the test mode. However, the worst pattern, in which the read operation is performed after the refresh operation, may be simulated and repeated in the test mode to evaluate a device.

In each of the above embodiments, the control signal CTL input from an external device is not restricted to the chip enable signal /CE, the write enable signal /WE, and the output enable signal /OE.

In each of the above embodiments, for the sake of brevity, only the address signals A0 and A1 are shown as the external address ADD in Figs. 13 and 18. However, the external address signal ADD includes multiple bits.

In each of the above embodiments, the pulse generation control code en-code may be randomly accessed via an external terminal (exclusive test terminal or another terminal that is not used when a test is conducted) when a command is input. In such a case, the pulse generation control code en-code enables the masking of certain edges (rising or falling) of the detection signals ceb, web, oeb, ad0, and ad1, which are output from the transition detectors 21 to 25.

When evaluating a device, the signals that are logically synthesized in the pulse synthesizing circuits 26 and 32 may be changed when required to set the deficient mode existing in the device (DPAM).

In each of the embodiments, the operating patterns simulated and repeated in the test mode are only examples, and other operating patterns may be repeated in the test mode to evaluate a device.

The configuration of the transition detection signal generation circuit 20 in Fig. 14 and the configuration of the refresh determination circuit 81 in Fig. 15 are only examples. The present invention is not restricted to such examples.

In the second embodiment, the transition detection signal generation circuit 31 of Fig. 20 may be replaced by a transition detection signal generation circuit 31, which is shown in Fig. 21. A pulse synthesizing circuit 34 is employed when evaluating a device in the test mode.

More specifically, the pulse synthesizing circuit 34 includes a plurality of inverter circuits 34a to 34d, which generate the command transition detection signal mtdcs, and a single signal synthesizing circuit (NAND circuit 34e). The pulse synthesizing circuit 34 includes a plurality of signal selection circuits (NAND circuits 32f to 32i), which generate the refresh transition detection signal mtdrs, and a single signal synthesizing circuit (NAND circuit 32j). The pulse synthesizing circuit 34 logically synthesizes the detection signals ceb, web, oeb, and ad0 in a selective manner in accordance with the pulse generation control code en-code (en-ceb, en-web, en-oeb, and en-ad0) to generate the refresh transition detection signal mtdrs.

The present examples and embodiments are to be considered as illustrative and not restrictive.


Anspruch[de]
Eine Halbleiterspeichervorrichtung, umfassend erste und zweite Zugriffsmodi, einen Testmodus und eine Eintrittssignalerzeugungsschaltung (20; 31) zum Erzeugen eines ersten Eintrittssignals (mtds; mtdcs), das verwendet wird, um in den ersten Zugriffsmodus einzutreten, wobei eine Mehrzahl von Eingangssignalen (ceb, web, oeb, ad0) verwendet wird, wobei der erste Zugriffsmodus ein externer Zugriffsmodus ist und der zweite Zugriffsmodus ein interner Auffrischmodus ist, und eine Steuerschaltung (27; 33), die mit der Eintrittssignalerzeugungsschaltung verbunden ist, um ein Triggersignal (rw-start) für einen ersten Modus in Antwort auf das erste Eintrittssignal zu erzeugen, und, wenn die Steuerschaltung ein zweites Eintrittssignal (ref-req) empfängt, um in den zweiten Zugriffsmodus einzutreten, erzeugt die Steuerschaltung ein Triggersignal (ref-start) für einen zweiten Modus in Antwort auf das zweite Eintrittssignal, wobei die Halbleiterspeichervorrichtung dadurch gekennzeichnet ist, dass die Eintrittsignalerzeugungsschaltung (20; 31) im Testmodus ein Auswahlsteuersignal (en-code) empfängt und mindestens eines der Eingangssignale auf selektive Weise ungültig macht in Übereinstimmung mit dem Auswahlsteuersignal (en-code), wodurch die Erzeugung des ersten Eintrittssignals gesperrt wird. Die Halbleiterspeichervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass das Auswahlsteuersignal Codeinformation in Bezug auf die Eingangssignale umfasst, die zu verwenden sind. Die Halbleiterspeichervorrichtung nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, dass die Eintrittssignalerzeugungsschaltung umfasst: eine Mehrzahl von Übergangsdetektoren (21-25), wobei jeder einen Übergang eines zugehörigen der Eingangssignale erkennt, um ein Erkennungssignal zu erzeugen; und eine Pulssynthetisierungsschaltung (26; 32), die mit den Übergangsdetektoren verbunden ist, um das erste Eintrittssignal zu erzeugen, wobei die Erkennungssignale in Übereinstimmung mit dem Auswahlsteuersignal verwendet werden. Die Halbleiterspeichervorrichtung nach einem der Ansprüche 1, 2 oder 3, dadurch gekennzeichnet, dass die Steuerschaltung das zweite Eintrittssignal ungültig macht in Übereinstimmung mit einem Testsignal, das verwendet wird, um in den Testmodus einzutreten, und das Triggersignal für einen zweiten Modus in Antwort auf das erste Eintrittssignal erzeugt. Die Halbleiterspeichervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass die Eintrittssignalerzeugungsschaltung (31) ein drittes Eintrittssignal (mtdrs) erzeugt, das verwendet wird, um in den zweiten Zugriffsmodus einzutreten, wobei die Eingangssignale in Übereinstimmung mit dem Auswahlsteuersignal verwendet werden. Die Halbleiterspeichervorrichtung nach Anspruch 5, dadurch gekennzeichnet, dass die Eintrittssignalerzeugungsschaltung umfasst: eine Mehrzahl von Übergangsdetektoren (21-25), wobei jeder einen Übergang eines zugehörigen der Eingangssignale erkennt, um ein Erkennungssignal zu erzeugen; und eine Pulssynthetisierungsschaltung (32), die mit den Übergangsdetektoren verbunden ist, um die ersten und dritten Eintrittssignale zu erzeugen, wobei die Erkennungssignale in Übereinstimmung mit dem Auswahlsteuersignal verwendet werden. Die Halbleiterspeichervorrichtung nach Anspruch 5 oder 6, dadurch gekennzeichnet, dass die Steuerschaltung das zweite Eintrittssignal ungültig macht in Übereinstimmung mit einem Testsignal, das verwendet wird, um in den Testmodus einzutreten, und das Triggersignal für den zweiten Modus in Antwort auf das dritte Eintrittssignal erzeugt. Die Halbleiterspeichervorrichtung nach einem der Ansprüche 5 bis 7, dadurch gekennzeichnet, dass die Steuerschaltung (33) umfasst: eine Modustriggererzeugungsschaltung (42), die mit der Eintrittssignalerzeugungsschaltung verbunden ist, um das Triggersignal für den ersten Modus in Antwort auf das erste Eintrittssignal zu erzeugen; eine Bestimmungsschaltung (41), die mit der Eintrittssignalerzeugungsschaltung verbunden ist, um das zweite Eintrittssignal in Übereinstimmung mit dem Testsignal ungültig zu machen und um das Triggersignal für den zweiten Modus in Antwort auf das dritte Eintrittssignal zu erzeugen; und eine Erzeugungsschaltung (43) für ein internes Betriebssignal, die mit der Modustriggererzeugungsschaltung und der Bestimmungsschaltung verbunden ist, um ein internes Betriebssignal in Übereinstimmung mit dem Triggersignal für den ersten Modus und dem Triggersignal für den zweiten Modus zu erzeugen. Die Halbleiterspeichervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass die Eingangssignale eine Mehrzahl von Steuersignalen und eine Mehrzahl von Adresssignalen umfassen. Die Halbleiterspeichervorrichtung nach Anspruch 1, des Weiteren gekennzeichnet durch eine Auswahlsignalerzeugungsschaltung (30), die mit der Eintrittssignalerzeugungsschaltung verbunden ist, um das Auswahlsteuersignal zu erzeugen. Die Halbleiterspeichervorrichtung nach Anspruch 1, des Weiteren gekennzeichnet durch einen Timer (28), der mit der Steuerschaltung verbunden ist, um das zweite Eintrittssignal zu erzeugen. Die Halbleiterspeichervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass der erste Zugriffsmodus ein Lesebetriebsmodus oder ein Schreibbetriebsmodus ist, und der zweite Zugriffsmodus ein Selbstauffrischbetriebsmodus ist. Die Halbleiterspeichervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass die Eintrittssignalerzeugungsschaltung (20) das erste Eintrittssignal (mtds) erzeugt, das verwendet wird, um in den ersten Zugriffsmodus oder den zweite Zugriffsmodus einzutreten, wobei die Mehrzahl von Eingangssignalen verwendet wird, und die Steuerschaltung (27) das Triggersignal (rw-start) für den ersten Modus erzeugt, welches verwendet wird, um den ersten Zugriffsmodus zu starten, in Antwort auf das erste Eintrittssignal, und das Triggersignal (ref-start) für den zweiten Modus erzeugt, welches verwendet wird, um den zweiten Zugriffsmodus zu starten, in Antwort auf das erste Eintrittssignal. Die Halbleiterspeichervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass die Eintrittssignalerzeugungsschaltung (31) das erste Eintrittssignal (mtdcs) erzeugt, das verwendet wird, um in den ersten Zugriffsmodus einzutreten, und ein drittes Eintrittssignal (mtdrs) erzeugt, das verwendet wird, um in den zweiten Zugriffsmodus einzutreten, wobei die Mehrzahl von Eingangssignalen verwendet wird, die Steuerschaltung (33) das Triggersignal (rw-start) für den ersten Modus erzeugt, welches verwendet wird, um den ersten Zugriffsmodus zu starten, in Antwort auf das erste Eintrittssignal, und das Triggersignal (ref-start) für den zweiten Modus erzeugt, welches verwendet wird, um den zweiten Zugriffsmodus zu starten, in Antwort auf das dritte Eintrittssignal. Ein Verfahren zum Testen einer Halbleiterspeichervorrichtung, die einen ersten Zugriffsmodus, einen zweiten Zugriffsmodus und einen Testmodus besitzt, wobei der erste Zugriffsmodus ein externer Zugriffsmodus ist und der zweite Zugriffsmodus ein interner Auffrischmodus ist, und wobei das Verfahren die Schritte umfasst: Empfangen einer Mehrzahl von Eingangssignalen (ceb, web, oeb, ad0); Erzeugen eines Eintrittssignals (mtds; mtdcs, mtdrs), das verwendet wird, um in den ersten Zugriffsmodus oder den zweiten Zugriffsmodus einzutreten, wobei die Eingangssignale verwendet werden; gekennzeichnet durch die Schritte: Empfangen eines Auswahlsteuersignals (en-code) im Testmodus; und Ungültigmachen mindestens eines der Eingangssignale auf selektive Weise, in Übereinstimmung mit dem Auswahlsteuersignal, wodurch die Erzeugung des Eintrittssignals gesperrt wird. Das Verfahren nach Anspruch 15, des Weiteren dadurch gekennzeichnet, dass: das Erzeugen des Eintrittssignals umfasst: Erzeugen eines ersten Eintrittssignals (mtdcs), das verwendet wird, um in den ersten Zugriffsmodus einzutreten, wobei die Eingangssignale verwendet werden, und Erzeugen eines zweiten Eintrittssignals (mtdrs), das verwendet wird, um in den zweiten Zugriffsmodus einzutreten, wobei die Eingangssignale verwendet werden; und das Ungültigmachen mindestens eines der Eingangssignale auf selektive Weise, in Übereinstimmung mit dem Auswahlsteuersignal, die Erzeugung des ersten Eintrittssignals oder des zweiten Eintrittssignals sperrt. Das Verfahren nach Anspruch 15, dadurch gekennzeichnet, dass: das Erzeugen des Eintrittssignals ein Auswählen mindestens eines der Eingabesignale und ein Erkennen eines Übergangs des ausgewählten, mindestens einen der Eingangssignale umfasst, um das Eintrittssignal zum Starten eines der Zugriffsmodi zu erzeugen. Das Verfahren nach Anspruch 17, des Weiteren gekennzeichnet durch den Schritt: Durchführen des anderen Zugriffsmodus in Übereinstimmung mit dem Übergang des ausgewählten, mindestens einen der Eingangssignale, nachdem der eine der Zugriffsmodi abgeschlossen ist. Das Verfahren nach Anspruch 18, des Weiteren gekennzeichnet durch den Schritt: Durchführen des anderen Zugriffsmodus in Übereinstimmung mit dem Übergang mindestens eines der Eingangssignale, mit Ausnahme des ausgewählten, mindestens einen der Eingangssignale. Das Verfahren nach Anspruch 17, dadurch gekennzeichnet, dass die Halbleiterspeichervorrichtung ein Zugriffsanforderungssignal erzeugt, welches einen Eintritt in den einen der Zugriffsmodi anfordert, zu vorbestimmten Zeitintervallen, und das Starten des einen der Zugriffsmodi ein Ungültigmachen des Zugriffsanforderungssignals mit dem Testsignal umfasst.
Anspruch[en]
A semiconductor memory device including first and second access modes, a test mode, and an entry signal generation circuit (20; 31) for generating a first entry signal (mtds; mtdcs) used to enter the first access mode using a plurality of input signals (ceb, web, oeb, ad0), the first access mode being an external access mode and the second access mode being an internal refresh mode, and a control circuit (27; 33) connected to the entry signal generation circuit to generate a first mode trigger signal (rw-start) in response to the first entry signal,

and when the control circuit receives a second entry signal (ref-req) to enter the second access mode, the control circuit generates a second mode trigger signal (ref-start) in response to the second entry signal, the semiconductor memory device characterized in that the entry signal generation circuit (20; 31) receives a selection control signal (en-code) in the test mode and invalidates at least one of said input signals in a selective manner in accordance with the selection control signal (en-code), thereby inhibiting the generation of the first entry signal.
The semiconductor memory device according to claim 1, characterized in that the selection control signal includes code information related to the input signals to be used. The semiconductor memory device according to any one of claims 1 or 2, characterized in that the entry signal generation circuit includes: a plurality of transition detectors (21-25), each detecting transition of an associated one of the input signals to generate a detection signal; and a pulse synthesizing circuit (26; 32) connected to the transition detectors to generate the first entry signal using the detection signals in accordance with the selection control signal. The semiconductor memory device according to any one of claims 12, or 3, characterized in that the control circuit invalidates the second entry signal in accordance with a test signal used to enter the test mode and generates the second mode trigger signal in response to the first entry signal. The semiconductor memory device according to claim 1, characterized in that the entry signal generation circuit (31) generates a third entry signal (mtdrs) used to enter the second access mode using the input signals in accordance with the selection control signal. The semiconductor memory device according to claim 5, characterized in that the entry signal generation circuit includes: a plurality of transition detectors (21-25), each detecting transition of an associated one of the input signals to generate a detection signal; and a pulse synthesizing circuit (32) connected to the transition detectors to generate the first and third entry signals using the detection signals in accordance with the selection control signal. The semiconductor memory device according to claim 5 or 6, characterized in that the control circuit invalidates the second entry signal in accordance with a test signal used to enter the test mode and generates the second mode trigger signal in response to the third entry signal. The semiconductor memory device according to any one of claims 5 to 7, characterized in that the control circuit (33) includes: a mode trigger generation circuit (42) connected to the entry signal generation circuit to generate the first mode trigger signal in response to the first entry signal; a determination circuit (41) connected to the entry signal generation circuit to invalidate the second entry signal in accordance with the test signal and generate the second mode trigger signal in response to the third entry signal; and an internal operation signal generation circuit (43) connected to the mode trigger generation circuit and the determination circuit to generate an internal operation signal in accordance with the first mode trigger signal and the second mode trigger signal. The semiconductor memory device according to claim 1, characterized in that the input signals include a plurality of control signals and a plurality of address signals. The semiconductor memory device according to claim 1, further characterized by a selection signal generation circuit (30) connected to the entry signal generation circuit to generate the selection control signal. The semiconductor memory device according to claim 1, further characterized by a timer (28) connected to the control circuit to generate the second entry signal. The semiconductor memory device according to claim 1, characterized in that the first access mode is a read operation mode or a write operation mode, and the second access mode is a self refresh operation mode. The semiconductor memory device according to claim 1, characterized in that the entry signal generation circuit (20) generates the first entry signal (mtds) used to enter the first access mode or the second access mode using the plurality of input signals, and the control circuit (27) generates the first mode trigger signal (rw-start), which is used to start the first access mode, in response to the first entry signal and generates the second mode trigger signal (ref-start), which is used to start the second access mode, in response to the first entry signal. The semiconductor memory device according to claim 1, characterized in that the entry signal generation circuit (31) generates the first entry signal (mtdcs) used to enter the first access mode and a third entry signal (mtdrs) used to enter the second access mode using the plurality of input signals, the control circuit (33) generates the first mode trigger signal (rw-start), which is used to start the first access mode, in response to the first entry signal and generates the second mode trigger signal (ref-start), which is used to start the second access mode, in response to the third entry signal. A method for testing a semiconductor memory device having a first access mode, a second access mode, and a test mode, the first access mode being an external access mode and the second access mode being an internal refresh mode, the method comprising the steps of: receiving a plurality of input signals (ceb, web, oeb, ad0); generating an entry signal (mtds; mtdcs; mtdrs) used to enter the first access mode or the second access mode using the input signals; characterised by the steps of: receiving a selection control signal (en-code) in the test mode; and invalidating at least one of said input signals in a selective manner in accordance with the selection control signal, thereby inhibiting the generation of the entry signal. The method according to claim 15, further characterized in that: said generating the entry signal includes: generating a first entry signal (mtdcs) used to enter the first access mode using the input signals, and generating a second entry signal (mtdrs) used to enter the second access mode using the input signals; and said invalidating at least one of said input signals in a selective manner in accordance with the selection control signal inhibits the generation of the first entry signal or the second entry signal. The method according to claim 15, characterized in that: said generating the entry signal includes selecting at least one of the input signals and detecting transition of the selected at least one of the input signals to generate the entry signal for starting one of the access modes. The method according to claim 17, further characterized by the step of: performing the other access mode in correspondence with the transition of the selected at least one of input signals after said one of the access modes is completed. The method according to claim 18, further characterized by the step of: performing said other access mode in correspondence with the transition of at least one of the input signals excluding the selected at least one of input signals. The method according to claim 17, characterized in that the semiconductor memory device generates an access request signal, which requests entry of said one of the access modes, at predetermined time intervals, and the starting of said one of the access modes includes invalidating the access request signal with the test signal.
Anspruch[fr]
Dispositif de mémoire à semiconducteur incluant des premier et second modes d'accès, un mode de test et un circuit de génération de signal d'entrée (20 ; 31) pour générer un premier signal d'entrée (mtds ; mtdcs) utilisé pour entrer dans le premier mode d'accès en utilisant une pluralité de signaux d'entrée (ceb, web, oeb, ad0), le premier mode d'accès étant un mode d'accès externe et le second mode d'accès étant un mode de rafraîchissement interne, et un circuit de commande (27 ; 33) connecté au circuit de génération de signal d'entrée pour générer un premier signal de déclencheur de mode (rw-start) en réponse au premier signal d'entrée,

et lorsque le circuit de commande reçoit un second signal d'entrée (ref-req) pour entrer dans le second mode d'accès, le circuit de commande génère un second signal de déclencheur de mode (ref-start) en réponse au second signal d'entrée, le dispositif de mémoire à semiconducteur étant caractérisé en ce que le circuit de génération de signal d'entrée (20 ; 31) reçoit un signal de commande de sélection (en-code) dans le mode de test et invalide au moins l'un desdits signaux d'entrée d'une manière sélective conformément au signal de commande de sélection (en-code), d'où ainsi l'inhibition de la génération du premier signal d'entrée.
Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en ce que le signal de commande de sélection inclut une information de code rapportée aux signaux d'entrée à utiliser. Dispositif de mémoire à semiconducteur selon l'une quelconque des revendications 1 ou 2, caractérisé en ce que le circuit de génération de signal d'entrée inclut : une pluralité de détecteurs de transition (21-25) dont chacun détecte la transition de l'un associé des signaux d'entrée pour générer un signal de détection ; et un circuit de synthèse d'impulsion (26 ; 32) connecté aux détecteurs de transition pour générer le premier signal d'entrée en utilisant les signaux de détection conformément au signal de commande de sélection. Dispositif de mémoire à semiconducteur selon l'une quelconque des revendications 1, 2 ou 3, caractérisé en ce que le circuit de commande invalide le second signal d'entrée conformément à un signal de test utilisé pour entrer dans le mode de test et génère le second signal de déclencheur de mode en réponse au premier signal d'entrée. Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en ce que le circuit de génération de signal d'entrée (31) génère un troisième signal d'entrée (mtdrs) utilisé pour entrer dans le second mode d'accès en utilisant les signaux d'entrée conformément au signal de commande de sélection. Dispositif de mémoire à semiconducteur selon la revendication 5, caractérisé en ce que le circuit de génération de signal d'entrée inclut : une pluralité de détecteurs de transition (21-25) dont chacun détecte la transition de l'un associé des signaux d'entrée pour générer un signal de détection ; et un circuit de synthèse d'impulsion (32) connecté aux détecteurs de transition pour générer les premier et troisième signaux d'entrée en utilisant les signaux de détection conformément au signal de commande de sélection. Dispositif de mémoire à semiconducteur selon la revendication 5 ou 6, caractérisé en ce que le circuit de commande invalide le second signal d'entrée conformément à un signal de test utilisé pour entrer dans le mode de test et génère le second signal de déclencheur de mode en réponse au troisième signal d'entrée. Dispositif de mémoire à semiconducteur selon l'une quelconque des revendications 5 à 7, caractérisé en ce que le circuit de commande (33) inclut : un circuit de génération de déclencheur de mode (42) connecté au circuit de génération de signal d'entrée pour générer le premier signal de déclencheur de mode en réponse au premier signal d'entrée ; un circuit de détermination (41) connecté au circuit de génération de signal d'entrée pour invalider le second signal d'entrée conformément au signal de test et pour générer le second signal de déclencheur de mode en réponse au troisième signal d'entrée ; et un circuit de génération de signal d'opération interne (43) connecté au circuit de génération de déclencheur de mode et au circuit de détermination pour générer un signal d'opération interne conformément au premier signal de déclencheur de mode et au second signal de déclencheur de mode. Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en ce que les signaux d'entrée incluent une pluralité de signaux de commande et une pluralité de signaux d'adresse. Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en outre par un circuit de génération de signal de sélection (30) connecté au circuit de génération de signal d'entrée pour générer le signal de commande de sélection. Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en outre par une minuterie (28) connectée au circuit de commande pour générer le second signal d'entrée. Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en ce que le premier mode d'accès est un mode d'opération de lecture ou un mode d'opération d'écriture et le second mode d'accès est un mode d'opération d'auto-rafraîchissement. Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en ce que le circuit de génération de signal d'entrée (20) génère le premier signal d'entrée (mtds) utilisé pour entrer dans le premier mode d'accès ou dans le second mode d'accès en utilisant la pluralité de signaux d'entrée, et le circuit de commande (27) génère le premier signal de déclencheur de mode (rw-start) qui est utilisé pour démarrer le premier mode d'accès en réponse au premier signal d'entrée et génère le second signal de déclencheur de mode (ref-start) qui est utilisé pour démarrer le second mode d'accès en réponse au premier signal d'entrée. Dispositif de mémoire à semiconducteur selon la revendication 1, caractérisé en ce que le circuit de génération de signal d'entrée (31) génère le premier signal d'entrée (mtdcs) utilisé pour entrer dans le premier mode d'accès et un troisième signal d'entrée (mtdrs) utilisé pour entrer dans le second mode d'accès en utilisant la pluralité de signaux d'entrée, le circuit de commande (33) génère le premier signal de déclencheur de mode (rw-start) qui est utilisé pour démarrer le premier mode d'accès en réponse au premier signal d'entrée et génère le second signal de déclencheur de mode (ref-start) qui est utilisé pour démarrer le second mode d'accès en réponse au troisième signal d'entrée. Procédé pour tester un dispositif de mémoire à semiconducteur comportant un premier mode d'accès, un second mode d'accès et un mode de test, le premier mode d'accès étant un mode d'accès externe et le second mode d'accès étant un mode de rafraîchissement interne, le procédé comprenant les étapes de : réception d'une pluralité de signaux d'entrée (ceb, web, oeb, ad0) ; génération d'un signal d'entrée (mtds ; mtdcs, mtdrs) utilisé pour entrer dans le premier mode d'accès ou dans le second mode d'accès en utilisant les signaux d'entrée, caractérisé par les étapes de : réception d'un signal de commande de sélection (en-code) dans le mode de test ; et invalidation d'au moins l'un desdits signaux d'entrée d'une manière sélective conformément au signal de commande de sélection, d'où ainsi l'inhibition de la génération du signal d'entrée. Procédé selon la revendication 15, caractérisé en outre en ce que : ladite génération du signal d'entrée inclut : la génération d'un premier signal d'entrée (mtdcs) utilisé pour entrer dans le premier mode d'accès en utilisant les signaux d'entrée ; et la génération d'un second signal d'entrée (mtdrs) utilisé pour entrer dans le second mode d'accès en utilisant les signaux d'entrée ; et ladite invalidation d'au moins l'un desdits signaux d'entrée d'une manière sélective conformément au signal de commande de sélection inhibe la génération du premier signal d'entrée ou du second signal d'entrée. Procédé selon la revendication 15, caractérisé en ce que : la génération du signal d'entrée inclut la sélection d'au moins l'un des signaux d'entrée et la détection d'une transition de l'au moins un sélectionné des signaux d'entrée pour générer le signal d'entrée pour démarrer l'un des modes d'accès. Procédé selon la revendication 17, caractérisé en outre par l'étape de : réalisation de l'autre mode d'accès en correspondance avec la transition de l'au moins un sélectionné de signaux d'entrée après que ledit un des modes d'accès est terminé. Procédé selon la revendication 18, caractérisé en outre par l'étape de : réalisation dudit autre mode d'accès en correspondance avec la transition d'au moins l'un des signaux d'entrée à l'exclusion de l'au moins un sélectionné des signaux d'entrée. Procédé selon la revendication 17, caractérisé en ce que le dispositif de mémoire à semiconducteur génère un signal de requête d'accès, lequel demande une entrée dans ledit un des modes d'accès, selon des intervalles temporels prédéterminés, et le démarrage dudit un des modes d'accès inclut l'invalidation du signal de requête d'accès avec le signal de test.






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