PatentDe  


Dokumentenidentifikation EP1394810 22.11.2007
EP-Veröffentlichungsnummer 0001394810
Titel Nichtflüchtige Speicheranordnung und Selbstreparatur-Verfahren
Anmelder STMicroelectronics S.r.l., Agrate Brianza, Mailand/Milano, IT
Erfinder De Ambroggi, Luca, 95127 Catania, IT;
Condemi, Carmelo, 95030 Gravina di Catania, IT
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 60222891
Vertragsstaaten DE, FR, GB, IT
Sprache des Dokument EN
EP-Anmeldetag 13.08.2002
EP-Aktenzeichen 024255291
EP-Offenlegungsdatum 03.03.2004
EP date of grant 10.10.2007
Veröffentlichungstag im Patentblatt 22.11.2007
IPC-Hauptklasse G11C 29/00(2006.01)A, F, I, 20070911, B, H, EP
IPC-Nebenklasse G11C 16/34(2006.01)A, L, I, 20070911, B, H, EP   

Beschreibung[en]

The present invention relates to a nonvolatile storage device and a self-redundancy method of the same.

As it is known, redundancy structures are provided for replacing failed memory locations so as to prevent the rejection of the entire storage device.

Normally, the replacement of the failed memory location with the redundancy part takes place in final production steps, when a special test, referred to as electrical wafer sorting (EWS), detects a failure.

The structure commonly used for storing the addresses of redunded or replaced memory locations is principally made up of CAM banks, i.e., nonvolatile storage units, programmable and erasable by the manufacturer in the testing step. In particular, when a failure is detected in a memory location, information designed to determine uniquely the memory location to be replaced is stored in the CAMs.

The information stored in the CAMs may be of various kinds: the addresses of the location to be repaired, whether and which bit packet of the word addressed is to be replaced, whether an entire sector is to be replaced, whether the bank has already been used for storing an address of a failed location or not (guard information), etc.

The number of banks used in the redundancy structure defines the maximum number of packets (columns, bytes, rows, sectors hereinafter indicated also as memory units or memory locations) that can be replaced in the entire memory array. When, then, the location has been replaced, it is necessary to carry out a number of operations for identifying the location that stores the information instead of the failed location.

The check and the possible redundancy replacement are carried out for any operation, either reading or writing, that is to be performed on the failed location, when addressing of the location is required.

The structure for managing redundancy has the function of verifying whether the time location addressed is among the replaced ones and, if so, provide for activation of the redundancy locations and to the simultaneous de-activation of the decoding of the memory array corresponding to the defective location.

In particular, the address of the location that is to be read or written (program or erase) is compared with the addresses of the replaced locations during the testing steps and, in the event of coincidence with one of them, a "hit" signal is generated that has the task of activating the redundancy circuitry and of replacing the failed location (whether it be a bit, a byte, a word, or a sector) by physically pointing to the redundancy unit.

In the ensuing description, the discussion will be limited to the case of sector redundancy. The following considerations, however, readily applicable also to other types of redundancy, such as for example column redundancy.

In the literature, sector redundancy is complementary to column redundancy and is preferred to row redundancy for high memory density devices (i.e., with a density greater than or equal to 16 Mbits). Furthermore, sector redundancy is preferred as regards area, speed and performance of the memory during reading operations, and finally because of a greater flexibility in solving serious problems that may arise in the array, such as for example shorts between wordlines and substrate.

At present, the common sector redundancy envisages a plurality of redundancy units, which, for area efficiency and yield, may be expressed as a redundancy unit (a redundancy sector) for each multiple of 16 Mbits. Each redundancy unit is therefore associated to a CAM comprising a plurality of nonvolatile cells, equal to the number of bits of the address necessary for identifying each sector of the memory array. Each CAM thus identifies a failed sector.

Furthermore, a further nonvolatile memory element, referred to as guard CAM, is associated to each redundancy unit and stores a guard information specifying whether the associated redundancy unit has been used or not.

During reading or programming of cells of the memory array, the comparison between the addresses supplied from outside by the user and the ones stored in the CAMS generates, in the presence of the guard information activated, the "hit" signal mentioned above.

In present memory architectures, the content of the CAMs, programmed, as has been said, during the EWS testing step, is read continuously throughout the lifetime of the device, using a structure the cells whereof are directly connected, through the drain terminal, to latches that buffer the content of the information present in the CAMs.

Programming is performed by using the same switch structure (the so-called "program loads") present in the array, disabling the array-decoding circuits, enabling the redundancy ones, and causing the datum to move (drain voltage) along bitlines (main bitline in the case of a hierarchical architecture) present in the memory array.

Examples of architectures and methods for replacing failed cells during EWS test or other tests by standard fuse elements are disclosed, e.g., in EP 0 805 451 , US 6,363,020 , US 5,668,818 , EP 0 867 810 .

EP 1 107 121 teaches a non-volatile memory device having the features of the preamble of claim 1 and including a testing mode for judging the validity of initially-setting data, including addresses of defective cells.

This architecture does not enable ease of activation and management of redundancy for addressing the nonvolatile cells during normal operation of the device by using an automatic replacement algorithm that exploits structures and circuits already present in the device.

The aim of the invention is consequently to provide a storage device and a method that enable activation and management of redundancy during normal operation using the circuits already present in the array for reading, programming, erasing and verifying.

According to the present invention, a nonvolatile storage device and a redundancy method are provided, as defined in claims 1 and 10, respectively.

For a better understanding of the present invention, a preferred embodiment is now described, purely by way of nonlimiting example, with reference to the attached drawings, wherein:

  • Figure 1 illustrates a block diagram of a storage device according to the invention;
  • Figure 2 is a simplified circuit diagram of a block of Figure 1, according to the invention;
  • Figures 3 and 4 are flowcharts of the method according to the invention; and
  • Figure 5 illustrates a diagram of the association between registers and redundancy sectors, according to the invention.

In the device and method described in detail hereinafter, the reading structure already present for reading the array, the structure storing the sectors for managing failures and sectors to be erased, and the counter of the present addresses are used. In this way, even the entire testing structure and the testing procedure of the DMA test, shadow test, and CAM program-and-erase test, may be kept unaltered.

For a better understanding of the invention, the simplified structure of a memory 1, of a flash type, as modified according to the invention for the implementation of self-redundancy, is now described with reference to Figure 1.

The memory 1 comprises a memory array 2 made up of standard sectors 19a (only two of which are shown) and of redundancy sectors 19b (only two of which are shown). The memory array 2 is connected, in a known way, to a row-decoder block 3 and to a column-decoder block 4. The column-decoder block 4 further comprises sense amplifiers SA and program loads, both built according to a known structure.

An address-counter block 5 has an input connected to an address-input gate 6, from which it receives, from outside, general addresses ADD; the address-counter block 5 generates, under the control of a state machine 12, internal addresses for addressing the memory array 2, supplied on an address bus 8 (ADDBUS). The address bus 8 is connected to the row-decoder and column-decoder blocks 3, 4 and to a redundancy-detection unit 15 (the structure whereof will now be described in greater detail with reference to Figure 2). The address-counter block 5 is moreover connected, through the address bus 8, to a RAM 7, which constitutes a sector memory.

In detail, as is represented schematically in the enlarged detail, the RAM 7 is divided into a plurality of portions or rows 14, one for each sector of the memory array 2, each portion 14 comprising a first subportion 14a and a second subportion 14b. During erasing, the first subportion 14a stores the address of a memory location where checking must start after application of the erasing pulses (and thus operates as a pointer), while the second subportion 14b stores a flag, the logic state of which indicates whether the associated sector is to be erased or not.

The address counter 5 is moreover connected to a sense-timing circuit 9, which supplies appropriate enabling signals to the row-decoder and column-decoder blocks 3, 4 as well as to a data-input/output unit 10. The data-input/output unit 10 is moreover connected to a data bus DBUS 11, which is in turn connected to the column-decoder block 4, to the state machine 12, to the redundancy-detection unit 15, to the RAM 7, and to a state register 17.

The state machine 12 exchanges information with a microprocessor control unit 16 and sends state information to the state register 17. The control unit 16 moreover exchanges information and commands with the redundancy-detection unit 15 and the RAM 7.

The redundancy-detection unit 15 is moreover connected to the row-decoder and column-decoder blocks 3, 4, and to the CAMs 18 (just one of which is shown), designed for storing the addresses of the replaced sectors. The CAMs 18 are functionally associated to the memory array 2, and share with this the same address and read circuits. Hence, for simplicity, in Figure 1 the CAMs 18 are represented as belonging to the memory array, even though they may be physically separate, albeit contiguous thereto.

As explained in greater in detail hereinafter, at turning-on of the memory, the redundancy-detection unit 15 receives from the memory array 2, and precisely from the CAMs 18, read via the column-decoder block 4, the previously stored redundancy data and writes them, in a volatile way, in registers where they are immediately accessible. Consequently, when the address counter 5 supplies the row and column addresses of words to be read, the redundancy-detection unit 15 compares the addresses received on the data bus 11 with the ones stored in its own registers, and, if it detects an identity, replaces the addresses received with the redundancy ones so as to address the redundancy sectors 19b, as explained in detail hereinafter with reference to Figure 2.

Furthermore, during erasing and programming, when a failure is detected in one or more standard sectors 19a, the redundancy-detection unit 15 receives the addresses of the failed sectors, supplied by the address counter 5 on the address bus 8, and, under appropriate control of the control unit 16, writes them in a temporary way in its own registers and subsequently, via the data bus 11, in the CAMs 18.

Hereinafter the structure of the redundancy-detection unit 15 is described as regards redundancy during the operation of the device (erasing, as described below with reference to Figures 3 and 4, or else programming and reading).

With reference to Figure 2, the redundancy-detection unit 15 comprises a switching gate 20 having a first data input connected to the data bus 11, a second data input connected to the address bus 8, a selection input receiving a first control signal SEL1 from the control unit 16, and an output connected to a redundancy bus 21. The output of the switching gate 20 is moreover connected to the storage bus 11 via a buffer 40 controlled by a second control signal SEL2, supplied by the control unit 16.

The redundancy bus 21 is connected to the data input D of a plurality of registers 22 (in the example three are shown), designated by 221, 222, 223, daisy-chain connected and made up of latches. In general, the number of registers 22 is equal to the number of available redundancy resources (number of redundancy sectors 19b) and of self-redundancy CAMs 18.

In detail, each register 22 is divided into two parts: a first part 22a, for storing an entire address of a failed sector, and a second part 22b, for storing a guard bit, the logic value whereof is indicative of whether the corresponding register 22 has already been loaded or not with an address of a failed sector. Each register 22 further comprises a synchronization input CK, a guard output G (connected to the second part 22b), and an output address Q, connected to the second portion 22b.

The registers 221, 222, 223 have the synchronization input CK connected to the output of a respective AND gate 231, 232, 233. The AND gates 231, 232, 233 are of the three-input type: a first input 24, of a inverted type, is connected to the guard output G of a respective register 221, 222, 223 and receives an inverted guard bit GN equal to the corresponding inverted guard bit; a second input 25 receives a load signal L supplied by the control unit 16; and a third input 26 is connected to the guard output of a preceding register, except for a first register 221. In detail, the first register 221 has the third input 26 connected in a fixed way to a voltage corresponding to a logic level "1"; a second register 222 has the third input 26 connected directly to the guard output G of the first register 221; and the third register 223 has the third input 26 connected directly to the guard output G of the second register 222. Other possible registers are likewise connected starting from the third register 223.

The last register (here the third register 223) has the guard output G connected to the control unit 16, which supplies a signal NO_RIS, the logic value of which indicates whether further free redundancy resources are present or not.

The address outputs Q of the registers 221, 222, 223 are connected each to a first input of a respective XNOR gate 30.

The XNOR gates 30 moreover have a second input connected to the redundancy bus 21, and a first output connected to a logic adder circuit 31, which outputs a disable signal DIS supplied to the row-decoder and column-decoder blocks 3, 4 of Figure 1. Each of the XNOR gates 30 further have a second output connected rigidly to a respective redundancy sector 19b, for enabling thereof, as explained below.

The redundancy-detection unit 15 operates as described hereinafter. As soon as redundancy is activated following upon the detection of one or more failed sectors after a modification operation (as described in detail hereinafter with reference to Figures 3 and 4 for erasing), the switching gate 20 is controlled by the first selection signal SEL1 so as to connect the address bus 8 to the redundancy bus 21. In this step, the buffer 40 is still inactive, and the address bus 8 supplies, in addition to the address of a failed sector, the guard bit, having logic value "1". This bit is programmed after the address information has been programmed in the CAMs. In this way, in the event of an accidental power-down between programming the addresses and programming the guard bit, it notifies the fact that the programmed information is incomplete.

Assuming that the redundancy has not yet been activated previously, the first register 221 is still empty and its guard bit G is still in the inactive state, corresponding to a logic "0"; consequently the inverted guard bit GN is equal to "1". Hence, as soon as the load signal L switches to the high state, the first AND gate 231 supplies, to the synchronization input CK, a "1", which enables loading of the address and of the guard bit supplied on the redundancy bus 21 inside the first register 221.

Instead, when the load signal L switches, the second and the third AND gates 232, 233 receive the previous value of the guard bit G of the first and second registers 231, 232 (still at "0") and consequently are not enabled for loading.

In this step, the XNOR gates 30 and the logic adder circuit 31 are practically disabled or in any case supply non-significant signals, which are ignored by the row-decoder and column-decoder blocks 3, 4.

At the subsequent redundancy activations, the data are loaded each time into a subsequent register 222, 223. In fact, at the second activation, the first register 221 disables its own AND gate 231 and enables the subsequent AND gate 232, since it has the guard bit G in the high state. Next, upon arrival of the load signal L, the address and the guard bit are stored in the second register 222. The third register 223 and possible subsequent registers remain, however, disabled.

In this way, it is possible to store the address of a number of failed sectors equal to the number of registers 22 present.

After all the registers 22 have been loaded, the high value of the guard bit G of the last register (here the third register 223), which constitutes the signal NO RIS, signals that there are no longer available further redundancy resources.

Immediately after loading the address of a failed sector in one of the registers 22, this is stored in a nonvolatile way in a CAM 18. To this end, the address of the failed sector, still present on the address bus 8, is supplied to the data bus 11 via the switching gate 20 and the buffer 40, now activated by the second selection signal SEL2. Consequently, the address of the failed sector is supplied to the column-decoder block 4, as explained in detail hereinafter.

Upon turning-on of the memory 1, when the POR (Power-On Reset) signal is generated, the contents of the CAMs 18 that store the addresses of the failed sectors previously detected are supplied in a sequential way on the data bus 11 and are loaded sequentially into the registers 22 via the switching gate 20, which now connects the data bus 11 to the address bus 8 on a command from the control unit 16. Loading takes place sequentially in the different registers 22, in a manner similar to what is described above. In this way, at each turning-on of the memory, the registers 22 are loaded with the redundancy data previously stored.

During reading, the address supplied on the address bus 8 is fed, by the redundancy bus 21, to the XNOR gates 30, which compare it to the failed-sector address supplied by the respective register 22. If the address supplied on the address bus 8 does not correspond to any of the addresses stored by the registers 22, the XNOR gates generate a non-recognition signal (disable signal DIS in the inactive state), and the row-decoder and column-decoder blocks 3, 4 operate in the usual way on the basis of the address present on the address bus 8. Instead, if one of the XNOR gates recognizes the equality with the address stored in the associated register 22, it generates a recognition signal, which is supplied to the logic adder circuit 31. Consequently, in this step, the disable signal DIS goes into the active state and disables the address present on the address bus 8 (disabling of the standard sector 19a addressed by the address counter 5 of Figure 1). Furthermore, the XNOR gate 30, which has recognized the equality, enables the redundancy sector 19b associated thereto.

Hereinafter, with reference to Figures 3 and 4, the procedure for erasing groups of sectors is described, where activation of redundancy on-line is carried out when detecting failed memory locations.

This procedure uses the RAM 7 of Figure 1, wherein the flags corresponding to the sectors to be erased are set in the second subportions 14b (flags in the active state), in a known way, before activating erasing. The RAM 7 thus represents a list of sectors to be erased, identified by the respective flags in active state.

In the ensuing description, it is moreover assumed that one or more sectors belonging to a preset group are to be erased; the same procedure is, however, applicable to the entire memory array.

Initially, step 50, the first subportions 14a of the portions 14 having flags in the set or active state (and consequently corresponding to the sectors to be erased) are reset, so as to contain the address of the first word of each respective sector. In addition, a sector counter is initialized with the first sector of the considered sector group.

Next, step 51, a check is made to see whether all the blocks to be erased have actually been erased by checking the state of the flags. If they have (all the flags in the inactive state), erasing terminates; otherwise, an erasing pulse is sent to all the sectors identified by the flags in the active state, step 52.

Next, step 53, the address stored in the first subportion 14a corresponding to the first sector of the list that has an active flag is read. As said, this address corresponds initially to the first word of the sector; hereinafter, as described below, it represents the address of the last word of the sector that has been checked (and for which the check has not been successful).

Subsequently, step 54, the considered sector is checked, starting from the word identified by the address just read and proceeding until the entire sector has been checked or detecting a word not correctly erased. If the entire sector has been erased (output YES from step 55), the flag corresponding to the sector just erased is reset (i.e., it is brought to the inactive state) by erasing in practice the sector itself from the list of the sectors to be erased, step 60. Then, the procedure goes to step 62, as described below.

If the check is interrupted on account of the detection of a word not correctly erased, output NO from step 55, the first subportion 14a is written with the address of the word just checked and for which the check has given a negative result, step 61. Then, a check is made to see whether the sector just checked is the last in the list, step 62.

If there are still sectors to be checked, output NO from step 62, a next sector is addressed, incrementing the sector counter, step 63, and then the procedure returns to step 53, where the address stored in the first subportion 14a of the RAM 7 and corresponding to the next sector just addressed is read. Instead, if all the sectors have been checked (but, of course, some contain words not correctly erased), output YES from step 62, a number-of-attempts counter I is incremented, step 64.

This counter (which indicates the number of supplied programming pulses) has the purpose of enabling the repetition of the cycle that comprises applying an erasing pulse and verifying the cells of the sectors starting from the ones that have yielded a negative result in the previous check. Only if, after a certain number of cycles, at least one cell is still not correctly erased, a redundancy routine is activated, and subsequently further cycles of erasing and verifying are repeated. If after these further cycles the sectors are still not erased, an error signal is generated ("fail").

For this purpose, after step 64, a check is made to see whether the number-of-attempts counter I is equal to a first threshold value IMAX1. If it is, a redundancy routine 70 is activated, described hereinafter with reference to Figure 4, and the program goes back to step 53 for reading the address of the first sector that has an active flag; otherwise, output NO from step 65, a check is made to see whether the number-of-attempts counter I is equal to a second threshold value IMAX2 greater than IMAX1, step 66. If not, the program goes back to step 51 for checking whether all the sectors have been erased, to repeat the cycle of applying erasing and verifying pulses, or to terminate the procedure, if all the sectors have been erased. If they have (the number-of-attempts counter I is equal to the second threshold value IMAX2), a failure signal is generated, step 67, and the procedure terminates.

With reference to Figure 4, the redundancy routine 70 starts with resetting the sector counter, step 71, and checking whether the first sector addressed by the sector counter has already been erased, by reading the state of the corresponding flag, step 72. If it has, a check is made to see whether all the sectors have been checked, step 80; otherwise, a check is made to see whether the sector currently addressed is already a redundancy sector or whether there are no longer available further redundancy resources, step 73. If this is the case, it is no longer possible to activate further redundancy resources; consequently, step 81, all the pointers are reset (addresses stored in the first subportions 14a of the RAM 7), and the redundancy routine 70 terminates.

Instead, if redundancy resources are still available, output NO from step 73, loading of the address of the current sector in the first register 22 available is commanded (according to the description made with reference to Figure 2), step 74, and the same current address is stored in a nonvolatile way in a CAM 18 (as previously described), step 75. Then, the program goes to step 80 for verifying whether the presently addressed sector is the last of the list stored in the RAM 7. If not, step 82, the sector counter is incremented, and the procedure returns to step 72; if it is, the program continues with step 81, as mentioned above. From now on, the portion 14 of the RAM 7 previously associated to a failed sector stores the information related to the redundancy sector that replaces it, and specifically the address of the first word to be checked and the erasing flag. In this way, returning to the main procedure of Figure 3, the redundancy sector or sectors just enabled is/are erased and checked in the way described above.

After resetting the addresses loaded in the RAM 7, the redundancy routine 70 terminates.

Figure 5 illustrates a structure of the registers 22 that enables the redundancy of a redundancy sector in the event of a failure occurring such as to render it unusable. For this purpose, instead of having a rigid association between each register 22 and the corresponding redundancy sector, the association is fixed when a failed sector is detected, and the address of the redundancy sector is stored together with the address of the replaced sector.

In the example of Figure 5, each register 22 (and consequently each CAM 18 storing the same data in a nonvolatile way) comprises a first portion 90 storing the address of a failed sector, a second portion 91 storing the guard bit G, and a third portion 92 storing the address of the redundancy sector (which replaces the sector the address whereof is stored in the first portion 90). In this way, the association between each register and the corresponding redundancy sector is not preset and is represented by the arrows. If the redundancy sector addressed by the first register fails, for example, it would be possible to replace the address of the failed redundancy sector with a further redundancy sector, as represented by the dashed arrow.

This applies, in particular, for enabling the redundancy of redundancy sectors activated during EWS.

The advantages of the described storage device are the following. First, it enables replacement of a failed unit not only during testing of the device inside the production plant (for example during EWS), but also when the device is in operation. In this way, the storage device presents a greater flexibility, and a consequent increase in yield.

Furthermore, it is possible to speed up also EWS testing, thanks to the use of the control unit 16 inside the storage device and an embedded algorithm, ruling out the need for any interfacing with external testing machines. This enables a reduction in the testing effort (development resources and testing times) aimed at identifying, at time zero, any failures that may occur subsequently during the life of the device (cycling, dedicated testing).

The storage device described herein involves a minimum increase in overall dimensions for the additional circuitry, thanks to the use principally of structures already present.

In particular, the implementation described herein of self-redundancy enables the use of the reading structure already present for operation of the memory array 2, the re-use of the RAM 7 for managing the failed sectors and of the sectors undergoing erasing, as well as the re-use of the address counter 5.

It is not necessary to use separate cells as CAMs, but memory cells of the memory array may be used that are intended specifically for redundancy.

The use of registers for loading redundancy information during turning-on of the storage device enables rapid detection of any replacement of a sector addressed to be read and addressing with the one operating correctly. In practice, the registers 22 operate as the nonvolatile cells provided for traditional EWS redundancy, at the same time guaranteeing a more agile management of the existing structures.

The redundancy operations are altogether transparent to the user (for example, during modification, the state register is accessible to the user, either a product manager or a customer who requires information on the state of the operations).

The registers 22 may be moreover equipped with set/reset transistors for testing operations of a shadow type.

Finally, it is clear that numerous modifications and variations may be made to the storage device and to the redundancy method described and illustrated herein, all falling within the scope of the invention, as defined in the annexed claims. For example, although the foregoing description refers only to sector redundancy, as indicated, the invention is applicable also to redundancy of a different type, for example column redundancy, byte redundancy, or row redundancy. Furthermore, the redundancy may be activated also following upon an unsuccessful programming operation.


Anspruch[de]
Nichtflüchtige Speichervorrichtung (1), aufweisend: eine Speicheranordnung (2), die in eine Mehrzahl von nichtflüchtigen Datenspeichereinheiten (19a) unterteilt ist; eine Steuereinheit (16) mit einer Datenmodifikations-Steuereinrichtung zum Aktivieren eines Datenmodifikationsvorgangs an den Datenspeichereinheiten, wobei die Steuereinheit ferner eine Detektionseinrichtung aufweist, die während des Datenmodifikationsvorgangs freigegeben wird, um die Funktionsfähigkeit der Datenspeichereinheiten festzustellen; eine Redundanz-Detektionseinheit (15), die durch die Steuereinheit freigegeben wird, wobei die Redundanz-Detektionseinheit flüchtige Speicherelemente (22) beinhaltet; und eine Mehrzahl von nichtflüchtigen Redundanz-Speichereinheiten (19b) zum Ersetzen von jeweiligen fehlerhaften Datenspeichereinheiten, dadurch gekennzeichnet, dass die Redundanz-Speichereinheit (15) während des Datenmodifikationsvorgangs durch die Steuereinheit (16) freigegeben wird, um die Adresse einer detektierten, fehlerhaften Datenspeichereinheit vorübergehend zu speichern, und dass die flüchtigen Speicherelemente (22) durch eine sequentielle Verbindung vom Verkettungs-Typ verbunden sind, um flüchtige Redundanz-Information in sequentieller Weise zu speichern. Vorrichtung nach Anspruch 1,

weiterhin mit mindestens einer nichtflüchtigen Speichereinheit (18) zum nichtflüchtigen Speichern der Redundanz-Information; und mit einem Datenbus (11), der mit der Redundanz-Detektionseinheit (15) und der nichtflüchtigen Speichereinheit (18) verbunden ist, um Adressen von fehlerhaften Datenspeichereinheiten (19a) von der Redundanz-Detektionseinheit (15) zu der nichtflüchtigen Speichereinheit (18) zu transferieren und die Adressen der fehlerhaften Datenspeichereinheiten nach dem Datenmodifikationsvorgang in dieser zu speichern.
Vorrichtung nach Anspruch 2,

weiterhin mit Dekodier-, Adressier- und Leseschaltungen (3, 4), die mit der Speicheranordnung (2) verbunden sind, wobei die nichtflüchtige Speichereinheit (18) mit den Dekodier-, Adressier- und Leseschaltungen verbunden ist.
Vorrichtung nach Anspruch 3,

mit einem Adressenbus (8), der mit den Dekodier-, Adressier- und Leseschaltungen (3, 4) und mit der Redundanz-Detektionseinheit (15) verbunden ist, wobei die Redundanz-Detektionseinheit eine durch die Steuereinheit (16) freigegebene Führungseinrichtung (20, 40) aufweist, um den Adressenbus bei Detektion einer fehlerhaften Datenspeichereinheit (19a) mit dem Datenbus (11) zu verbinden.
Vorrichtung nach einem der vorausgehenden Ansprüche,

mit einem Adressenbus (8), wobei die Redundanz-Detektionseinheit (15) Folgendes aufweist: eine mit dem Adressenbus verbundene Eingangseinrichtung (20), einen mit der Eingangseinrichtung verbundenen Redundanz-Bus (21), eine Mehrzahl von Registern (22), die die flüchtigen Speicherelemente bilden und aus einem ersten Bereich (22a) zum Speichern einer Adresse einer fehlerhaften Datenspeichereinheit (19a) in jedem Register sowie aus einem zweiten Bereich (22b) zum Speichern von Schutzinformation (G) gebildet sind, wobei der erste Bereich einen mit dem Redundanz-Bus (21) verbundenen Dateneingang (D) und einen Freigabeeingang (CK) aufweist; und eine Freigabeschaltung (23), die mit den Freigabeeingängen der Register und mit der Steuereinheit (16) verbunden ist, um die Register zum Laden von Adressen von dem Redundanz-Bus (21) in sequentieller Weise freizugeben.
Vorrichtung nach Anspruch 5,

wobei jedes der Register (22) einen mit einem jeweiligen zweiten Bereich (22b) verbundenen Schutzausgang (G) aufweist und wobei die Freigabeschaltung (23) eine Mehrzahl von Freigabeelementen (23) aufweist, und zwar eines pro Register, wobei jedes Freigabeelement einen mit dem Schutzausgang (G) eines jeweiligen Registers (G) verbundenen ersten Eingang (24), einen zweiten Eingang (25), der ein Lastsignal (L) von der Steuereinheit (16) erhält, sowie einen dritten Eingang (26) aufweist, der mit einem Schutzausgang (G) eines vorangehenden Registers (22) in der sequentiellen Verbindung verbunden ist.
Vorrichtung nach Anspruch 5 oder 6,

wobei die Redundanz-Detektionseinheit (15) ferner eine Mehrzahl von Vergleichsgliedern (30) aufweist, und zwar eines pro Register (22), wobei jedes Vergleichsglied einen mit dem Redundanz-Bus (21) verbundenen ersten Eingang, einen mit dem Datenausgang (Q) eines jeweiligen Registers verbundenen zweiten Eingang sowie einen Ausgang aufweist, der ein Erkennunssignal (DIS) zum Sperren einer fehlerhaften Datenspeichereinheit (19a) liefert, wobei die Vergleichsglieder (30) eine Freigabeeinrichtung zum Freigeben einer jeweiligen Redundanz-Speichereinheit (19b) aufweisen.
Vorrichtung nach Anspruch 7,

wobei jedes Vergleichsglied (30) mit einer jeweiligen Redundanz-Speichereinheit (19b) fest verbunden ist.
Vorrichtung nach einem der Ansprüche 5 bis 7,

wobei jedes Register einen dritten Bereich (92) zum Speichern der Adresse einer Redundanz-Speichereinheit (19b) aufweist.
Redundanz-Verfahren in einer nichtflüchtigen Speichervorrichtung (1) mit einer Speicheranordnung (2), die aus einer Mehrzahl von nichtflüchtigen Datenspeichereinheiten (19a) gebildet ist, wobei das Verfahren einen Datenmodifikationsvorgang und einen Lesevorgang aufweist,

wobei der Datenmodifikationsvorgang folgende Schritte aufweist: Zuführen (52) eines Datenmodifikationsbefehls zu mindestens einer der Datenspeichereinheiten (19a); Verifizieren (54) der Korrektheit der Daten in der mindestens einen Datenspeichereinheit; bei Detektion eines Fehlers in der mindestens einen Datenspeichereinheit während des Datenmodifikationsvorgangs, vorübergehendes Speichern (74) der Adresse der fehlerhaften Datenspeichereinheit in einer Redundanz-Detektionseinheit (15), die flüchtige Speicherelemente (22) beinhaltet, die durch eine sequentielle Verbindung vom Verkettungs-Typ miteinander verbunden sind, um flüchtige Redundanz-Information in sequentieller Weise zu speichern; und wobei der Lesevorgang folgende Schritte aufweist: Erzeugen einer Leseadresse einer Datenspeichereinheit; Vergleichen (30) der Leseadresse mit der in der Redundanz-Detektionseinheit (15) gespeicherten Adresse; und im Fall der Übereinstimmung, Sperren der Leseadresse und Freigeben einer Redundanz-Speichereinheit.
Verfahren nach Anspruch 10,

bei dem weiterhin nach dem Schritt des vorübergehenden Speicherns (74) die Adresse in einer nichtflüchtigen Speichereinheit (18) in nichtflüchtiger Weise gespeichert (75) wird.
Verfahren nach Anspruch 11,

bei dem vor dem Schritt des vorübergehenden Speicherns (74) und dem Schritt des Speicherns (75) in nichtflüchtiger Weise der Schritt des Zuführens (52) eines Datenmodifikationsbefehls und der Schritt des Verifizierens (54) im Fall eines negativen Resultats des Schrittes des Verifizierens höchstens eine erste Anzahl von Malen wiederholt werden,

und nach den Schritten des vorübergehenden Speicherns (74) und des Speicherns (75) in nichtflüchtiger Weise der Schritt des Zuführens (52) eines Datenmodifikationsbefehls und der Schritt des Verifizierens (54) im Fall eines negativen Resultats des Verifizierschrittes höchstens eine zweite Anzahl von Malen wiederholt werden und nach der zweiten Anzahl von Malen ein Fehlersignal erzeugt wird.
Verfahren nach Anspruch 12,

bei dem ferner im Fall eines negativen Resultats des Schrittes des Verifizierens sowie vor einer Wiederholung des Schrittes des Zuführens (52) eines Datenmodifikationsbefehls und des Schrittes des Verifizierens (54) die Adresse der soeben überprüften Daten geschrieben wird, wobei nach der Wiederholung des Schrittes des Zuführens (52) die geschriebene Adresse gelesen (53) wird.
Anspruch[en]
A nonvolatile storage device (1), comprising: a memory array (2) divided into a plurality of non-volatile data-storage units (19a); a control unit (16) including data-modification control means activating a data modification operation on said data-storage units, said control unit further comprising detection means enabled during said data modification operation for detecting the functionality of said data-storage units; a redundancy-detection unit (15), enabled by said control unit, said redundancy-detection unit including volatile-memory elements (22); and a plurality of non-volatile redundancy-storage units (19b) for replacing respective failed data-storage units, characterized in that said redundancy-detection unit (15) is enabled by said control, unit (16) during said data modification operation for temporarily storing the address of a detected failed data-storage unit and in that said volatile-memory elements (22) are connected through a sequential connection of a daisy-chain type to sequentially storing volatile redundancy information. The device according to claim 1, further comprising at least one nonvolatile memory unit (18) for nonvolatile-storing of said redundancy information; and a data bus (11) connected to said redundancy-detection unit (15) and said nonvolatile memory unit (18) for transferring addresses of failed data-storage units (19a) from said redundancy-detection unit (15) to said nonvolatile memory unit (18) and storing said addresses of said failed data-storage units therein after said data modification operation. The device according to claim 2, comprising decoding, addressing and reading circuits (3, 4), connected to said memory array (2), said nonvolatile memory unit (18) being connected to said decoding, addressing and reading circuits. The device according to claim 3, comprising an address bus (8) connected to said decoding, addressing and reading circuits (3, 4) and to said redundancy-detection unit (15), said redundancy-detection unit comprising routing means (20, 40) enabled by said control unit (16) for connecting said address bus to said data bus (11) upon detection of a failed data-storage unit (19a). The device according to any one of the foregoing claims, comprising an address bus (8), wherein said redundancy-detection unit (15) comprises: input means (20), connected to said address bus, a redundancy bus (21), connected to said input means, a plurality of registers (22) forming said volatile-memory elements, made up of a first portion (22a) for storing, in each register, an address of a failed data-storage unit (19a), and a second portion (22b) for storing a guard information (G), said first portion having a data input (D) connected to said redundancy bus (21) and an enable input (CK); and an enabling circuit (23), connected to said enable inputs of said registers and to said control unit (16) for sequentially enabling said registers to load addresses from said redundancy bus (21). The device according to claim 5, wherein each of said registers (22) comprises a guard output (G) connected to a respective second portion (22b), and wherein said enabling circuit (23) comprises a plurality of enabling elements (23), one for each register, each enabling element having a first input (24) connected to said guard output (G) of a respective register (G), a second input (25) receiving a load signal (L) from said control unit (16), and a third input (26) connected to a guard output of a preceding register (22) in said sequential connection. The device according to claim 5 or 6, wherein said redundancy-detection unit (15) further comprises a plurality of comparison gates (30), one for each said register (22), each comparison gate having a first input connected to said redundancy bus (21), a second input connected to a data output (Q) of a respective register, and an output supplying a recognition signal (DIS) for disabling a failed data-storage unit (19a), said comparison gates (30) having enabling means for enabling a respective redundancy-storage unit (19b). The device according to claim 7, wherein each comparison gate (30) is rigidly connected to a respective redundancy-storage unit (19b). The device according to any one of claims 5-7, wherein each said register comprises a third portion (92) for storing the address of a redundancy-storage unit (19b). A redundancy method in a nonvolatile storage device (1) comprising a memory array (2) made up of a plurality of nonvolatile data-storage units (19a), the method comprising a data-modification operation and a read operation,

said data-modification operation comprising the steps of: supplying (52) a data-modification command to at least one of said data-storage units (19a); verifying (54) the correctness of the data in said at least one data-storage unit; in the event of an error being detected in said at least one data-storage unit during said data-modification operation, temporarily storing (74) the address of the failed data-storage unit in a redundancy-detection unit (15) including volatile-memory elements (22) connected to each other through a sequential connection of a daisy-chain type to sequentially storing volatile redundancy information; and said read operation comprises the steps of: generating a read address of a data-storage unit; comparing (30) said read address to said address stored in said redundancy-detection unit (15); and in the event of equality, disabling said read address and enabling a redundancy-storage unit.
The method according to claim 10, further comprising, after the step of temporarily storing (74), storing (75) said address in a nonvolatile way in a nonvolatile memory unit (18). The method according to claim 11, wherein before said step of temporarily storing (74) and said step of storing (75) in a nonvolatile way, said step of supplying (52) a data-modification command and said step of verifying (54) are repeated, in the event of a negative result of said step of verifying, for at the most a first number of times,

and, after said steps of temporarily storing (74) and storing (75) in a nonvolatile way, said step of supplying (52) a data-modification command and said step of verifying (54) are repeated, in the event of a negative result of said step of verifying, for at the most a second number of times, and after said second number of times an error signal is generated.
The method according to claim 12, further comprising, in the event of a negative result of said step of verifying and before repeating the steps of supplying (52) a data-modification command and verifying (54), writing the address of said data just checked, wherein, after repeating the step of supplying (52), said written address is read (53).
Anspruch[fr]
Dispositif de mémoire non volatile (1), comprenant : une matrice de mémoire (2) divisée en une pluralité d'unités de stockage de données non volatile (19a) ; une unité de commande (16) comprenant des moyens de commande de modification de données activant une opération de modification de données sur lesdites unités de stockage de données, ladite unité de commande comprenant en outre des moyens de détection activés pendant ladite opération de modification de données pour détecter la fonctionnalité desdites unités de stockage de données ; une unité de détection de redondance (15), activée par ladite unité de commande, ladite unité de détection de redondance comprenant des éléments à mémoire volatile (22) ; et une pluralité d'unités de stockage de redondance non volatile (19b) pour remplacer des unités de stockage de données défaillantes respectives, caractérisé en ce que ladite unité de détection de redondance (15) est activée par ladite unité de commande (16) pendant ladite opération de modification de données pour stocker temporairement l'adresse d'une unité de stockage de données défaillante détectée et en ce que lesdits éléments à mémoire volatile (22) sont connectés par l'intermédiaire d'une connexion séquentielle en guirlande pour stocker séquentiellement des informations de redondance volatiles. Dispositif selon la revendication 1, comprenant en outre au moins une unité à mémoire non volatile (18) pour stocker de façon non volatile lesdites informations de redondance; et un bus de données (11) connecté à ladite unité de détection de redondance (15) et à ladite unité à mémoire non volatile (18) pour transférer des adresses d'unités de stockage de données défaillantes (19a) depuis ladite unité de détection de redondance (15) vers ladite unité à mémoire non volatile (18) et y stocker lesdites adresses desdites unités de stockage de données défaillantes après ladite opération de modification de données. Dispositif selon la revendication 2, comprenant des circuits de décodage, d'adressage et de lecture (3, 4), connectés à ladite matrice de mémoire (2), ladite unité à mémoire non volatile (18) étant connectée auxdits circuits de décodage, d'adressage et de lecture. Dispositif selon la revendication 3, comprenant un bus d'adresses (8) connecté auxdits circuits de décodage, d'adressage et de lecture (3, 4) et à ladite unité de détection de redondance (15), ladite unité de détection de redondance comprenant des moyens de routage (20, 40) activés par ladite unité de commande (16) pour connecter ledit bus d'adresses audit bus de données (11) lors de la détection d'une unité de stockage de données défaillante (19a). Dispositif selon l'une quelconque des revendications précédentes, comprenant un bus d'adresses (8), dans lequel ladite unité de détection de redondance (15) comprend : des moyens d'entrée (20), connectés audit bus d'adresses, un bus de redondance (21), connecté auxdits moyens d'entrée, une pluralité de registres (22) formant lesdits éléments à mémoire volatile, constitués d'une première partie (22a) pour stocker, dans chaque registre, une adresse d'une unité de stockage de données défaillante (19a), et d'une deuxième partie (22b) pour stocker une information de garde (G), ladite première partie ayant une entrée de données (D) connectée audit bus de redondance (21) et une entrée d'activation (CK) ; et un circuit d'activation (23), connecté auxdites entrées d'activation desdits registres et à ladite unité de commande (16) pour permettre séquentiellement auxdits registres de charger des adresses à partir dudit bus de redondance (21). Dispositif selon la revendication 5, dans lequel chacun desdits registres (22) comprend une sortie de garde (G) connectée à une deuxième partie respective (22b), et dans lequel ledit circuit d'activation (23) comprend une pluralité d'éléments d'activation (23), un pour chaque registre, chaque élément d'activation ayant une première entrée (24) connectée à ladite sortie de garde (G) d'un registre respectif (G), une deuxième entrée (25) recevant un signal de chargement (L) de la part de ladite unité de commande (16), et une troisième entrée (26) connectée à une sortie de garde d'un registre précédent (22) dans ladite connexion séquentielle. Dispositif selon la revendication 5 ou 6, dans lequel ladite unité de détection de redondance (15) comprend en outre une pluralité de portes de comparaison (30), une pour chacun desdits registres (22), chaque porte de comparaison ayant une première entrée connectée audit bus de redondance (21), une deuxième entrée connectée à une sortie de données (Q) d'un registre respectif, et une sortie délivrant un signal de reconnaissance (DIS) pour désactiver une unité de stockage de données défaillante (19a), lesdites portes de comparaison (30) ayant des moyens d'activation pour activer une unité de stockage de redondance respective (19b). Dispositif selon la revendication 7, dans lequel chaque porte de comparaison (30) est connectée de manière rigide à une unité de stockage de redondance respective (19b). Dispositif selon l'une quelconque des revendications 5 à 7, dans lequel chacun desdits registres comprend une troisième partie (92) pour stocker l'adresse d'une unité de stockage de redondance (19b). Procédé de redondance dans un dispositif de mémoire non volatile (1) comprenant une matrice de mémoire constituée d'une pluralité d'unités de stockage de données non volatile (19a), le procédé comprenant une opération de modification de données et une opération de lecture,

ladite opération de modification de données comprenant les étapes consistant à : délivrer (52) une commande de modification de données à au moins une desdites unités de stockage de données (19a) ; vérifier (54) l'exactitude des données dans ladite au moins une unité de stockage de données ; en cas de détection d'erreur dans ladite au moins une unité de stockage de données pendant ladite opération de modification de données, stocker temporairement (74) l'adresse de l'unité de stockage de données défaillante dans une unité de détection de redondance (15) comprenant des éléments à mémoire volatile (22) connectés les uns aux autres par l'intermédiaire d'une connexion séquentielle en guirlande pour stocker séquentiellement des informations de redondance volatiles ; et ladite opération de lecture comprend les étapes consistant à : générer une adresse de lecture d'une unité de stockage de données ; comparer (30) ladite adresse de lecture à ladite adresse stockée dans ladite unité de détection de redondance (15) ; et en cas d'égalité, désactiver ladite adresse de lecture et activer une unité de stockage de redondance.
Procédé selon la revendication 10, comprenant en outre, après l'étape de stockage temporaire (74), l'étape consistant à stocker (75) ladite adresse de façon non volatile dans une unité à mémoire non volatile (18). Procédé selon la revendication 11, dans lequel avant ladite étape de stockage temporaire (74) et ladite étape de stockage (75) de façon non volatile, ladite étape de délivrance (52) d'une commande de modification de données et ladite étape de vérification (54) sont répétées, en cas de résultat négatif de ladite étape de vérification, pendant tout au plus un premier nombre de fois,

et, après lesdites étapes de stockage temporaire (74) et de stockage (75) de façon non volatile, ladite étape de délivrance (52) d'une commande de modification de données et ladite étape de vérification (54) sont répétées, en cas de résultat négatif de ladite étape de vérification, pendant tout au plus un second nombre de fois, et après le second nombre de fois, un signal d'erreur est généré.
Procédé selon la revendication 12, comprenant en outre, en cas de résultat négatif de ladite étape de vérification et avant la répétition des étapes de délivrance (52) d'une commande de modification de données et de vérification (54), une étape d'écriture de l'adresse desdites données venant d'être vérifiées, dans lequel, après la répétition de l'étape de délivrance (52), ladite adresse écrite est lue (53).






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