The present invention relates to a nonvolatile storage
device and a self-redundancy method of the same.
As it is known, redundancy structures are provided for
replacing failed memory locations so as to prevent the rejection of the entire storage
Normally, the replacement of the failed memory location
with the redundancy part takes place in final production steps, when a special test,
referred to as electrical wafer sorting (EWS), detects a failure.
The structure commonly used for storing the addresses of
redunded or replaced memory locations is principally made up of CAM banks, i.e.,
nonvolatile storage units, programmable and erasable by the manufacturer in the
testing step. In particular, when a failure is detected in a memory location, information
designed to determine uniquely the memory location to be replaced is stored in the
The information stored in the CAMs may be of various kinds:
the addresses of the location to be repaired, whether and which bit packet of the
word addressed is to be replaced, whether an entire sector is to be replaced, whether
the bank has already been used for storing an address of a failed location or not
(guard information), etc.
The number of banks used in the redundancy structure defines
the maximum number of packets (columns, bytes, rows, sectors hereinafter indicated
also as memory units or memory locations) that can be replaced in the entire memory
array. When, then, the location has been replaced, it is necessary to carry out
a number of operations for identifying the location that stores the information
instead of the failed location.
The check and the possible redundancy replacement are carried
out for any operation, either reading or writing, that is to be performed on the
failed location, when addressing of the location is required.
The structure for managing redundancy has the function
of verifying whether the time location addressed is among the replaced ones and,
if so, provide for activation of the redundancy locations and to the simultaneous
de-activation of the decoding of the memory array corresponding to the defective
In particular, the address of the location that is to be
read or written (program or erase) is compared with the addresses of the replaced
locations during the testing steps and, in the event of coincidence with one of
them, a "hit" signal is generated that has the task of activating the redundancy
circuitry and of replacing the failed location (whether it be a bit, a byte, a word,
or a sector) by physically pointing to the redundancy unit.
In the ensuing description, the discussion will be limited
to the case of sector redundancy. The following considerations, however, readily
applicable also to other types of redundancy, such as for example column redundancy.
In the literature, sector redundancy is complementary to
column redundancy and is preferred to row redundancy for high memory density devices
(i.e., with a density greater than or equal to 16 Mbits). Furthermore, sector redundancy
is preferred as regards area, speed and performance of the memory during reading
operations, and finally because of a greater flexibility in solving serious problems
that may arise in the array, such as for example shorts between wordlines and substrate.
At present, the common sector redundancy envisages a plurality
of redundancy units, which, for area efficiency and yield, may be expressed as a
redundancy unit (a redundancy sector) for each multiple of 16 Mbits. Each redundancy
unit is therefore associated to a CAM comprising a plurality of nonvolatile cells,
equal to the number of bits of the address necessary for identifying each sector
of the memory array. Each CAM thus identifies a failed sector.
Furthermore, a further nonvolatile memory element, referred
to as guard CAM, is associated to each redundancy unit and stores a guard information
specifying whether the associated redundancy unit has been used or not.
During reading or programming of cells of the memory array,
the comparison between the addresses supplied from outside by the user and the ones
stored in the CAMS generates, in the presence of the guard information activated,
the "hit" signal mentioned above.
In present memory architectures, the content of the CAMs,
programmed, as has been said, during the EWS testing step, is read continuously
throughout the lifetime of the device, using a structure the cells whereof are directly
connected, through the drain terminal, to latches that buffer the content of the
information present in the CAMs.
Programming is performed by using the same switch structure
(the so-called "program loads") present in the array, disabling the array-decoding
circuits, enabling the redundancy ones, and causing the datum to move (drain voltage)
along bitlines (main bitline in the case of a hierarchical architecture) present
in the memory array.
Examples of architectures and methods for replacing failed
cells during EWS test or other tests by standard fuse elements are disclosed, e.g.,
EP 0 805 451
EP 0 867 810
EP 1 107 121
teaches a non-volatile memory device having the features of the preamble
of claim 1 and including a testing mode for judging the validity of initially-setting
data, including addresses of defective cells.
This architecture does not enable ease of activation and
management of redundancy for addressing the nonvolatile cells during normal operation
of the device by using an automatic replacement algorithm that exploits structures
and circuits already present in the device.
The aim of the invention is consequently to provide a storage
device and a method that enable activation and management of redundancy during normal
operation using the circuits already present in the array for reading, programming,
erasing and verifying.
According to the present invention, a nonvolatile storage
device and a redundancy method are provided, as defined in claims 1 and 10, respectively.
For a better understanding of the present invention, a
preferred embodiment is now described, purely by way of nonlimiting example, with
reference to the attached drawings, wherein:
- Figure 1 illustrates a block diagram of a storage device according to the invention;
- Figure 2 is a simplified circuit diagram of a block of Figure 1, according to
- Figures 3 and 4 are flowcharts of the method according to the invention; and
- Figure 5 illustrates a diagram of the association between registers and redundancy
sectors, according to the invention.
In the device and method described in detail hereinafter,
the reading structure already present for reading the array, the structure storing
the sectors for managing failures and sectors to be erased, and the counter of the
present addresses are used. In this way, even the entire testing structure and the
testing procedure of the DMA test, shadow test, and CAM program-and-erase test,
may be kept unaltered.
For a better understanding of the invention, the simplified
structure of a memory 1, of a flash type, as modified according to the invention
for the implementation of self-redundancy, is now described with reference to Figure
The memory 1 comprises a memory array 2 made up of standard
sectors 19a (only two of which are shown) and of redundancy sectors 19b (only two
of which are shown). The memory array 2 is connected, in a known way, to a row-decoder
block 3 and to a column-decoder block 4. The column-decoder block 4 further comprises
sense amplifiers SA and program loads, both built according to a known structure.
An address-counter block 5 has an input connected to an
address-input gate 6, from which it receives, from outside, general addresses ADD;
the address-counter block 5 generates, under the control of a state machine 12,
internal addresses for addressing the memory array 2, supplied on an address bus
8 (ADDBUS). The address bus 8 is connected to the row-decoder and column-decoder
blocks 3, 4 and to a redundancy-detection unit 15 (the structure whereof will now
be described in greater detail with reference to Figure 2). The address-counter
block 5 is moreover connected, through the address bus 8, to a RAM 7, which constitutes
a sector memory.
In detail, as is represented schematically in the enlarged
detail, the RAM 7 is divided into a plurality of portions or rows 14, one for each
sector of the memory array 2, each portion 14 comprising a first subportion 14a
and a second subportion 14b. During erasing, the first subportion 14a stores the
address of a memory location where checking must start after application of the
erasing pulses (and thus operates as a pointer), while the second subportion 14b
stores a flag, the logic state of which indicates whether the associated sector
is to be erased or not.
The address counter 5 is moreover connected to a sense-timing
circuit 9, which supplies appropriate enabling signals to the row-decoder and column-decoder
blocks 3, 4 as well as to a data-input/output unit 10. The data-input/output unit
10 is moreover connected to a data bus DBUS 11, which is in turn connected to the
column-decoder block 4, to the state machine 12, to the redundancy-detection unit
15, to the RAM 7, and to a state register 17.
The state machine 12 exchanges information with a microprocessor
control unit 16 and sends state information to the state register 17. The control
unit 16 moreover exchanges information and commands with the redundancy-detection
unit 15 and the RAM 7.
The redundancy-detection unit 15 is moreover connected
to the row-decoder and column-decoder blocks 3, 4, and to the CAMs 18 (just one
of which is shown), designed for storing the addresses of the replaced sectors.
The CAMs 18 are functionally associated to the memory array 2, and share with this
the same address and read circuits. Hence, for simplicity, in Figure 1 the CAMs
18 are represented as belonging to the memory array, even though they may be physically
separate, albeit contiguous thereto.
As explained in greater in detail hereinafter, at turning-on
of the memory, the redundancy-detection unit 15 receives from the memory array 2,
and precisely from the CAMs 18, read via the column-decoder block 4, the previously
stored redundancy data and writes them, in a volatile way, in registers where they
are immediately accessible. Consequently, when the address counter 5 supplies the
row and column addresses of words to be read, the redundancy-detection unit 15 compares
the addresses received on the data bus 11 with the ones stored in its own registers,
and, if it detects an identity, replaces the addresses received with the redundancy
ones so as to address the redundancy sectors 19b, as explained in detail hereinafter
with reference to Figure 2.
Furthermore, during erasing and programming, when a failure
is detected in one or more standard sectors 19a, the redundancy-detection unit 15
receives the addresses of the failed sectors, supplied by the address counter 5
on the address bus 8, and, under appropriate control of the control unit 16, writes
them in a temporary way in its own registers and subsequently, via the data bus
11, in the CAMs 18.
Hereinafter the structure of the redundancy-detection unit
15 is described as regards redundancy during the operation of the device (erasing,
as described below with reference to Figures 3 and 4, or else programming and reading).
With reference to Figure 2, the redundancy-detection unit
15 comprises a switching gate 20 having a first data input connected to the data
bus 11, a second data input connected to the address bus 8, a selection input receiving
a first control signal SEL1 from the control unit 16, and an output connected to
a redundancy bus 21. The output of the switching gate 20 is moreover connected to
the storage bus 11 via a buffer 40 controlled by a second control signal SEL2, supplied
by the control unit 16.
The redundancy bus 21 is connected to the data input D
of a plurality of registers 22 (in the example three are shown), designated by 221,
222, 223, daisy-chain connected and made up of latches. In
general, the number of registers 22 is equal to the number of available redundancy
resources (number of redundancy sectors 19b) and of self-redundancy CAMs 18.
In detail, each register 22 is divided into two parts:
a first part 22a, for storing an entire address of a failed sector, and a second
part 22b, for storing a guard bit, the logic value whereof is indicative of whether
the corresponding register 22 has already been loaded or not with an address of
a failed sector. Each register 22 further comprises a synchronization input CK,
a guard output G (connected to the second part 22b), and an output address Q, connected
to the second portion 22b.
The registers 221, 222, 223
have the synchronization input CK connected to the output of a respective AND gate
231, 232, 233. The AND gates 231, 232,
233 are of the three-input type: a first input 24, of a inverted type,
is connected to the guard output G of a respective register 221, 222,
223 and receives an inverted guard bit GN equal to the corresponding
inverted guard bit; a second input 25 receives a load signal L supplied by the control
unit 16; and a third input 26 is connected to the guard output of a preceding register,
except for a first register 221. In detail, the first register 221
has the third input 26 connected in a fixed way to a voltage corresponding to a
logic level "1"; a second register 222 has the third input 26 connected
directly to the guard output G of the first register 221; and the third
register 223 has the third input 26 connected directly to the guard output
G of the second register 222. Other possible registers are likewise connected
starting from the third register 223.
The last register (here the third register 223)
has the guard output G connected to the control unit 16, which supplies a signal
NO_RIS, the logic value of which indicates whether further free redundancy resources
are present or not.
The address outputs Q of the registers 221,
222, 223 are connected each to a first input of a respective
XNOR gate 30.
The XNOR gates 30 moreover have a second input connected
to the redundancy bus 21, and a first output connected to a logic adder circuit
31, which outputs a disable signal DIS supplied to the row-decoder and column-decoder
blocks 3, 4 of Figure 1. Each of the XNOR gates 30 further have a second output
connected rigidly to a respective redundancy sector 19b, for enabling thereof, as
The redundancy-detection unit 15 operates as described
hereinafter. As soon as redundancy is activated following upon the detection of
one or more failed sectors after a modification operation (as described in detail
hereinafter with reference to Figures 3 and 4 for erasing), the switching gate 20
is controlled by the first selection signal SEL1 so as to connect the address bus
8 to the redundancy bus 21. In this step, the buffer 40 is still inactive, and the
address bus 8 supplies, in addition to the address of a failed sector, the guard
bit, having logic value "1". This bit is programmed after the address information
has been programmed in the CAMs. In this way, in the event of an accidental power-down
between programming the addresses and programming the guard bit, it notifies the
fact that the programmed information is incomplete.
Assuming that the redundancy has not yet been activated
previously, the first register 221 is still empty and its guard bit G
is still in the inactive state, corresponding to a logic "0"; consequently the inverted
guard bit GN is equal to "1". Hence, as soon as the load signal L switches to the
high state, the first AND gate 231 supplies, to the synchronization input
CK, a "1", which enables loading of the address and of the guard bit supplied on
the redundancy bus 21 inside the first register 221.
Instead, when the load signal L switches, the second and
the third AND gates 232, 233 receive the previous value of
the guard bit G of the first and second registers 231, 232
(still at "0") and consequently are not enabled for loading.
In this step, the XNOR gates 30 and the logic adder circuit
31 are practically disabled or in any case supply non-significant signals, which
are ignored by the row-decoder and column-decoder blocks 3, 4.
At the subsequent redundancy activations, the data are
loaded each time into a subsequent register 222, 223. In fact,
at the second activation, the first register 221 disables its own AND
gate 231 and enables the subsequent AND gate 232, since it
has the guard bit G in the high state. Next, upon arrival of the load signal L,
the address and the guard bit are stored in the second register 222.
The third register 223 and possible subsequent registers remain, however,
In this way, it is possible to store the address of a number
of failed sectors equal to the number of registers 22 present.
After all the registers 22 have been loaded, the high value
of the guard bit G of the last register (here the third register 223),
which constitutes the signal NO RIS, signals that there are no longer available
further redundancy resources.
Immediately after loading the address of a failed sector
in one of the registers 22, this is stored in a nonvolatile way in a CAM 18. To
this end, the address of the failed sector, still present on the address bus 8,
is supplied to the data bus 11 via the switching gate 20 and the buffer 40, now
activated by the second selection signal SEL2. Consequently, the address of the
failed sector is supplied to the column-decoder block 4, as explained in detail
Upon turning-on of the memory 1, when the POR (Power-On
Reset) signal is generated, the contents of the CAMs 18 that store the addresses
of the failed sectors previously detected are supplied in a sequential way on the
data bus 11 and are loaded sequentially into the registers 22 via the switching
gate 20, which now connects the data bus 11 to the address bus 8 on a command from
the control unit 16. Loading takes place sequentially in the different registers
22, in a manner similar to what is described above. In this way, at each turning-on
of the memory, the registers 22 are loaded with the redundancy data previously stored.
During reading, the address supplied on the address bus
8 is fed, by the redundancy bus 21, to the XNOR gates 30, which compare it to the
failed-sector address supplied by the respective register 22. If the address supplied
on the address bus 8 does not correspond to any of the addresses stored by the registers
22, the XNOR gates generate a non-recognition signal (disable signal DIS in the
inactive state), and the row-decoder and column-decoder blocks 3, 4 operate in the
usual way on the basis of the address present on the address bus 8. Instead, if
one of the XNOR gates recognizes the equality with the address stored in the associated
register 22, it generates a recognition signal, which is supplied to the logic adder
circuit 31. Consequently, in this step, the disable signal DIS goes into the active
state and disables the address present on the address bus 8 (disabling of the standard
sector 19a addressed by the address counter 5 of Figure 1). Furthermore, the XNOR
gate 30, which has recognized the equality, enables the redundancy sector 19b associated
Hereinafter, with reference to Figures 3 and 4, the procedure
for erasing groups of sectors is described, where activation of redundancy on-line
is carried out when detecting failed memory locations.
This procedure uses the RAM 7 of Figure 1, wherein the
flags corresponding to the sectors to be erased are set in the second subportions
14b (flags in the active state), in a known way, before activating erasing. The
RAM 7 thus represents a list of sectors to be erased, identified by the respective
flags in active state.
In the ensuing description, it is moreover assumed that
one or more sectors belonging to a preset group are to be erased; the same procedure
is, however, applicable to the entire memory array.
Initially, step 50, the first subportions 14a of the portions
14 having flags in the set or active state (and consequently corresponding to the
sectors to be erased) are reset, so as to contain the address of the first word
of each respective sector. In addition, a sector counter is initialized with the
first sector of the considered sector group.
Next, step 51, a check is made to see whether all the blocks
to be erased have actually been erased by checking the state of the flags. If they
have (all the flags in the inactive state), erasing terminates; otherwise, an erasing
pulse is sent to all the sectors identified by the flags in the active state, step
Next, step 53, the address stored in the first subportion
14a corresponding to the first sector of the list that has an active flag is read.
As said, this address corresponds initially to the first word of the sector; hereinafter,
as described below, it represents the address of the last word of the sector that
has been checked (and for which the check has not been successful).
Subsequently, step 54, the considered sector is checked,
starting from the word identified by the address just read and proceeding until
the entire sector has been checked or detecting a word not correctly erased. If
the entire sector has been erased (output YES from step 55), the flag corresponding
to the sector just erased is reset (i.e., it is brought to the inactive state) by
erasing in practice the sector itself from the list of the sectors to be erased,
step 60. Then, the procedure goes to step 62, as described below.
If the check is interrupted on account of the detection
of a word not correctly erased, output NO from step 55, the first subportion 14a
is written with the address of the word just checked and for which the check has
given a negative result, step 61. Then, a check is made to see whether the sector
just checked is the last in the list, step 62.
If there are still sectors to be checked, output NO from
step 62, a next sector is addressed, incrementing the sector counter, step 63, and
then the procedure returns to step 53, where the address stored in the first subportion
14a of the RAM 7 and corresponding to the next sector just addressed is read. Instead,
if all the sectors have been checked (but, of course, some contain words not correctly
erased), output YES from step 62, a number-of-attempts counter I is incremented,
This counter (which indicates the number of supplied programming
pulses) has the purpose of enabling the repetition of the cycle that comprises applying
an erasing pulse and verifying the cells of the sectors starting from the ones that
have yielded a negative result in the previous check. Only if, after a certain number
of cycles, at least one cell is still not correctly erased, a redundancy routine
is activated, and subsequently further cycles of erasing and verifying are repeated.
If after these further cycles the sectors are still not erased, an error signal
is generated ("fail").
For this purpose, after step 64, a check is made to see
whether the number-of-attempts counter I is equal to a first threshold value IMAX1.
If it is, a redundancy routine 70 is activated, described hereinafter with reference
to Figure 4, and the program goes back to step 53 for reading the address of the
first sector that has an active flag; otherwise, output NO from step 65, a check
is made to see whether the number-of-attempts counter I is equal to a second threshold
value IMAX2 greater than IMAX1, step 66. If not, the program
goes back to step 51 for checking whether all the sectors have been erased, to repeat
the cycle of applying erasing and verifying pulses, or to terminate the procedure,
if all the sectors have been erased. If they have (the number-of-attempts counter
I is equal to the second threshold value IMAX2), a failure signal is
generated, step 67, and the procedure terminates.
With reference to Figure 4, the redundancy routine 70 starts
with resetting the sector counter, step 71, and checking whether the first sector
addressed by the sector counter has already been erased, by reading the state of
the corresponding flag, step 72. If it has, a check is made to see whether all the
sectors have been checked, step 80; otherwise, a check is made to see whether the
sector currently addressed is already a redundancy sector or whether there are no
longer available further redundancy resources, step 73. If this is the case, it
is no longer possible to activate further redundancy resources; consequently, step
81, all the pointers are reset (addresses stored in the first subportions 14a of
the RAM 7), and the redundancy routine 70 terminates.
Instead, if redundancy resources are still available, output
NO from step 73, loading of the address of the current sector in the first register
22 available is commanded (according to the description made with reference to Figure
2), step 74, and the same current address is stored in a nonvolatile way in a CAM
18 (as previously described), step 75. Then, the program goes to step 80 for verifying
whether the presently addressed sector is the last of the list stored in the RAM
7. If not, step 82, the sector counter is incremented, and the procedure returns
to step 72; if it is, the program continues with step 81, as mentioned above. From
now on, the portion 14 of the RAM 7 previously associated to a failed sector stores
the information related to the redundancy sector that replaces it, and specifically
the address of the first word to be checked and the erasing flag. In this way, returning
to the main procedure of Figure 3, the redundancy sector or sectors just enabled
is/are erased and checked in the way described above.
After resetting the addresses loaded in the RAM 7, the
redundancy routine 70 terminates.
Figure 5 illustrates a structure of the registers 22 that
enables the redundancy of a redundancy sector in the event of a failure occurring
such as to render it unusable. For this purpose, instead of having a rigid association
between each register 22 and the corresponding redundancy sector, the association
is fixed when a failed sector is detected, and the address of the redundancy sector
is stored together with the address of the replaced sector.
In the example of Figure 5, each register 22 (and consequently
each CAM 18 storing the same data in a nonvolatile way) comprises a first portion
90 storing the address of a failed sector, a second portion 91 storing the guard
bit G, and a third portion 92 storing the address of the redundancy sector (which
replaces the sector the address whereof is stored in the first portion 90). In this
way, the association between each register and the corresponding redundancy sector
is not preset and is represented by the arrows. If the redundancy sector addressed
by the first register fails, for example, it would be possible to replace the address
of the failed redundancy sector with a further redundancy sector, as represented
by the dashed arrow.
This applies, in particular, for enabling the redundancy
of redundancy sectors activated during EWS.
The advantages of the described storage device are the
following. First, it enables replacement of a failed unit not only during testing
of the device inside the production plant (for example during EWS), but also when
the device is in operation. In this way, the storage device presents a greater flexibility,
and a consequent increase in yield.
Furthermore, it is possible to speed up also EWS testing,
thanks to the use of the control unit 16 inside the storage device and an embedded
algorithm, ruling out the need for any interfacing with external testing machines.
This enables a reduction in the testing effort (development resources and testing
times) aimed at identifying, at time zero, any failures that may occur subsequently
during the life of the device (cycling, dedicated testing).
The storage device described herein involves a minimum
increase in overall dimensions for the additional circuitry, thanks to the use principally
of structures already present.
In particular, the implementation described herein of self-redundancy
enables the use of the reading structure already present for operation of the memory
array 2, the re-use of the RAM 7 for managing the failed sectors and of the sectors
undergoing erasing, as well as the re-use of the address counter 5.
It is not necessary to use separate cells as CAMs, but
memory cells of the memory array may be used that are intended specifically for
The use of registers for loading redundancy information
during turning-on of the storage device enables rapid detection of any replacement
of a sector addressed to be read and addressing with the one operating correctly.
In practice, the registers 22 operate as the nonvolatile cells provided for traditional
EWS redundancy, at the same time guaranteeing a more agile management of the existing
The redundancy operations are altogether transparent to
the user (for example, during modification, the state register is accessible to
the user, either a product manager or a customer who requires information on the
state of the operations).
The registers 22 may be moreover equipped with set/reset
transistors for testing operations of a shadow type.
Finally, it is clear that numerous modifications and variations
may be made to the storage device and to the redundancy method described and illustrated
herein, all falling within the scope of the invention, as defined in the annexed
claims. For example, although the foregoing description refers only to sector redundancy,
as indicated, the invention is applicable also to redundancy of a different type,
for example column redundancy, byte redundancy, or row redundancy. Furthermore,
the redundancy may be activated also following upon an unsuccessful programming