PatentDe  


Dokumentenidentifikation EP1677203 22.11.2007
EP-Veröffentlichungsnummer 0001677203
Titel Datenübertragungsvorrichtung zur Übertragung von Flüssigkeitsausstoßdaten und Flüssigkeitsausstoßvorrichtung
Anmelder Seiko Epson Corp., Tokyo, JP
Erfinder Kimura, Masahiro, Suwa-shi Nagano-ken, JP;
Fukumitsu, Yasunori, Suwa-shi Nagano-ken, JP;
Yamamoto, Yasuhisa, Suwa-shi Nagano-ken, JP;
Igarashi, Masahiro, Suwa-shi Nagano-ken, JP
Vertreter derzeit kein Vertreter bestellt
DE-Aktenzeichen 60316856
Vertragsstaaten DE, GB
Sprache des Dokument EN
EP-Anmeldetag 26.08.2003
EP-Aktenzeichen 060058302
EP-Offenlegungsdatum 05.07.2006
EP date of grant 10.10.2007
Veröffentlichungstag im Patentblatt 22.11.2007
IPC-Hauptklasse G06F 13/28(2006.01)A, F, I, 20060606, B, H, EP
IPC-Nebenklasse G06K 15/10(2006.01)A, L, I, 20060606, B, H, EP   

Beschreibung[en]
BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a data transferring apparatus for transferring liquid ejection data and a liquid ejecting apparatus of liquid ejection data for transferring the liquid ejection data to a liquid ejecting head, in which the liquid ejection data is inputted into the liquid ejecting apparatus which ejects liquid such as ink from the liquid ejecting head onto a medium to be ejected.

Description of the Related Art

A liquid ejecting apparatus called an inkjet type printer records image data by ejecting ink droplets from a recording head onto recording papers. The inkjet type printer ejects ink droplets of plural colors from plural nozzle arrays which are provided at the head face of the recording head as developing image data, which has been compressed to be capable of being developed in line, to bitmap images in line and forming the developed bitmap images on the recording side of the recording papers. It forms images on the recording papers by ejecting ink droplets of plural colors to form plural ink dots. Further, the compressed data capable of being developed in line is, for example, the compressed data by the run length compression method which is generally widely known, capable of developing per byte unit sequentially. This inkjet type recording apparatus generally has a data transferring apparatus for receiving image data compressed to be capable of being developed in line inputted from an external apparatus such as a personal computer, developing (extracting) the inputted compressed data in line, performing data processes required for the developed bitmap images and then transferring the data to a register of the recording head. The generally conventional data transferring apparatus is configured, for example, as shown in Fig. 36.

The data transferring apparatus 10 has a system bus SB as a data transfer route. To the system bus SB a microprocessor (MPU) 11, a RAM 12 and a head controlling unit 13 are coupled so as to transfer data, and a recording head 62 is coupled to the head controlling unit 13. The compressed recording data transferred from an information processing apparatus such as a personal computer or a digital camera, which is not shown in drawings, is stored in the RAM 12 via the system bus SB.

The compressed recording data stored in a compressed data storing area of the RAM 12 is transferred to the microprocessor 11 via the system bus SB one byte each in order (a route represented by the symbol A), extracted by a program in accordance with an extraction sequence one byte each in order, then transferred to the RAM 12 via the system bus SB one byte each in order once more (a route represented by the symbol B) and then stored a desired bitmap image area of the RAM 12. When the developed data has been completely stored in the bitmap image area of the RAM 12, the developed data in the bitmap image area of the RAM 12 is transferred to the head controlling unit 13 via the system bus SB one byte each (a route represented by the symbol C) and ink is ejected from each of the nozzle arrays of the recording head 62 onto the recording papers based on these bitmap images. And, as an example of the prior art to speed up the data transfer process, it is well-known that two independent buses, a system bus and a local bus, are provided and two bus controllers are provided between the system bus and the local bus. In regard to the data transferring apparatus, parallel processing is performed, that is, one bus controller accesses a main memory which is coupled to the system bus while the other bus controller accesses the local memory which is coupled to the local bus so that the data transfer process can be speeded up as shown, for example, in Japanese Patent No. 3251053 .

To enhance the performance speed of liquid ejection with regard to the data transferring apparatus 10 of the conventional liquid ejecting apparatus configured as described above, in other words, to further increase the recording speed in regard to the inkjet type recording apparatus, there are some obstacles as mentioned below.

First, since the compressed recording data is developed (extracted) by a program one byte each, it is impossible to process a great quantity of compressed data at high speed. If the microprocessor 11, which operates at high speed clock with a high process capacity, is used, speeding up can be achieved, but it causes problems such that cost of the data transferring apparatus 10 gets extremely high if this expensive microprocessor 11 is mounted.

In addition, since both the data transfer to the RAM 12 and the data transfer from the RAM 12 are performed through the microprocessor 11, while the microprocessor 11 executes other data processes or calculations such that the microprocessor 11 fetches programs from the RAM 12, the data transfer might get into a waiting state, and thus the data transfer delay occurs, so that the data transfer at high speed cannot be achieved.

Further, in regard to the prior art disclosed in the Japanese Patent Publication No. 3251053 described above, the compressed recording data is also developed (extracted) by a program one byte each, so that a great amount of compressed data cannot be developed at high speed. Therefore, in regard to the liquid ejecting apparatus such as the recording apparatus which executes recording by developing the compressed recording data transferred from an information processing apparatus and then transferring it to the recording head, the speed of ejecting liquid cannot be enhanced because the process to develop the compressed data is still slow though the data transfer process can be performed at high speed.

Further, EP 0 802 503 A2 discloses a printer with a buffer memory formed with at least one buffer area, each for starting one band worth of print data.

SUMMARY OF THE INVENTION

It is the first object of the present invention to achieve development process of compressed data at high speed and the data transfer to the liquid ejecting head at high speed so that it is possible to considerably increase the liquid ejection speed of the liquid ejecting apparatus compared with that of the prior art.

In addition, it is the second object of the present invention to exactly nullify byte data which is not relevant in case the byte data irrelevant to the compressed liquid ejection data is included in and then securely develop only the compressed liquid ejection data from the head data.

Further, it is the third object of the present invention to realize the data transfer to the liquid ejecting head at high speed by performing a process rearranging the developed liquid ejection data for the liquid ejecting head so that it is possible to considerably increase the liquid ejection speed of the liquid ejecting apparatus compared with that of the prior art.

To achieve the objects above, according to the first aspect of the present invention, a data transferring apparatus for transferring liquid ejection data, comprises a decode unit comprising a decode circuit capable of performing hardware development on liquid ejection data, which is DMA-transferred per word unit from a main memory via a system bus, compressed to be capable of line development, a line buffer for storing liquid ejection data developed by the decode circuit per word unit and a DMA-transferring means for DMA-transferring liquid ejection data compressed to be capable of line development from the main memory to the decode circuit, DMA-transferring liquid ejection data developed in the line buffer to the local memory per word unit and DMA-transferring developed liquid ejection data stored in the local memory to a register of an liquid ejecting head sequentially, wherein the decode unit comprises a data storage starting position shifting means for storing liquid ejection data developed by the decode circuit from a first byte of the line buffer in a state where a 0-th byte of the line buffer is vacant.

First, since the data transfer of the compressed liquid ejection data from the main memory used to be performed one byte each in the conventional way is performed per word (two bytes) unit, the data transfer speed can be increased over two times. For example, if the system bus is a 16 bits bus, the compressed liquid ejection data stored in the main memory can be retrieved one word (two bytes) a time, and if the system bus is a 32 bits bus, the compressed liquid ejection data stored in the main memory can be retrieved two words (four bytes) a time.

In addition, the compressed liquid ejection data software-developed by a conventional program is hardware-developed by the decode circuit. That is, by independently performing only the development of the compressed data by the decode circuit which is exclusively used for developing compressed data rather than developing the compressed data by a program of single thread which performs various data processes in consecutive order besides the development process of the compressed data, it is possible to perform the development process of the compressed recording data at high speed. Further, the high speed data transfer can be achieved by the DMA transfer.

By the way, for example, the inkjet type recording apparatus as a liquid ejecting apparatus performs recording by ejecting ink from the plural nozzle arrays provided on the head face of the recording head as a liquid ejecting head onto the recording papers to form ink dots on the surface of the recording papers, based on the bitmap data to which the compressed recording data has been developed. However, when the developed bitmap data is stored in the bitmap area of the local memory and transferred to the recording head, there is a case that the data starting address of the bitmap data needs to be an odd address. Therefore, hitherto, after the compressed recording data is software-developed by a program, the developed bitmap data is transferred in order that the data starting address of the bitmap data can be an odd address by a program. However, if the bitmap data hardware-developed by the decode circuit per word unit is DMA-transferred to the local memory per word unit, the transfer is always performed as an even address comes first.

Accordingly, the data storage starting position shifting means is provided in the decode unit to store the liquid ejection data developed by the decode circuit from the first byte of the line buffer in a state where the 0-th byte of the line buffer is vacant, when storing the bitmap data developed by the decode circuit in the line buffer. That is, in regard to the decode unit, after the development process of the compressed liquid ejection data, when the developed liquid ejection data is stored in the line buffer, it is stored from the first byte of the line buffer in a state where the 0-th byte of the line buffer is vacant, and the developed liquid ejection data stored in the line buffer is DMA-transferred to the bitmap area in the local memory from the 0-th byte of the line buffer.

Since the developed liquid ejection data is stored from the first byte of the line buffer in a state where the 0-th byte of the line buffer is vacant, that is, from an odd byte-th in the line buffer, if DMA-transferred as it is to the bitmap area in the local memory per word unit from the 0-th byte of the line buffer, the vacant data which was stored in the 0-th byte of the line buffer is stored in the first even address area of the bitmap area. And, in the next odd address area, the head data of the developed liquid ejection data stored in the first byte of the line buffer is stored. Therefore, the data starting address of the bitmap data can be an odd address.

Owing to this, according to the data transferring apparatus for transferring liquid ejection data relating to the first aspect of the present invention, since it is possible to realize the development process of compressed data at high speed and the data transfer to the liquid ejecting head at high speed by the DMA transfer capable of transferring data at high speed without a microprocessor and the decode unit comprising the decode circuit, the action and effect that it is possible to considerably increase the liquid ejection speed of the liquid ejecting apparatus compared with that of the prior art can be obtained.

And, when the developed bitmap data is stored in the bitmap area of the local memory and transferred to the recording head, if it is necessary that the data starting address of the bitmap data be an odd address, by the data storage starting position shifting means for storing the liquid ejection data developed by the decode circuit from the first byte of the line buffer in a state where the 0-th byte of the line buffer is vacant when storing the bitmap data developed by the decode circuit in the line buffer, the action and effect that the data starting address of the bitmap data can be an odd address can be obtained.

According to the second aspect of the present invention, a data transferring apparatus for transferring liquid ejection data, comprises a decode unit comprising a decode circuit capable of performing hardware development on liquid ejection data, which is DMA-transferred per word unit from a main memory via a system bus, compressed to be capable of line development, a line buffer for storing liquid ejection data developed by the decode circuit per word unit and a DMA-transferring means for DMA-transferring liquid ejection data compressed to be capable of line development from the main memory to the decode circuit, DMA-transferring liquid ejection data developed in the line buffer to the local memory per word unit and DMA-transferring developed liquid ejection data stored in the local memory to a register of an liquid ejecting head sequentially, wherein the decode unit comprises a data storage ending position shifting means for transferring developed liquid ejection data stored in the line buffer to liquid ejecting head each time developed data of the predetermined words from which one byte has been subtracted is stored in the line buffer.

As described above, the inkjet type recording apparatus as a liquid ejecting apparatus performs recording by ejecting ink from the plural nozzle arrays provided on the head face of the recording head as a liquid ejecting head onto the recording papers to form ink dots on the surface of the recording papers, based on the bitmap data to which the compressed recording data has been developed. However, there is a case that the bytes of the data block of the bitmap area need to be odd bytes, wherein the developed bitmap data is stored in the bitmap area of the local memory and transferred to the recording head. For example, the bytes of the data block of the bitmap area to be transferred to the recording head are generally set to be 16 bytes, however, there a case that the bytes need to be 15 bytes one byte less under a specific condition, and hitherto, sine the compressed liquid ejection data is software-developed by a program per byte unit, then stored in the bitmap area of the memory one byte each by a program, there is no problem though the bytes of the data block are odd bytes. However, if the bitmap data hardware-developed by the decode circuit per word unit is DMA-transferred to the local memory per word unit, the transfer is always performed per word unit, that is, 2 bytes each. For this reason, the bytes of the data block of the bitmap area set to be 16 bytes cannot be 15 bytes, that is, the last one byte of the data block set to be 16 bytes cannot be a vacant byte.

Accordingly, by the data storage ending position shifting means is provided in the decode unit to transfer the developed liquid ejection data stored in the line buffer to the liquid ejecting head each time developed data of the predetermined words from which one byte has been subtracted is stored in the line buffer, it is possible to configure the data block of odd bytes in the bitmap area of the local memory. That is, when the developed data of predetermined words from which one byte has been subtracted is stored in the line buffer, the data of the last one word has the second half with one vacant byte.

And, since the data stored in the line buffer is DMA-transferred to the bitmap area of the local memory per word unit, the last one byte in regard to the data block of predetermined words in the bitmap area can be vacant, that is, the data block of predetermined words in the bitmap area can be the data block of predetermined words from which one byte has been subtracted. Further, the rest data of one byte developed per word unit, for example, is temporarily stored in a reserve storage area provided in the line buffer, and then stored in the 0-th byte of the line buffer. Alternatively, plural line buffers are provided, and it may be stored in the 0-th byte of a different line buffer as it is.

Owing to this, according to the data transferring apparatus for transferring liquid ejection data relating to the second aspect of the present invention, like the first aspect of the present invention described above, since it is possible to realize the development process of compressed data at high speed and the data transfer to the liquid ejecting head at high speed by the DMA transfer capable of transferring data at high speed without a microprocessor and the decode unit comprising the decode circuit, the action and effect that it is possible to considerably increase the liquid ejection speed of the liquid ejecting apparatus compared with that of the prior art can be obtained.

According to the third aspect of the present invention, in regard to the first or second aspect, the decode unit comprises a data storage ending position shifting means for transferring developed liquid ejection data stored in the line buffer to liquid ejecting head each time developed data of the predetermined words from which one byte has been subtracted is stored in the line buffer.

According to the data transferring apparatus for transferring liquid ejection data relating to the third aspect of the present invention, added to the first, aspect described above, when the developed bitmap data is stored in the bitmap area of the local memory and transferred to the recording head, if it is necessary that the data block of the bitmap area be the data block of odd bytes, by the data storage ending position shifting means for transferring the developed liquid ejection data stored in the line buffer to the liquid ejecting head each time the developed data of the predetermined words from which one byte has been subtracted is stored in the line buffer, the action and effect that it is possible to configure the data block of odd bytes in the bitmap area of the local memory can be obtained.

According to the forth aspect of the present invention, in regard to the third aspect, the data transferring apparatus comprises an invalid data mask processing means for nullifying data from head data, as many bytes as the remainder resulting from dividing a value of a data starting address of compressed liquid ejection data by the number of data bytes which the system bus can transfer per one data transfer, with respect to word data including head data of compressed data DMA-transferred from the main memory to the decode circuit.

In the DMA transfer per word unit by a 16 bit bus, an even address cannot help always coming first. Then, for example, if one word (two bytes) each is transferred per one data transfer operation as the system bus is a 16 bits, the data starting address of the compressed liquid ejection data stored in the main memory is an odd address, and thus byte data which is irrelevant to the liquid ejection data exists in the transferred data of one word (two bytes) including the head data of the compressed data. That is, the first byte of the word data (the byte data of the even address) is the byte data irrelevant to the liquid ejection data, and the second byte of the word data (the byte data of the odd address) is the head byte data of the liquid ejection data. For this reason, if the compressed liquid ejection data of which the starting address is an odd address is DMA-transferred from the main memory to the decode circuit per word unit and hardware-developed, the liquid ejection data in a state where the irrelevant data is at the head of the original liquid ejection data is transferred.

Accordingly, if the irrelevant byte data is included in the transferred data including the head data of the compressed data DMA-transferred from the main memory to the decode circuit, this irrelevant byte data is nullified and then data is hardware-developed. Specifically, the number of bytes the system bus which is the data transfer route from the main memory to the decode circuit can transferper one data transfer is first obtained. For example, in case of a 16 bits bus, 16 bits/1 byte (8 bits) = 2 bytes, in case of a 32 bits bus, 4 bytes and in case of a 64 bits bus then 8 bytes.

And, the remainder resulting from dividing the data starting address of the compressed liquid ejection data by the number of data bytes which the system bus can transfer per one data transfer is obtained. That is, if the remainder resulting from dividing the data starting address by the number of data bytes which the system bus can transfer per one data transfer does not exist, the first byte data (odd address) becomes the head byte data of the, and the irrelevant byte data is not included in regard to the transferred data of word unit including the compressed head data. On the other hand, if the remainder exists, the irrelevant byte data of as many bytes as the remainder from the head data is included in regard to the transferred data of word unit including the compressed head data.

Therefore, in regard to the word data including the compressed head data DMA-transferred from the main memory to the decode circuit having the possibility of including the irrelevant byte data, data of as many bytes as the remainder resulting from dividing the data starting address of compressed liquid ejection data DMA-transferred from the main memory to the decode circuit by the number of data bytes which the system bus can transfer per one data transfer is nullified, then hardware-developed by the decode circuit and then stored in the line buffer. Owing to this, since only the irrelevant byte data included in the word data including the compressed head data DMA-transferred from the main memory to the decode circuit is nullified, only the compressed liquid ejection data can developed by the decode circuit.

Owing to this, according to the data transferring apparatus for transferring liquid ejection data relating to the forth aspect of the present invention, added to the third aspect described above, by DMA-transferring the compressed liquid ejection data from the main memory to the decode circuit per word unit, the data transfer can be achieved at further high speed, and in case the irrelevant byte data is included in the compressed liquid ejection data DMA-transferred from the main memory to the decode circuit per word unit, the action and effect that the irrelevant byte data can be exactly nullified by the invalid data mask processing means described above, and then only the compressed liquid ejection data can be securely hardware-developed from the head data can be obtained.

According to the fifth aspect of the present invention, in regard to the third aspect, the data transferring apparatus comprises an invalid data mask processing means for nullifying head data of one byte in case data starting address of compressed data stored in the main memory is an odd address, with respect to word data including head data of compressed data DMA-transferred from the main memory to the decode circuit.

In this way, if the irrelevant byte data is included in the transferred data including the head data of the compressed data DMA-transferred from the main memory to the decode circuit, this irrelevant byte data is nullified and then data is hardware-developed. Specifically, since the compressed liquid ejection data is DMA-transferred from the main memory via the system bus one word each, if the data starting address of the compressed liquid ejection data stored in the main memory is an odd address, the first byte (byte data of an even address) of the word data is the byte data irrelevant to the liquid ejection data, and the second byte of the word data (byte data of an odd address) is the head byte data of the liquid ejection data, in regard to the transferred data of one word (2 bytes) including the head data of the compressed data.

Here, if the data starting address of the compressed liquid ejection data stored in the main memory is an odd address, the first one byte of the word data including the head data of the compressed data DMA-transferred from the main memory to the decode circuit is nullified. Owing to this, only the compressed liquid ejection data can be developed by the decode circuit while only the irrelevant byte data included in the word data including the head data of the compressed data DMA-transferred from the main memory to the decode circuit is nullified.

Therefore, according to the data transferring apparatus for transferring liquid ejection data relating to the fifth aspect of the present invention, added to the third aspect described above, by DMA-transferring the compressed liquid ejection data from the main memory to the decode circuit one word each, the data transfer can be achieved at further high speed, and in case the irrelevant byte data is included in the compressed liquid ejection data DMA-transferred from the main memory to the decode circuit one word each, the action and effect that the irrelevant byte data can be exactly nullified by the invalid data mask processing means described above, and only the compressed liquid ejection data can be securely hardware-developed from the head data can be obtained.

According to the sixth aspect of the present invention, in regard to the fifth aspect, the data transferring apparatus comprises two independent buses which are the system bus and a local bus, the main memory coupled to the system bus, capable of transferring data and the local memory coupled to the local bus, capable of transferring data, and the decode unit is coupled to the system bus and local bus in order to transfer data therebetween.

In this way, by the configuration to have two independent buses of the system bus and the local bus and the local memory which is coupled to the local bus, it is possible to secure the data transfer route of the liquid ejection data from an independent memory to the liquid ejecting head while it is separated from an access route from a microprocessor to a memory. Therefore, it is possible to perform the data transfer from the local memory to a register of the liquid ejecting head through the local bus not synchronized with the system bus. Owing to this, it isprevented that the data transfer from the memory to the liquid ejecting head gets interrupted by the access from the microprocessor to the memory so that the recording performance speed gets low because the data transfer delay of liquid ejection data occurs.

Owing to this, according to the data transferring apparatus for transferring liquid ejection data relating to the sixth aspect of the present invention, added to the fifth aspect described above, since it is possible to realize the development process of compressed data at high speed and the data transfer to the liquid ejecting head at high speed by the two independent buses of the system bus and the local bus and the DMA transfer means capable of transferring data at high speed without a microprocessor and the decode unit comprising the decode circuit, the action and effect that it is possible to considerably increase the liquid ejection speed of the liquid ejecting apparatus compared with that of the prior art can be obtained.

According to the seventh aspect of the present invention, in regard to the sixth aspect, an ASIC comprises registers of the main memory, the decode unit and the liquid ejecting head as a circuit block respectively, and registers of the decode unit and the liquid ejecting head are coupled through an dedicated bus in the ASIC.

In this way, since the main memory, which stores the compressed data, is configured to be the same block as the decode unit in the ASIC, the high speed DMA transfer can be achieved so as to transfer data particularly with one clock. Therefore, the compressed liquid ejection data can be transferred to the decode unit at higher speed. In addition, since the registers of the liquid ejecting head are also included in the same ASIC as a circuit block, and coupled to the decode unit through an dedicated bus in the ASIC, the data transfer of developed liquid ejection data from the local memory to the liquid ejecting head can be performed at higher speed.

Owing to this, according to the data transferring apparatus for transferring liquid ejection data relating to the seventh aspect of the present invention, added to the sixth aspect described above, the compressed liquid ejection data can be transferred to the decode unit at higher speed, the data transfer of developed liquid ejection data from the local memory to the liquid ejecting head can be performed at higher speed, and thus the action and effect that it is possible to further increase the liquid ejection speed of the liquid ejecting apparatus can be obtained.

According to the eighth aspect of the present invention, in regard to the seventh aspect, the line buffer comprises two faces of buffer areas capable of storing developed data of predetermined words, liquid ejection data developed by the decode circuit is sequentially stored in a first face of the buffer areas while liquid ejection data developed by the decode circuit is sequentially stored in a second face of the buffer areas when developed data of predetermined words has been accumulated, and developed data is DMA-transferred to the local memory per predetermined words when developed data of predetermined words has been accumulated.

In this way, the line buffer has two faces of buffer areas which are capable of storing the developed data of predetermined bytes, and stores the data which has been developed by the decode circuit in a first face of the buffer areas, and when predetermined bytes have been accumulated, the developed data of the first face is transferred per word unit by the DMA transferring means, while the data developed by the decoded circuit can be stored in a second face, so that it is possible to perform development process of compressed recording data and data transfer process in parallel.

Owing to this, according to the data transferring apparatus for transferring liquid ejection data relating to the forty-fifth aspect of the present invention, added to the seventh aspect described above, the development process of compressed recording data and the data transfer process can be perform in parallel, and thus the action and effect that it is possible to further increase the liquid ejection speed of the liquid ejecting apparatus can be obtained.

According to the ninth aspect of the present invention, in regard to the eighth aspect, data transfers with respect to the local bus from the decode circuit to the local memory and from the local memory to a register of the liquid ejecting head are performed in a burst transfer.

The burst transfer is such data transfer method which is a well-known method for speeding up the data transfer as when the continuous data is transferred, the data is transferred while a bus is occupied until all data of a predetermined data block is completely transferred by omitting a part of a sequence such as an address designation so as to increase the data transfer speed. And, since the data transfer to the liquid ejecting head performed via the system bus in the conventional method is per formed via the local bus separated from the system bus, the data transfers from the decode unit to the local memory via the local bus and from the local memory to the register of the liquid ejecting head can be performed in the burst transfer.

That is, in regard to the conventional data transferring apparatus performing the data transfer from the main memory to the liquid ejecting head via the systembus, if the transfer is performed while the bus is occupied until all data of predetermined data blocks is completely transferred to the liquid ejecting head, such problem occurs as the data transfer requested by a microprocessor cannot performed, however, in regard to the local bus independent of the system bus, this problem does not occur, and thus the data transfer to the liquid ejecting head via the local bus can be performed in the burst transfer.

Owing to this, according to the data transferring apparatus for transferring liquid ejection data relating to the ninth aspect of the present invention, added to the eighth aspect described above, the data transfer to the liquid ejecting head via the local bus can be performed in the burst transfer, and thus the action and effect that it is possible to further increase the liquid ejection speed of the liquid ejecting apparatus can be obtained.

In addition, since the system bus and the local are independent each other, and the data transfer to the register of the liquid ejecting head not synchronized with the system bus can be performed by the decode circuit of the decode unit and the line buffer, the action and effect that it is possible to maximize the effect of increasing the liquid ejection speed of the liquid ejecting apparatus can be obtained.

According to the tenth aspect of the present invention, in regard to the ninth aspect, the compressed liquid ejection data is run length compressed data, and the decode circuit can perform hardware development on run length compressed data.

According to the data transferring apparatus for transferring liquid ejection data relating to the tenth aspect of the present invention, by the decode circuit whereby the run length compressed data capable of line development can be hardware-developed, the action and effect in the ninth aspect described above can be achieved.

According to the eleventh aspect of the present invention, in regard to the tenth aspect, the decode unit comprises a non-development processing means for storing uncompressed liquid ejection data DMA-transferred from the main memory in the line buffer without hardware development by the decode circuit.

According to the data transferring apparatus for transferring liquid ejection data relating to the eleventh aspect of the present invention, added to the tenth aspect described above, if the liquid ejection data stored in the main memory is uncompressed data, a means stores it the line buffer as it is without hardware development by the decode circuit, and thus the action and effect that it is possible to further increase the liquid ejection speed of the liquid ejecting apparatus in regard to the uncompressed liquid ejection data can be obtained.

According to the twelfth aspect of the present invention, a liquid ejecting apparatus comprises a data transferring apparatus according to any of the preceding aspects.

According to the liquid ejecting apparatus relating to the forty-ninth aspect of the present invention, the action and effect in the aspects described above can be achieved in regard to the liquid ejecting apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the presently preferred exemplary embodiments of the invention taken in conjunction with the accompanying drawings, in which:

Fig. 1 is a plan view of an inkjet type recording apparatus relating to the present invention.

Fig. 2 is a side view of an inkjet type recording apparatus relating to the present invention.

Fig. 3 is a flowchart of the inkjet type recording apparatus relating to the present invention.

Fig. 4 is a block diagram showing the configuration of a data transferring apparatus relating to the present invention.

Fig. 5 is a timing chart showing the flow of recording data.

Fig. 6 is a block diagram showing the configuration of the DECU relating to the present invention.

Fig. 7 is a diagram showing such flow as compressed recording data is developed.

Fig. 8 is a diagram showing such flow as compressed recording data is developed.

Figs. 9A to 9D are diagrams showing the recording data after development.

Figs. 10A to 100 are diagrams showing the recording data after development.

Fig. 11 is a diagram showing such flow as compressed recording data is developed.

Fig. 12 is a diagram showing such flow as compressed recording data is developed.

Fig. 13 is a diagram showing such flow as compressed recording data is developed.

Fig. 14 is a diagram showing such flow as compressed recording data is developed.

Figs. 15A to 15D are diagrams showing the recording data after development.

Figs. 16A to 16D are diagrams showing the recording data after development.

Fig. 17 is a diagram showing such flow as compressed recording data is developed.

Fig. 18 is a diagram showing such flow as compressed recording data is developed.

Fig. 19 is a diagram showing such flow as compressed recording data is developed.

Fig. 20 is a diagram showing such flow as compressed recording data is developed.

Figs. 21A to 21D are diagrams showing the recording data after development.

Fig. 22 is a diagram showing such flow as compressed recording data is developed.

Fig. 23 is a diagram showing such flow as compressed recording data is developed.

Figs. 24A to 24D are diagrams showing the recording data after development.

Fig. 25 is a diagram showing such flow as compressed recording data is developed.

Fig. 26 is a diagram showing such flow as compressed recording data is developed.

Fig. 27 is a diagram showing such flow as compressed recording data is developed.

Fig. 28 is a diagram showing such flow as compressed recording data is developed.

Figs. 29A to 29D are diagrams showing the recording data after development.

Figs. 30A to 30D are diagrams showing the recording data after development.

Figs. 31A to 31D are diagrams showing the recording data after development.

Figs. 32A to 32D are diagrams showing the recording data after development.

Figs. 33A to 33D are diagrams showing the recording data after development.

Figs. 34A to 34D are diagrams showing the recording data after development.

Fig. 35 is a diagram showing the state in which uncompressed data is transferred.

Fig. 36 is a block diagram showing a data transferring apparatus in regard to the prior art.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, the preferred embodiments of the present invention will now be described based on drawings.

To begin with, a first embodiment of the inkjet type recording apparatus will be described as "liquid ejecting apparatus" relating to the present invention. Fig. 1 is a schematic plan view of an inkjet type recording apparatus relating to the present invention, and Fig. 2 is a side view of the apparatus shown in Fig. 1.

In the inkjet type recording apparatus 50, a carriage 61 is provided tomove along amain scanning direction X as a recording means which performs recording on recording papers P, rotatably supported by carriage guide shaft 51. On the carriage 61, a recording head 62 is mounted as a "liquid ejecting head" which performs recording by ejecting ink onto the recording papers P. Opposite to the recording head 62, a platen 52 is provided to control a gap between the head surface of the recording head 62 and the recording papers P. And, recording on the recording papers P is performed by repeating an operation of carrying the recording papers P between the carriage 61 and the platen 52 in a sub scanning direction Y a predetermined amount each and an operation of ejecting ink onto the recording papers P from the recording head 62 while the recording head 62 moves back and forth once in the main scanning direction X.

A paper feeding tray 57 is configured to be capable of feeding the recording papers P such as normal papers or foot papers, and an ASF (Auto Sheet Feeder) is provided in it as a paper feeding means to automatically feed the recording papers P. The ASF is an automatic paper feeding mechanism which has two paper feeding rollers 57b provided in the paper feeding tray 57 and a separating pad not shown in drawings. One of these two paper feeding rollers 57b is arranged at the one side of the paper feeding tray 57 while the other one of the paper feeding rollers 57b is installed at a recording paper guide 57a, and the recording paper guide 57a is provided at the paper feeding tray 57 to be capable of sliding in the longitudinal direction corresponding to the width of the recording papers P. And, by the rotation drive force of the paper feeding roller 57b and the frictional resistance of the separating pad, the plural recording papers P stacked in the paper feeding tray 57 are automatically and accurately fed not all but a piece each during feeding.

As a recording paper carrying means for carrying the recording papers P in the sub scanning direction Y, a driving transfer roller 53 and driven transfer rollers 54 are provided. The driving transfer roller 53 is rotatably controlled by the rotation drive force such as a stepping motor, and by the rotation of the driving transfer roller 53 the recording papers P are carried in the sub scanning direction Y. The driven transfer rollers 54 are provided as plural pieces, and each of them is urged by the driving transfer roller 53 to rotate in contact with the recording papers P as following the carriage of the recording papers P when the recording papers P are carried by the rotation of the driving transfer roller 53. On the surface of the driving transfer roller 53, a film which has high frictional resistance is provided. By the driven transfer rollers 54, the recording papers P pressed onto the surface of the driving transfer roller 53 are firmly in contact with the surface of the driving transfer roller 53 so that they are carried in the sub scanning direction Y by the rotation of the driving transfer roller 53.

And, a paper detector 63 is provided between the paper feeding roller 57b and the driving transfer roller 53 in the well-known art. The paper detector 63 has a lever to which a self-resetting characteristic into an upright position is granted pivotally supported to be rotatable only in the recording paper carriage direction as projecting toward the carriage route of the recording papers P, and is configured as the end of the lever is pushed toward the recording papers P and thus the lever is rotated so that the recording papers P are detected. The paper detector 63 detects the starting end position and the terminal end position of the recording papers P fed by the paper feeding roller 57b, and determines a recording area corresponding to the detected positions to perform recording.

Meanwhile, a driving paper discharge roller 55 and driven paper discharge rollers 56 are provided as a means for discharging the recording papers P which have been recorded. The driving paper discharge roller 55 is rotatably controlled by the rotation drive force such as a stepping motor, and by the rotation of the driving paper discharge roller 55 the recording papers P are carried in the sub scanning direction Y. The driven paper discharge rollers 56 have plural teeth on their circumference, and become a toothed roller in which the end of each tooth is sharp in an acute angle to be in contact with the recording surface of a recording paper P at point. Each of the plural driven paper discharge rollers 56 is urged by the driving paper discharge roller 55 to rotate in contact with the recording papers P as following the discharge of the recording papers P when the recording papers P are carried by the rotation of the driving paper discharge roller 55.

And, the rotation driving motor not shown in drawings which rotatably drives the paper feeding roller 57b or the driving transfer roller 53 and the driving paper discharge roller 55 and the carriage driving motor not shown in drawings which drives the carriage 61 in the main scanning direction are controlled by the recording controlling unit 100. In addition, the recording head is also controlled by the recording controlling unit 100 to eject ink onto the surface of the recording papers P.

Fig. 3 is a schematic flowchart of the inkjet type recording apparatus 50 relating to the present invention.

The inkjet type recording apparatus 50 has a recording controlling unit 100 for controlling carious recording processes. The recording controlling unit 100 has two independent buses, namely, a system bus SB and a local bus LB. To the system bus SB a MPU (microprocessor) 24, a ROM 21, a RAM 22, a nonvolatile storage medium 23, I/O 25 and a decode circuit 28 are coupled so as to be capable of transferring data. In the MPU 24 various calculation processes are performed. In the ROM 21, software/ program and data needed for calculation processes of the MPU 24 are stored beforehand. The RAM 22 is used as a temporarily storing area for the software/program or a working area for the MPU 24. And, in the nonvolatile storage medium 23 such as a flash memory some data resulting from the calculation processes of the MPU 24 is stored, and it is designed to hold the data even if the power of the inkjet type recording apparatus 50 is turned off.

Further, the recording controlling unit 100 is configured to be coupled to an information processing apparatus 200 such as a personal computer via an interface unit 27 which has an interface function with external apparatuses, and to be capable of processing input and output of various kinds of information or data via the system bus SB with the information processing apparatus 200. And; I/O 25 performs output control to a various motors controlling unit 31 via an input and/or output unit 26 based on the calculation process result of the MPU 24, and allows input information to be inputted from various sensors 32. The various motors controlling unit 31 is a drive control circuit which controls various motors of the inkjet type recording apparatus 50, and is controlled by the recording controlling unit 100. And, the various sensors 32 detect various kinds of condition information of the inkjet type recording apparatus 50 and output them to the I/O 25 via the input and/or output unit 26.

During performing recording, the information processing apparatus 200 plays a host part to output recording data (liquid ejection data) compressed by the information processing apparatus 200, and the inkjet type recording apparatus 50 receives the compressed recording data from the interface unit 27 via the system bus SB. The decode circuit 28 develops the compressed recording data and then stores the developed recording data in a local memory 29 via the local bus LB. The developed recording data stored in the local memory 29 is transferred again from a register in a head controlling unit 33 to the recording head 62 via the local bus LB. The head controlling unit 33 controls the recording head 62 to eject ink of various colors onto he recording papers P from the plural nozzle arrays provided on the head side of the recording head 62.

In this way, by two independent buses, namely, the systembus S3 and the local bus LB and the decode circuit 28 developing the compressed data, it is possible to realize the development process of the compressed data at high speed and the data transfer to the recording head 62 at high speed so that it is possible to increase the liquid ejection speed of the inkjet type recording apparatus 50 considerably compared with that of the prior art. In the end, by not developing the compressed data by a program of single thread which performs various data processes in consecutive order besides the development process of the compressed data in regard to the MPU 24 in the conventional way but independently performing only the development of the compressed data by the decode circuit 28 which is exclusively used for developing compressed data, it is possible to perform the development process of the compressed recording data at high speed.

In addition, by the configuration to have two independent buses of the system bus SB and the local bus LB and the local memory 29 which is coupled to the local bus LB, it is possible to secure the data transfer route of recording data (local bus LB) to the recording head 62 which is separated from the system bus SB which is coupled to the MPU 24. Therefore, it is possible to perform the data transfer from the local memory 29 to the register of the recording head 62 through the local bus LB not synchronized with the system bus SB. Owing to this, it is prevented that the data transfer to the recording head 62 gets interrupted by the access from the MPU 24 to the RAM 22 so that the recording performance speed gets low because the data transfer delay of recording data occurs.

Further, in the present embodiment, a line buffer 281 is provided to store data after development per word unit between the decode circuit 28 and the local bus LB. The recording data developed in the decode circuit 28 is temporarily stored once in line buffer 281. The developed recording data stored in the line buffer 281 is transferred to the local memory 29 via the local bus LB two words each. In this way, the line buffer 281 may provided to store data after development per word unit between the decode circuit 28 and the local bus LB. By providing the line buffer 281 to store data after development per word unit, developing the compressed data, which used to be developed by the conventional program per one byte, per word unit (2 bytes), storing the data in the line buffer 281 and transferring the data to the local memory 29 per word unit, the amount of compressed data which is developed and transferred at a time gets twice that of the conventional way, and thus it is possible to perform the development process of compressed data at higher speed, which is desirable.

Fig. 4 is a block diagram showing the configuration of a data transferring apparatus 10 as a "data transferring apparatus for transferring liquid ejection data" relating to the present invention. Fig. 5 is a timing chart schematically showing the flow of recording data in a data transferring apparatus 10.

The recording controlling unit 100 has an ASIC (Application Specific Integrated Circuit) 4, and the ASIC 4 includes the interface unit 27 described above, the head controlling unit 33 described above, a receiving buffer unit 42 and a DECU 41 as a "decode unit" relating to the present invention. The DECU 41 includes the decode circuit 28 described above, the line buffer 281 and a "DMA transferring means" (It will be described in detail.) . And, the system bus SB and the local bus LB are 16 bits buses, and thus it is possible to transfer data of 1 word (2 bytes) per a predetermined data transfer period. Hereinafter, with reference to the timing chart shown in Fig. 5, the flow of recording data in regard to the data transferring apparatus 10 will be described.

The compressed recording data is DMA-transferred from the information processing apparatus 200 to the receiving buffer unit 42 as a "main memory" via the interface unit 27 through the system bus SB one word each (symbol T1). As described above, the DMA transfer is such transfer method as once addresses of a transfer source and a transfer destination or the number of transfer are set in a register then the data transfer can be performed at high speed by hardware without the MPU 24. Next, data is DMA-transferred from the receiving buffer unit 42 to the DECU 41 via the system bus SB (symbol T2). Continuously, in the DECU 41, the compressed data of 1 word is hardware-developed by the decode circuit 28, and the developed recording data is stored in the line buffer 281 (symbol T3).

The recording data developed and stored in the line buffer 281 is DMA-transferred to a bitmap area in the local memory 29 via the local bus LB with non-synchronization to the data transfer through the system SB when the recording data stored in the line buffer 281 has reached a predetermined amount (symbol T4). Continuously, the recording data as bitmap data stored in the bitmap area of the local memory 29 is DMA-transferred again to the DECU 41 via the local bus LB (symbol T5), then DMA-transferred from the DECU 41 to the head controlling unit 33 via an internal bus IB (symbol T6), then stored in a register in the head controlling unit 33 and then DMA-transferred to the recording head 62 (symbol T7) .

In this way, the data transfer from the receiving buffer unit 42 (the main memory) to the decode circuit 28, the data transfer from the decode circuit 28 to the local memory 29 and the data transfer from the local memory 29 to the recording head 62 may be performed by the DMA transfer, and thus data transfer at higher speed can be achieved, which is more preferable. In addition, since the "main memory" which stores the compressed data is configured to be the same block as the DECU 41 in the ASIC 41 as the receiving buffer unit 42, high DMA transfer can be achieved so as to transfer data particularly with one clock. Moreover, a part of the RAM 22 may be used for the "main memory" without providing the receiving buffer unit 42 to the ASIC 41.

Fig. 6 is a block diagram showing the configuration of the DECU 41 as the "decode unit" relating to the present invention.

An S-DMA controller 411 as the "DMA transferring means" described above is a controller for DMA transfer through the system bus SB. By the S-DMA controller 411, the compressed recording data stored in the receiving buffer unit 42 is DMA-transferred to the development processing controller 412 one word each. The development processing controller 412 includes the decode circuit 28 and the line buffer 281 described above. The compressed recording data DMA-transferred one word each by the S-DMA controller 411 from the receiving buffer unit 42 is hardware-developed by the decode circuit 28 one word each, and the developed recording data is accumulated in the line buffer 281.

In the same way, an L-DMA controller 413 as the "DMA transferring means" is a controller for DMA transfer through the local bus LB. In addition, a local memory controller 414 retrieves data from the local memory 29 coupled to the local bus LB and controls writing in it. And, when developed recording data of predetermined bytes has been accumulated in the line buffer 281, it is DMA-transferred to the local memory 29 through the local bus LB via the local memory controller 414 by the L-DMA controller 413 as not synchronized with the DMA transfer through the system bus SB. The recording data developed and DMA-transferred to the local memory 29 is stored in the predetermined bitmap area of the local memory 29.

In the same way, an I-DMA controller 415 controls the DMA transfer through the internal bus IB which is an dedicated bus between the DECU 41 in the ASIC and the head controlling unit 33. The developed recording data stored in the bitmap area of the local memory 29 is DMA-transferred to the head controlling unit 33 through the local bus LB and the internal bus IB via the local memory controller 414 by the I-DMA controller 415, then stored in a register in the head controlling unit 33 and then DMA-transferred to the recording head 62.

In addition, the DMA transfer from the line buffer 281 to the local memory 29 is transfer in burst by the L-DMA controller 413, and the DMA transfer from the local memory 29 to the recording head 62 is transfer in burst by the I-DMA controller 415, As described above, the burst transfer is such data transfer method as, when the continuous data is transferred, the data is transferred occupying a bus until all data of a predetermined data block is completely transferred by omitting a part of a sequence such as an address designation. The L-DMA controller 413 transfers in burst the developed recording data of predetermined bytes accumulated in the line buffer 281 one word each, occupying the local bus LB until the DMA-transfer to the local memory 29 is completed. The I-DMA controller 415 transfers in burst the developed recording data stored in the bitmap area of the local memory 29 one word per a data block of predetermined bytes, occupying the local bus LB until all of one data block has been completely DMA-transferred to the recording head 62.

And, in case the burst transfer from the line buffer 281 to the local memory 29 and the burst transfer from the local memory 29 to the recording head 62 compete each other, the burst transfer from the local memory 29 to the recording head 62 has priority, and thus during the burst transfer from the local memory 29 to the recording head 62 the burst transfer from the line buffer 281 to the local memory 29 is temporarily stopped, so that the ink ejecting operation from the nozzle arrays of the recording head 62 based on the recording data from the local memory 29 to the recording head 62 is not interrupted.

In addition, the DEDU 41 has a non-development processing means 491, an invalid data mask processing means 492, a data rearranging means 493, a data dividing means 494, a data storage starting position shifting means 495 and a data storage ending position shifting means 496, which are will be described below.

In this way, by transferring data while occupying the local bus LB until all data of a predetermined data block is completely sent in regard to the recording head 62, such problem as data transfer by the request of the MPU 24 through the system bus 5B cannot be performed does not occur, and thus it is possible to perform data transfer of recording data to the recording head 62 at high speed.

Fig. 7 and Fig. 8 are diagrams schematically showing the state until compressed recording data is hardware-developed in the decoded circuit 28 and stored in the line buffer 281 in the DECU 41. In addition, Fig. 9 is a diagram schematically showing the state until the developed recording data is transferred and stored from the line buffer 281 to the local memory 29.

In this embodiment, the compressed recording data has been compressed by a run length compression method. The run length compression method is a well-known data compression method and it will be briefly described below. The run length compressed data is compressed data of byte boundary, and has a set of count (1 byte) and data (byte or bytes) . In other words, the run length compressed data is configured to first have the count and then necessarily have the data. If the value of the count is more than 128 (a negative constant), that is, more than 80H, that means repeatedly developing the next data of 1 byte, and thus the data of 1 byte following the count is repeatedly developed as many times as 257 from which the value of the count subtracted. On the other hand, if the value of the count is less than 127, that is, less than 7FH, that means continuing data to be developed as it is without repeating after the count, and thus the data following the count is developed as it is without repetition as many times as the value of the count to which one is added.

Next, the configuration of the line buffer 281 will be described. The line buffer 281 has two faces of data storing areas of 9 words that combine storing areas of 8 words (16 bytes) and preliminary storing areas of 1 word (2 bytes), and each of faces is A face and B face respectively. The recording data developed by the decode circuit 28 one word each is stored in one of the A face and the B face of the line buffer 281 one word each in turn, and the data is turned to be stored into the other face after the developed data has been accumulated to be a predetermined amount, in the present embodiment, 16 bytes. In addition, the accumulated and developed data of 16 bytes, as described above, is stored in a predetermined bitmap area of the local memory 29.

In this way, the line buffer 281 has two faces of buffer areas which are capable of storing the recording data after development of 16 bytes, and stores the recording data which has been developed by the decode circuit 28 in a first face of the buffer areas. And, after 16 bytes have been accumulated, while the developed recording data of the first face is transferred per word unit by a DMA transferring means, the recording data developed by the decoded circuit 28 can be stored in a second face of the buffer areas, so that it is possible to perform development process of compressed recording data and data transfer process in parallel.

Continuously, run length compressed data taken for example, the flow of recording data will be described, wherein the compressed data is developed by the decode circuit 28, stored in the line buffer 281 and stored from the line buffer 281 to the local memory 29.

In the receiving buffer unit (main memory) 42, the run length compressed recording data of 24 words (48 bytes) which begins from FEH is stored. The run length compressed recording data is DMA-transferred to the decode circuit 28 via the system bus SB one word each, namely, two bytes each, hardware-developed and stored in the line buffer 281. In the present embodiment, the data starting address of the run length compressed data is an even address, and the data starting address of the bitmap data (image data) in the local memory 29 is an even address. And, the number of bytes of the data block DMA-transferred from the line buffer 281 to the local memory 29 (the number of bytes of 1 line) is 16 bytes.

Further, in the main memory, the line buffer 281 in the DECU 41 shown in Fig. 7 and the local memory 29 shown in Fig. 9, the left top is an even address, and addresses gets to be upper addresses in order from the left to the right, which will be the same with that of drawings below,

Hereinafter, one word each will be described in order. First, the compressed recording data of initial 1 word (FEH, 01H) DMA-transferred from the receiving buffer unit 42 to the decode circuit 28 in the DECU 41 (Transfer S1). The FEH is the count, and the 01H is the data. Since the value of the count of FEH is 254, that is, larger than 128 and 257-254=3 times, the data of 01H is repeatedly developed and 1 byte each is stored in order in the A face of the line buffer 281. Next, the run length compressed data DMA-transferred to the decode circuit 28 is 03H and 02H (Transfer S2). The 03H is the count, and the 02H is the data. Since the value of the count of 03H is 3, that is, smaller than 127 and 3+1=4 bytes, the data following the count gets developed without repletion. That is, the data of 02H, 78H, 55H and 44H following the count 03H is developed as it is without repetition, and stored in order in the A face of the line buffer 281 (Transfers S2 to S4). The FBH, which is the upper part (odd address part) of the DMA-transferred word data in the Transfer S4, is the count, and the next data of 1 byte is repeatedly developed 6 times (257-251=6).

Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is FFH and FEH (Transfer S5). The lower address (even address) of FFH is the data, besides the data of the previous count of FBH. Therefore, FFH is repeatedly developed 6 times, and stored in order in the A face of the line buffer 281. And, the upper address (odd address) of FEH is the count, and the next data of 1 byte is repeatedly developed 3 times (257-254=3). Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is 11H and 06H (Transfer S6). The lower address (even address) of 11H is the data, besides the data of the previous count of FEH. Therefore, 11H is repeatedly developed 3 times, and stored in the A face of the line buffer 281. And, the upper address (odd address) of 06H is the count, and the next data (66H, 12H, 77H, 45H, 89H, 10H and 55H) of 7 bytes (6+1=7) is developed as it is without repetition, and stored in order in the B face of the line buffer 281 (Transfers S7 to S10).

In the mean time, when the developed recording data has been accumulated to be the number of bytes of 1 line in the A face of the line buffer 281, namely, 16 bytes (at the Transfer S6), the 16 bytes are DMA-transferred to the local memory 29 one word each as a data block of the 1 line. At that time, the L-DMA controller 413 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data after 1 line development is completely DMA-transferred to the local memory 29 (Transfer D1). The recording data of 1 line transferred to the local memory 29 is stored 1 word each in order in the predetermined bitmap area of the local memory 29 at the first of the even address from the lower address (Fig. 9A).

Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is 10H and FAH (Transfer S11). The lower address (even address) of 10H is the data, besides the data of the previous count of FBH. Therefore, 10H is repeatedly developed 6 times, and stored in order in the B face of the line buffer 281. And, the upper address (odd address) of FAH is the count, and the next data of 1 byte is repeatedly developed 7 times (257-250=7). Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is 20H and 08H (Transfer S12) . The lower address (even address) of 20H is the data, besides the data of the previous count of FAH. Therefore, 20H is repeatedly developed 7 times, and stored in the B face of the line buffer 281, and when the accumulated data in the B face has reached 16 bytes the remaining data gets stored in order in the A face. And, the upper address (odd address) of 06H is the count, and the next data (12H, 13H, 14H, 15H, 16H, 17H, 18H, 19H and 20H) of 9 bytes (8+1=9) is developed as it is without repetition, and stored in order in the A face of the line buffer 281 (Transfers S13 to S17 in Fig. 8).

In the mean time, when the developed recording data has been accumulated to be the number of bytes of 1 line in the B face of the line buffer 281, namely, 16 bytes (at the Transfer S12), the 16 bytes are DMA-transferred to the local memory 29 one word each as a data block of the 1 line. At that time, the L-DMA controller 413 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data after 1 line development is completely DMA-transferred to the local memory 29 (Transfer D2) . The recording data of 1 line transferred to the local memory 29 is stored 1 word each in order in the predetermined bitmap area of the local memory 29 at the first of the even address from the lower address (Fig. 9B).

Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is 11H and 02H (Transfer S18) . The lower address (even address) of 11H is the data, besides the data of the previous count of FDH . Therefore, 11H is repeatedly developed 3 times (257-254=3), and stored in the A face of the line buffer 281, and when the accumulated data in the A face has reached 16 bytes the remaining data gets stored in order in the B face. And, the upper address (odd address) of 02H is the count, and the next data (98H, B0H and F2H) of 3 bytes (2+1=3) is developed as it is without repetition, and stored in order in the B face of the line buffer 281 (Transfers S19 to S20).

In the mean time, when the developed recording data has been accumulated to be the number of bytes of 1 line in the A face of the line buffer 281, namely, 16 bytes (at the Transfer S18) , the 16 bytes are DMA-transferred to the local memory 29 one word each as a data block of the 1 line. At that time, the L-DMA controller 413 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data after 1 line development is completely DMA-transferred to the local memory 29 (Transfer D3). The recording data of 1 line transferred to the local memory 29 is stored 1 word each in order in the predetermined bitmap area of the local memory 29 at the first of the even address from the lower address (Fig. 9C).

Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is ABH and 03H (Transfer S21) . The lower address (even address) of ABH is the data, besides the data of the previous count of FCH (the upper address of the Transfer S20). Therefore, ABH is repeatedly developed 5 times (257-252=5), and stored in order in the B face of the line buffer 281. And, the upper address (odd address) of 03H is the count, and the next data (FFH, FEH, FCH and FDH) of 4 bytes (3+1=4) is developed as it is without repetition, and stored in order in the B face of the line buffer 281 (Transfers 522 to S23).

Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is FEH and FFH (Transfer 524). The lower address (even address) of FEH is the data, besides the data of the count of FEH. Therefore, FFH is repeatedly developed 3 times (257-254=3), and stored in order in the B face of the line buffer 281. When the developed recording data has been accumulated to be the number of bytes of 1 line in the B face of the line buffer 281, namely, 16 bytes (at the Transfer S24), the 16 bytes are DMA-transferred to the local memory 29 one word each as a data block of the 1 line. At that time, the L-DMA controller 413 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data after 1 line development is completely DMA-transferred to the local memory 29 (Transfer D4).

The recording data of 1 line transferred to the local memory 29 is stored 1 word each in order in the predetermined bitmap area of the local memory 29 at the first of the even address from the lower address (Fig. 9D). And, when the recording data of the bitmap data for ejecting ink with one main scanning pass has been stored in the local memory 29, data is DMA-transferred from the local memory 29 to the recording head 62. At this time, the I-DMA controller 415 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data of the bitmap data for ejecting ink with one main scanning pass is completely DMA-transferred to the head controlling unit 33.

In this way, it is possible to perform the development process of the compressed recording data at high speed by hardware-developing the compressed recording data, which used to be software-developed by the conventional program, in the decode circuit 28. In addition, since the compressed recording data, which used to be developed one byte each by the conventional program, is developed per word unit (two bytes), it is possible to perform the development process of the compressed recording data at high speed. And, by the configuration to have two independent buses, namely, the system bus SB and the local bus LB and the local memory 29 which is coupled to the local bus LB, it is possible to perform the data transfer to the from the local memory 29 to the recording head 62 through the local bus LB not synchronized with the system bus SB. Owing to this, it is prevented that the data transfer to the recording head 62 gets interrupted by the access from the MPU 24 to the RAM 22 so that the recording performance speed gets low because the data transfer delay of recording data occurs. Further, higher data transfer can be achieved by the DMA transfer.

Accordingly, since it is possible to realize the development process of the compressed data at high speed and the data transfer to the recording head 62 at high speed, it is possible to increase the liquid ejection speed of the inkjet type recording apparatus 50 considerably compared with that of the prior art. By the way, the data transfer speed to the recording head 62, which was 1 Mbytes/sec in the prior art, can be high up to 8 to 10 Mbytes/sec by the data transferring apparatus 10 relating to the present invention. Further, if the data processing capacity of the recording head 62 is low, no matter how fast the data transfer is performed, only the recording performance speed corresponding to the data processing capacity of the recording head 62 is obtained, and thus it is surely necessary to provide a recording head 62 which has enough process speed.

Next, as a second embodiment of the inkjet type recording apparatus 50 relating to the present invention, added to the first embodiment described above, when the developed recording data DMA-transferred from the DECU 41 to the local memory 29 is stored in the predetermined bitmap area, the data of 1 line is not stored in order from the lower address of the bitmap area (stored in a horizontal direction) but is changed and stored in a vertical direction to be well-arranged for the recording head 62 by the data rearranging means 493 (Fig. 6) described above.

Figs. 10A, 10B, 10C and 10D are diagrams which schematically show the states until the developed recording data is transferred and stored from the line buffer 281 to the local memory 29, and show the states in which the data of 1 line is changed and stored in a vertical direction.

In the bitmap area of the local memory 29 which is the DMA transfer destination, the transfer destination address is individually set for each word of the developed recording data stored in the line buffer 281 by the data rearranging means 493 (Fig. 6) in the DECU 41 in order that the data of 1 line is stored to be arranged in a vertical direction. And, the L-DMA controller 413 (Fig. 6) in the DECU 41 sets this individual transfer destination address as the transfer destination address of the DMA transfer, and DMA-transfers the developed recording data stored in the line buffer 281 to the local memory 29 one word each.

In this way, when the recording data of 1 word (16 bytes) is DMA-transferred from the line buffer 281 to the local memory 29, it is possible to perform rearrangement of the necessary recording data instantly by performing rearrangement of the recording data developed in the DECU 41, comparing it with performing rearrangement of data in a memory 1 byte each in order by the conventional program, and thus it is possible to perform rearrangement of recording data at high speed.

Further, as a third embodiment of the inkjet type recording apparatus 50 relating to the present invention, in regard to the first or second embodiment described above, in case the data starting address of the run length compressed recording data stored in the receiving buffer unit 42 is an odd address, the invalid data mask processing means 492 described above nullifies the head data of 1 byte of word data including the head data of the run length compressed data DMA-transferred from the receiving buffer unit 42 to the decode circuit 28.

Fig. 11 and Fig. 12 are diagrams schematically showing the state until the compressed recording data is hardware-developed in the decode circuit 28 and stored in the line buffer 281, in case the data starting address of the compressed recording data is an odd address.

The head byte data (FEH) of the run length compressed recording data stored in the receiving buffer unit 42 (main memory) is stored in the upper address (odd address) of the head word data. That is, in the lower address (even address) of the word data including this head byte data, the data irrelevant to the recording data (AAH) is stored. However, if one word each is DMA-transferred from the receiving buffer unit 42 to the decode circuit 28, the even address cannot help but be initially transferred. Therefore, if the head word data of the run length compressed recording data is hardware-developed as it is by the decode circuit 28, the development is performed in the state where the data irrelevant to the recording data is included, and thus it is impossible to surely develop the compressed recording data.

Here, before the decode circuit 28 develops data in the development processing controller 412 (Fig. 6), the invalid data nullifying means 492 nullifies the irrelevant byte data at the lower address (even address) of the word data including the head byte data of the compressed recording data by masking . Further, when head data of 1 word is developed by the decode circuit as it is, AAH becomes the count, and FEH becomes the data, so that FEH can be correctly developed as the count by nullifying AAH which is the irrelevant data.

Next, the compressed recording data DMA-transferred to the decode circuit 28 is 01H and 03H (Transfer S31) . The lower address (even address) of 01H is the data, besides the data of the previous count of FEH. Therefore, 01H is repeatedly developed 3 times (257-254 = 3), and stored in order in the A face of the line buffer 281. And, the upper address (odd address) of 03H is the count, and the next data (02H, 78H, 55H and 44H) of 4 bytes (3+1=4) is developed as it is without repetition, and stored in order in the A face of the line buffer 281 (Transfers S32 to S33). Then, in the same order as that of the first embodiment, the run length compressed recording data is developed one word each and stored in order in the line buffer 281 (Transfers S32 to S54), and when the developed recording data has been accumulated to be 1 line bytes (16 bytes) the data is DMA-transferred to the local memory 29 (Transfers D1 to D4). Further, itispreferabletojudgeswhether the data starting address of the run length compressed recording data stored in the receiving buffer unit 42 is an odd address or not by, for example, a firmware program which is performed by the MPU 24.

In this way, although the data starting address of the run length compressed recording data stored in the receiving buffer unit 42 is an odd address, it is possible to accurately perform hardware development on data from the first of the run length compressed recording data in the decode circuit 28.

Further, as a fourth embodiment of the inkjet type recording apparatus 50 relating to the present invention, in regard to the first to third embodiments described above, the number of bites of 1 line is an odd number.

Fig. 13 and Fig. 14 are diagrams schematically showing the state until the compressed recording data is hardware-developed in the decode circuit 28 and stored in the line buffer 281, in case the quantity of 1 line is 15 bytes in regard to the first or second embodiment described above. In addition, Figs. 15A to 15D are diagrams schematically showing the state until the developed recording data is transferred and stored from the line buffer 281 to local memory 29 to be vertically rearranged in line in regard to the fourth embodiment, and Figs. 16A to 16D are diagrams schematically showing the state until the developed recording data is stored without being vertically rearranged in line.

As described above, since the developed recording data is DMA-transferred one word each from the line buffer 281 to the local memory 29, the storage of the developed recording data in the bitmap area of the local memory 29 is performed 1 word each, and thus the recording data of odd bytes cannot be DMA-transferred from the DECU 41 to the local memory 29. Here, the data storage ending position shifting means 496 (Fig. 6), in regard to the development processing controller 412 (Fig. 6), sets the number of bytes of 1 line of the line buffer to be an odd number, in the present embodiment, 15 bytes, and DMA-transfers it to the local memory 29 after the developed recording data is accumulated to be 15 bytes in the A or B face of the line buffer 281. Therefore, the upper address part (odd address part) of the word data including the recording data of 15 bytes gets DMA-transferred in the state of 00H.

Transfers S61 to S64 will not be described because they are the same as the Transfers S1 to S4 in the first embodiment (Fig. 7). Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is FFH and FEH (Transfer S65). The lower address (even address) of FFH is the data, besides the data of the count of FBH. Therefore, FFH is repeatedly developed 6 times (257-251=6) , and stored in order in the A face of the line buffer 281. And, the upper address (odd address) of FFH is the count, and the next data is repeatedly developed 2 times (257-255=2) and stored in order in the A face of the line buffer 281.

Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is 11H and 06H (Transfer S66). The lower address (even address) of 11H is the data, besides the data of the previous count of FFH. Therefore, FFH is repeatedly developed 2 times, and stored in order in the A face of the line buffer 281. And, the upper address (odd address) of 06H is the count, and the next data (66H, 12H, 77H, 45H, 89H, 10H and 55H) of 7 bytes (6+1=7) is developed as it is without repetition, and stored in order in the B face of the line buffer 281 (Transfers S67 to S70).

In the mean time, when the developed recording data has been accumulated to be the number of bytes of 1 line in the A face of the line buffer 281, namely, 15 bytes (at the Transfer S66), the 15 bytes are DMA-transferred to the local memory 29 one word each as a data block of the 1 line. At that time, the L-DMA controller 413 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data after 1 line development is completely DMA-transferred to the local memory 29 (Transfer D1) . The recording data of 1 line transferred to the local memory 29 is vertically rearranged in line by the data rearranging means described above and stored 1 word each in order in the predetermined bitmap area of the local memory 29 at the first of the even address from the lower address (Fig. 15A). In addition, if the data is not vertically rearranged in line, then it is stored in order as it is (Fig. 16A) . Then, in the same way, the run length compressed recording data is hardware-developed by the decode circuit 28 (Transfers S71 to S84), and when the recording data developed in the line buffer 281 has been accumulated to be 1 line bytes (15 bytes) the data is DMA-transferred to the local memory 29 (Transfers D2 to D4) .

Fig. 17 and Fig. 18 are diagrams schematically showing the state until the compressed recording data is hardware-developed in the decode circuit 28 and stored in the line buffer 281, in case the quantity of 1 line is 15 bytes in regard to the third embodiment described above.

Transfers S91 to S94 will not be described because they are the same as the Transfers S31 to S34 in the second embodiment (Fig. 11). Continuously, the compressed recording data DMA-transferred to the decode circuit 28 is FFH and 11H (Transfer S95). The lower address (even address) of FFH is the count, and the upper address (odd address) of 11H is the data. Therefore, 11H is repeatedly developed 2 times (257-255=2), and stored in order in the A face of the line buffer 281.

And, when the developed recording data has been accumulated to be the number of bytes of 1 line in the A face of the line buffer 281, namely, 15 bytes (at the Transfer S95), the 15 bytes are DMA-transferred to the local memory 29 one word each as a data block of the 1 line. At that time, the L-DMA controller 413 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data after 1 line development is completely DMA-transferred to the local memory 29 (Transfer D1). The recording data of 1 line transferred to the local memory 29 is vertically rearranged in line by the data rearranging means described above and stored 1 word each in order in the predetermined bitmap area of the local memory 29 at the first of the even address from the lower address (Fig. 15A). In addition, if the data is not vertically rearranged in line by the data arranging means 493, then it is stored in order as it is (Fig. 16A). Then, in the same way, the run length compressedrecording data ishardware-developed by the decode circuit 28 (Transfers S71 to S84), and when the recording data developed in the line buffer 281 has been accumulated to be 1 line bytes (15 bytes) the data is DMA-transferred to the local memory 29 (Transfers D2 to D4).

In this way, since the recording data is DMA-transferred to the local memory 29 after the recording data developed in the line buffer 281 has been accumulated to be odd bytes, the transfer is performed while the upper address of the last word data is 00H, and thus the developed recording data can be stored in the bitmap area of the local memory 29 in order that the last 1 byte of 1 line is 00H and the recording data of 1 line is odd bytes as the data starting address is an even address as shown in Fig. 15D and Fig. 16D.

Further, as a fifth embodiment of the inkjet type recording apparatus 50 relating to the present invention, added to the second to fourth embodiments described above, the recording data is stored in the bitmap area of the local memory 29 in order that the recording data of 1 line is odd bytes as the data starting address is an even address.

In the nozzle arrays arranged in numbers and provided on the recording head 62, the colors of ink which is ejected are determined for each of the nozzle arrays. In the mean time, the recording data stored in the bitmap area of the local memory 29 becomes the data for each of the colors of ink corresponding to each of the nozzle arrays of each line. And, in regard to a means for correcting the lag of the ink ejecting timing caused by the nozzle arrays, there is a case that it is necessary to store the recording data of 1 line in the bitmap area of the local memory 29 letting the head address be an odd address.

However, as described above, by DMA-transferring one word each from the receiving buffer unit 42 to the decode circuit 28, the recording data developed in the bitmap area of the local memory 29 is stored while an even address is always positioned at the first, and thus in this state the recording data cannot be stored while an odd address is positioned at the first. Here, the data storage starting position shifting means 495 (Fig. 6) described above, when storing the recording data developed in the decode circuit 28 in the line buffer 281, in regard to the development processing controller 412 (Fig. 6), stores it from the first byte of the line buffer 281 in the state where the 0-th byte is vacant. That is, when the developed recording data is stored in the line buffer 281 after the compressed recording data is developed in the decode circuit 28, it is stored from the first byte of the line buffer 281 in the state where the 0-th byte is vacant, and the developed recording data stored in the line buffer 281 is DMA-transferred to the bitmap area of the local memory 29 from the 0-th byte of the line buffer 281.

Fig. 19 and Fig. 20 are diagrams schematically showing the state until the compressed recording data is hardware-developed in the decode circuit 28 and stored in the line buffer 281, in case the recording data is developed by the data storage starting position shifting means 495 from the first byte of the line buffer 281 in the state where the 0-th byte is vacant in regard to the second embodiment described above. In addition, Figs. 21A to 21D are diagrams schematically showing the state until the developed recording data of 1 line, 16 bytes, is transferred from the line buffer 281 to the local memory 29, and vertically rearranged in line by the data rearranging means 493 and stored while an odd address comes first.

As described above, the line buffer 231 has a reserve storage area of 1 word (2 bytes) which is added to the storage area of 8 words (16 bytes) for both of the A and B faces. The recording data developed 1 word each in the decode circuit 28 is stored from the first byte in the state where the 0-th byte of the A face of the line buffer is vacant. And, the 16-th byte of the recording data, which cannot help but be forced out from the storage area as the 0-th byte is made vacant, gets stored in the reserve storage area.

When the developed recording data has been accumulated to be 16 bytes in the A face of the line buffer 281, the 18 bytes (9 words) of the recording data in total, that is, the 16 bytes in the storage area and the data in the reserve storage area are DMA-transferred to the local memory 29 one word each as a data block of the 1 line. At that time, the L-DMA controller 413 (Fig. 6) transfers data in burst, occupying the local bus LB until all the recording data after 1 line development is completely DMA-transferred to the local memory 29 (Transfer D1). The recording data of 1 line transferred to the local memory 29 is vertically rearranged in line by the data rearranging means 493 described above and stored 1 word each in order in the predetermined bitmap area of the local memory 29 at the first of the even address from the lower address (Fig. 21A). Therefore, since data to which the vacant data of 1 byte at the first is added is DMA-transferred to the local memory 29 and stored at the even address of the bitmap area, the head data of the recording data of 1 line gets to be stored from the even address.

Then, in the same way, the run length compressed recording data is hardware-developed by the decode circuit 28, and when the recording data developed in the line buffer 281 has been accumulated to be 1 line bytes, 16 bytes, the data is DMA-transferred to the local memory 29 (Transfers D2 to D4). Further, transfers S121 to 8144 will not be described because they are the same as the Transfers S1 to S24 shown in Fig. 7.

In this way, since the recording data developed one word each in the decode circuit 28 is stored by the data storage starting position shifting means 495 from the first byte of the line buffer 281 in the state where the 0-th byte of the A face of the line buffer 281 is vacant, and it is DMA-transferred to the local memory 29 after the developed recording data of 16 bytes has been stored, the transfer is performed while the lower address of the first word data is 00H, and thus the developed recording data can be stored in the bitmap area of the local memory 29 in order that the first 1 byte of 1 line is 00H and the recording data of 1 line is odd bytes as the data starting address is an even address as shown in Fig. 21D.

Fig. 22 and Fig. 23 are diagrams schematically showing the state until the compressed recording data is hardware-developed in the decode circuit 28 and stored in the line buffer 281, in case the recording data is developed from the first byte of the line buffer 281 in the state where the 0-th byte is vacant in regard to the fourth embodiment described above. In addition, Figs. 24A to 24D are diagrams schematically showing the state until the developed recording data of 1 line, 15 bytes, is transferred from the line buffer 281 to the local memory 29, and vertically rearranged in line and stored while an odd address comes first.

In this way, the number of 1 line bytes can be 15 bytes, that is, odd bytes. Therefore, as shown in Fig. 24D, the storage in the bitmap area of the local memory 29 can be performed in order that the first 1 byte of 1 line is 00H and the data starting address of the recording data of 1 line, 15 bytes, is an even address.

In addition, Fig. 25 and Fig. 26 are diagrams schematically showing the state until the compressed recording data is hardware-developed in the decode circuit 28 and stored in the line buffer 261, in case the recording data is developed from the first byte of the line buffer 281 in the state where the 0-th byte is vacant in regard to the third embodiment described above and the recording data of 1 line is 16 bytes. In the same way, Fig. 27 and Fig. 28 shows ones in case the recording data is developed from the first byte of the line buffer 231 in the state where the 0-th byte is vacant in regard to the third embodiment described above and the recording data of 1 line is 15 bytes.

In this way, after the compressed recording data stored in the receiving buffer unit 42 while an odd address comes first is developed in the decode circuit 28, the recording data of 1 line, 15 or 16 bytes, can be stored in the bitmap area of the local memory 29 while an odd address comes first.

Further, as a sixth embodiment of the inkjet type recording apparatus 50 relating to the present invention, added to any of the first to fifth embodiments described above, the developed recording data is stored in two different bitmap areas of the local memory 29. Figs. 29A to 29D are diagrams schematically showing the state until the developed recording data of 1 line, 16 bytes, is transferred from the line buffer 281 to the local memory 29, and vertically rearranged in line and stored in the two different bitmap areas while an even address comes first.

If a dot interval of the sub scanning direction Y in regard to the developed bitmap data is smaller than an interval of the nozzle arrays adjacent to the sub scanning direction Y, the ink dots adjacent to the sub scanning direction Y cannot be formed simultaneously by one main scan, and thus it is formed during a different main scanning operation. However, since the bitmap data developed in the decode circuit 28 has a data configuration by which the ink ejection data formed to be adjacent to the sub scanning direction Y is continuously arranged, recording cannot be performed while the developed bitmap data is transferred to the recording head 62 as it is. For this reason, it is necessary to divide the developed bitmap data in order that the ink dot data adjacent to the sub scanning direction Y can be transferred to the recording head 62 during a different main scanning operation while it is stored in a different bitmap area.

in this regard, two different bitmap areas are provided in the local memory beforehand. In this embodiment, they are represented by image 1 and image 2 respectively. In regard to the bitmap area of the local memory 29 which is the DMA transfer destination, the data dividing means 494 described above sets the transfer destination addresses individually for each one word of the developed recording data stored in the line buffer 281 by the development processing controller 41 (Fig. 6) in order that the data of 1 line is stored in the image 1 and the image 2 in turn. And, the L-DMA controller 413 (Fig. 6) in the DECU 41 sets the individual transfer destination address to be the transfer destination address of DMA transfer, and DMA-transfers the developed recording data stored in the line buffer 281 to local memory 29 one word each.

First, when the developed recording data has been accumulated in the A face of the line buffer 281 to be 1 line of 16 bytes, the recording data of 1 line is DMA-transferred to the local memory 29 (Transfer D1), and stored in the image 1 (Fig. 29A. Continuously, after the developed recording data has been accumulated in the B face of the line buffer 281 to be 1 line of 16 bytes, the recording data of 1 line is DMA-transferred to the local memory 29 (Transfer D2), and stored in the image 2 (Fig. 29B. Continuously, when the developed recording data has been accumulated in the A face of the line buffer 281 to be 1 line of 16 bytes, the recording data of 1 line is DMA-transferred to the local memory 29 (Transfer D3), and stored in the image 1 (Fig. 29C, Continuously, after the developed recording data has been accumulated in the B face of the line buffer 281 to be 1 line of 16 bytes, the recording data of 1 line is DMA-transferred to the local memory 29 (Transfer D4), and stored in the image 2 (Fig. 29D).

In this way, the developed recording data stored in the line buffer 281 after the compressed recording data is developed is DMA-transferred to the different bitmap areas of the local memory 29 one line each in order that each of the ink dots adjacent to the sub scanning direction Y is formed during the different main scanning operations respectively. Owing to this, the development process of the compressed recording data (in the decode circuit 28) and the division of the developed recording data (in the development processing controller 412) can be performed at high speed by a hardware process. In addition, Figs. 30A to 30D are diagrams schematically showing the state until the developed recording data of 1 line, 16 bytes, is transferred from the line buffer 281 to the local memory 29, and stored in the two different bitmap areas, while an even address comes first, as it is without being vertically rearranged in line.

In addition, Figs. 31A to 31D are diagrams schematically showing the state until the developed recording data of 1 line, 16 bytes, is transferred from the line buffer 281 to the local memory 29, and vertically rearranged in line and stored in the two different bitmap areas, while an even address comes first. Figs. 32A to 32D are diagrams schematically showing the state until the developed recording data of 1 line, 15 bytes, is transferred from the line buffer 281 to the local memory 29, and stored in the two different bitmap areas, while an even address comes first, as it is without being vertically rearranged in line.

In this way, the developed recording data of odd bytes, as the number of bytes of 1 line is an odd number, is DMA-transferred to the local memory 29 after it has been stored in the line buffer 281, and thus the recording data of 1 line is transformed while the upper address of the last word data is 00H. Therefore, the developed recording data stored in the bitmap area of the local memory 29 is stored in the two different bitmap areas, the images 1 and 2, for each line in order that the last 1 byte of 1 line is 00H and the recording data of 1 line is odd bytes as the data starting address is an odd address.

In addition, Figs. 33A to 33D are diagrams schematically showing the state until the developed recording data of 1 line, 16 bytes, is transferred from the line buffer 281 to the local memory 29, and vertically rearranged in line and stored in the two different bitmap areas, while an odd address comes first. Figs. 34A to 34D are diagrams schematically showing the state until the developed recording data of 1 line, 15 bytes, is transferred from the line buffer 281 to the local memory 29, and vertically rearranged in line and stored in the two different bitmap areas, while an odd address comes first.

In this way, since the recording data developed one word each in the decode circuit 28 is stored from the first byte of the line buffer 281 in the state where the 0-th byte of the A face of the line buffer 281 is vacant, and it is DMA-transferred to the local memory 29 after the developed recording data of 16 bytes has been stored, the transfer is performed while the lower address of the first word data is 00H, and thus the recording data can be stored in each of the two different bitmap areas, the image 1 and the image 2, of the local memory 29 in order that the first 1 byte of 1 line is 00H and the data starting address of the recording data of 1 line is an odd address.

Further, as a seventh embodiment of the inkjet type recording apparatus 50 relating to the present invention, in regard to any of the first to sixth embodiments described above, if the recording data stored in the receiving buffer unit 42 is uncompressed data, it is stored in the bitmap area without development process. Fig. 35 is a diagram schematically showing the state where the uncompressed recording data is stored in the line buffer 281 as it is, and DMA-transferred to the local memory 29.

In this way, if the recording data transferred from the information processing apparatus 200 to the receiving buffer unit 42 is uncompressed data, it is stored in the line buffer 281 one word each by the non-developmentprocessing means 491 described above as it is without development process by the decode circuit 28. And then, like the case that the compressed recording data is developed by the decode circuit 28, in regard to the development processing controller (Fig. 6), the recording data can be, as shown by the second to sixth embodiments described above, stored in the two different bitmap areas by being rearranged by the data rearranging means 493 or being stored in the local memory 29 as the head address is an odd address by the data dividing means 494, the data storage starting position shifting means 495 and the data storage ending position shifting means 496, while 1 line bytes are set to be 16 or 15 bytes.

Although the invention has been described in its preferred form with a certain degree of particularity, obviously many changes and variations are possible therein. It is therefore to be understood that the present invention may be practiced than as specifically described herein without departing from scope thereof.


Anspruch[de]
Eine Datenübertragungsvorrichtung (100, 10) zum Übertragen von Flüssigkeitsausstoßdaten, umfassend: eine Decodiereinheit (41), die einen Decodierschaltkreis (28) umfasst, der Hardwareentwicklung auf Flüssigkeitsausstoßdaten durchführt, die pro Worteinheit von einem Hauptspeicher (22) über einen Systembus (SB)DMA-übertragen werden, die komprimiert werden, um Leitungsentwicklungsfähig zu sein; einen Leitungspuffer (281) zum Speichern von Flüssigkeitsausstoßdaten, die entwickelt werden durch den Decodierschaltkreis pro Worteinheit; eine DMA-Übertragungseinrichtung (411) zum DMA-Übertragen von Flüssigkeitsausstoßdaten, die komprimiert sind, um für Leitungsentwicklung fähig zu sein, von dem Hauptspeicher (22) zu dem Decodierschaltkreis (28); und DMA-Übertragen von Flüssigkeitsausstoßdaten, die in dem Leitungspuffer (281) entwickelt sind, zu dem lokalen Speicher (29) pro Worteinheit, und sequentielles DMA-Übertragen von entwickelten Flüssigkeitsausstoßdaten, die in dem lokalen Speicher gespeichert sind, zu einem Register eines Flüssigkeitsausstoßkopfes (62); dadurch gekennzeichnet, dass die Decodiereinheit (41) eine Datenspeicher-Startposition-Verschiebeeinrichtung (495) umfasst zum Speichern von Flüssigkeitsausstoßdaten, die von dem Decodierschaltkreis entwickelt werden, von einem ersten Byte des Leitungspuffers (281) in einem Zustand, wo ein 0-tes Byte des Leitungspuffers vakant ist. Eine Datenübertragungsvorrichtung (100, 10) zum Übertragen von Flüssigkeitsausstoßdaten, umfassend: eine Decodiereinheit (41), die einen Decodierschaltkreis (28) umfasst, der in der Lage ist, Hardwareentwicklung auf Flüssigkeitsausstoßdaten durchzuführen, die DMA-übertragen werden pro Worteinheit von einem Hauptspeicher (22) über einen Systembus (SB), die komprimiert werden, um über Leitungsentwicklung in der Lage zu sein; einen Leitungspuffer (281) zum Speichern von Flüssigkeitsausstoßdaten, die entwickelt werden durch den Decodierschaltkreis pro Worteinheit, und DMA-Übertragungseinrichtung (411) zum DMA-Übertragen von Flüssigkeitsausstoßdaten, die komprimiert sind, um über Leitungsentwicklung in der Lage zu sein, von dem Hauptspeicher (22) zu dem Decodierschaltkreis (28); und DMA-Übertragen von Flüssigkeitsausstoßdaten, die in dem Leitungspuffer (281) entwickelt sind, zu dem lokalen Speicher (29) pro Worteinheit, und sequentielles DMA-Übertragen von entwickelten Flüssigkeitsausstoßdaten, die in dem lokalen Speicher (29) gespeichert sind, zu einem Register eines Flüssigkeitsausstoßkopes (62); dadurch gekennzeichnet, dass die Decodiereinheit (41) eine Datenspeicher-Endposition-Verschiebeeinrichtung (496) umfasst zum Übertragen von entwickelten Flüssigkeitsausstoßdaten, die in dem Leitungspuffer (281) gespeichert sind, zu dem Flüssigkeitsausstoßkopf (62), jedes mal, wenn entwickelte Daten der vorbestimmten Wörter, von denen ein Byte subtrahiert wurde, in dem Leitungspuffer (281) gespeichert werden. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach Anspruch 1, wobei die Decodiereinheit eine Datenspeicher-Endposition-Verschiebeeinrichtung (496) umfasst zum Übertragen von entwickelten Flüssigkeitsausstoßdaten, die in dem Leitungspuffer gespeichert sind, zu dem Flüssigkeitsausstoßkopf, jedes mal, wenn entwickelte Daten der vorbestimmten Wörter, von denen ein Byte subtrahiert wurde, in dem Leitungspuffer gespeichert werden. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 2 bis 3, wobei die Datenübertragungsvorrichtung eine ungültige Datenmasken-Bearbeitungseinrichtung (492) umfasst zum Annullieren von Daten von den Kopfdaten von so vielen Bytes wie der Rest resultierend aus dem Dividieren eines Wertes einer Datenstartadresse von komprimierten Flüssigkeitsausstoßdaten durch die Anzahl von Datenbytes, die der Systembus pro Datenübertragung übertragen kann, mit Bezug auf Wortdaten, die Kopfdaten von komprimierten Daten beinhalten, die DMA-übertragen werden von dem Hauptspeicher zu dem Decodierschaltkreis. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 1 bis 3, wobei die Datenübertragungsvorrichtung eine ungültige Datenmasken-Bearbeitungseinrichtung (492) umfasst zum Annullieren von Daten von den Kopfdaten von einem Byte im Fall, dass die Datenstartadresse der komprimierten Daten, die in dem Hauptspeicher gespeichert sind, eine ungerade Adresse ist, mit Bezug auf Wortdaten, die Kopfdaten von komprimierten Daten beinhalten, die DMA-übertragen werden von dem Hauptspeicher zu dem Decodierschaltkreis. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 1 bis 5, wobei die Datenübertragungsvorrichtung zwei unabhängige Busse umfasst, die der Systembus (SB) und ein lokaler Bus (LB) sind, wobei dem Hauptspeicher an den Systembus gekoppelt ist, der in der Lage ist, Daten zu übertragen, und der lokale Speicher mit dem lokalen Bus gekoppelt ist, der in der Lage ist, Daten zu übertragen, und wobei die Decodiereinheit mit dem Systembus und dem lokalen Bus gekoppelt ist, um Daten dazwischen zu übertragen. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 1 bis 6, wobei eine ASIC jeweils Register des Hauptspeichers, der Decodiereinheit und des Flüssigkeitsausstoßkopfes umfasst, und wobei Register der Decodiereinheit und des Flüssigkeitsausstoßkopfes gekoppelt sind über einen zugehörigen Bus in dem ASIC. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 1 bis 7, wobei der Leitungspuffer zwei Seiten von Puffergebieten umfasst, die in der Lage sind, entwickelte Daten von vorbestimmten Wörtern zu speichern, wobei Flüssigkeitsausstoßdaten durch den Decodierschaltkreis sequentiell in einer ersten Seite der Puffergebiete gespeichert werden, während Flüssigkeitsausstoßdaten, die von dem Decodierschaltkreis entwickelt werden, sequentiell gespeichert werden in einer zweiten Seite der Puffergebiete, wenn entwickelte Daten von vorbestimmten Wörtern akkumuliert wurden, und entwickelte Daten werden DMA-übertragen zu dem lokalen Speicher für vorbestimmte Wörter, wenn entwickelte Daten von vorbestimmten Wörtern akkumuliert wurden. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 1 bis 8, wobei Datenübertragungen mit Bezug auf den lokalen Bus von dem Decodierschaltkreis zu dem lokalen Speicher und von dem lokalen Speicher zu einem Register des Flüssigkeitsausstoßkopfes in einer ersten Signalfolge-Übertragung durchgeführt werden. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 1 bis 9, wobei die komprimierten Flüssigkeitsausstoßdaten Lauflängen komprimierte Daten sind, und der Decodierschaltkreis Hardwareentwicklung auf den Lauflängen komprimierten Daten durchführen kann. Eine Datenübertragungsvorrichtung zum Übertragen von Flüssigkeitsausstoßdaten nach einem der Ansprüche 1 bis 10, wobei die Decodiereinheit eine Nicht-Entwicklungs-Bearbeitungseinrichtung umfasst zum Speichern von unkomprimierten Flüssigkeitsausstoßdaten, die DMA-übertragen werden von dem Hauptspeicher in den Leitungspuffer ohne Hardwareentwicklung durch den Decodierschaltkreis. Eine Flüssigkeitsausstoßvorrichtung (50), die eine Datenübertragungsvorrichtung nach einem der vorangehenden Ansprüche umfasst.
Anspruch[en]
A data transferring apparatus (100,10) for transferring liquid ejection data, comprising: a decode unit (41) comprising a decode circuit (28) performing hardware development on liquid ejection data, which is DMA-transferred per word unit from a main memory (22) via a system bus (SB), compressed to be capable of line development; a line buffer (281) for storing liquid ejection data developed by said decode circuit per word unit; a DMA-transferring means (411) for DMA-transferring liquid ejection data compressed to be capable of line development from said main memory (22) to said decode circuit (28); and DMA-transferring liquid ejection data developed in said line buffer (281) to a local memory (29) per word unit and DMA-transferring developed liquid ejection data stored in said local memory to a register of an liquid ejecting head (62) sequentially, characterized in that, said decode unit (41) comprises a data storage starting position shifting means (495) storing liquid ejection data developed by said decode circuit from a first byte of said line buffer (281) in a state where a 0-th byte of said line buffer is vacant. A data transferring apparatus (100, 10) for transferring liquid ejection data, comprising: a decode unit (41) comprising a decode circuit (28) capable of performing hardware development on liquid ejection data, which is DMA-transferred per word unit from a main memory (22) via a system bus (SB), compressed to be capable of line development; a line buffer (281) for storing liquid ejection data developed by said decode circuit per word unit and a DMA-transferring means (411) for DMA-tranferring liquid ejection data compressed to be capable of line development from said main memory (22) to said decode circuit (28); and DMA-transferring liquid ejection data developed in said line buffer (281) to a local memory (29) per word unit and DMA-transferring developed liquid ejection data stored in said local memory (29) to a register of an liquid ejecting head (62) sequentially, characterized in that, said decode unit (41) comprises a data storage ending position shifting means (496) for transferring developed liquid ejection data stored in said line buffer (281) to liquid ejecting head (62) each time developed data of said predetermined words from which one byte has been substracted is stored in said line buffer (281). A data transferring apparatus for transferring liquid ejection data as claimed in claim 1, wherein said decode (496) unit comprises a data storage ending position shifting means for transferring developed liquid ejection data stored in said line buffer to liquid ejecting head each time developed data of said predetermined words from which one byte has been subtracted is stored in said line buffer. A data transferring apparatus for transferring liquid ejection data as claimed in any of claims 2 to 3, wherein said data transferring apparatus comprises an invalid data mask processing means (492) for nullifying data from head data, as many bytes as a remainder resulting from dividing a value of a data starting address of compressed liquid ejection data by the number of data bytes which said system bus can transfer per one data transfer, with respect to word data including head data of compressed data DMA-transferred from said main memory to said decode circuit. A data transferring apparatus for transferring liquid ejection data as claimed in any of claim 1 to 3, wherein said data transferring apparatus comprises an invalid data mask processing means (492) for nullifying head data of one byte in case data starting address of compressed data stored in said main memory is an odd address, with respect to word data including head data of compressed data DMA-transferred from said main memory to said decode circuit. A data transferring apparatus for transferring liquid ejection data as claimed in any of claims 1 to 5, wherein said data transferring apparatus comprises two independent buses which are said system bus (SB) and a local bus (LB) said main memory coupled to said system bus, capable of transferring data and said local memory coupled to said local bus, capable of transferring data, and said decode unit is coupled to said system bus and local bus in order to transfer data therebetween. A data transferring apparatus for transferring liquid ejection data as claimed in any of claims 1 to 6, wherein an ASIC comprises registers of said main memory, said decode unit and said liquid ejecting head as a circuit block respectively, and registers of said decode unit and said liquid ejecting head are coupled through an dedicated bus in said ASIC. A data transferring apparatus for transferring liquid ejection data as claimed in any of claims 1 to 7, wherein said line buffer comprises two faces of buffer areas capable of storing developed data of predetermined words, liquid ejection data developed by the decode circuit is sequentially stored in a first face of the buffer areas while liquid ejection data developed by said decode circuit is sequentially stored in a second face of said buffer areas when developed data of predetermined words has been accumulated, and developed data is DMA-transferred to said local memory per predetermined words when developed data of predetermined words has been accumulated. A data transferring apparatus for transferring liquid ejection data as claimed in any of claims 1 to 8, wherein data transfers with respect to said local bus from said decode circuit to said local memory and from said local memory to a register of said liquid ejecting head are performed in a burst transfer. A data transferring apparatus for transferring liquid ejection data as claimed in any of claims 1 to 9, wherein said compressed liquid ejection data is run length compressed data, and said decode circuit can perform hardware development on run length compressed data. A data transferring apparatus for transferring liquid ejection data as claimed in any of claims 1 to 10, wherein said decode unit comprises a non-development processing means for storing uncompressed liquid ejection data DMA-transferred from said main memory in said line buffer without hardware development by said decode circuit. A liquid ejecting apparatus (50) comprising a data transferring apparatus according to any of the preceding claims.
Anspruch[fr]
Appareil (100,10) de transfert de données pour le transfert de données d'émission de liquide, comprenant : une unité de décodage (41) comprenant un circuit de décodage (28) effectuant un développement de matériel sur des données d'émission de liquide, qui sont transférées par accès direct à la mémoire par unité de mot à partir d'une mémoire principale (22) via un bus de système (SB), compressées pour être aptes à un développement en ligne ; une mémoire tampon de ligne (281) destinée à mémoriser les données d'émission de liquide développées par ledit circuit de décodage par unité de mot ; un moyen (411) de transfert par accès direct à la mémoire destiné à transférer par accès direct à la mémoire les données d'émission de liquide compressées pour être aptes à un développement en ligne depuis ladite mémoire principale (22) vers ledit circuit de décodage (28) ; et transférant par accès direct à la mémoire les données d'émission de liquide développées dans ladite mémoire tampon de ligne (281) vers une mémoire locale (29) par unité de mot et transférant par accès direct à la mémoire les données d'émission de liquide développées mémorisées dans ladite mémoire locale séquentiellement vers un registre d'une tête (62) d'émission de liquide, caractérisé en ce que, ladite unité de décodage (41) comprend un moyen (495) de décalage de la position de départ de la mémorisation des données destiné à mémoriser les données d'émission de liquide développées par ledit circuit de décodage à partir d'un premier byte de ladite mémoire tampon de ligne (281) dans une situation où un 0me byte de ladite mémoire tampon de ligne est libre. Appareil (100,10) de transfert de données pour le transfert de données d'émission de liquide, comprenant : une unité de décodage (41) comprenant un circuit de décodage (28) apte à effectuer un développement de matériel sur des données d'émission de liquide, qui sont transférées par accès direct à la mémoire par unité de mot à partir d'une mémoire principale (22) via un bus de système (SB), compressées pour être aptes à un développement en ligne ; une mémoire tampon de ligne (281) destinée à mémoriser les données d'émission de liquide développées par ledit circuit de décodage par unité de mot et un moyen (411) de transfert par accès direct à la mémoire destiné à transférer par accès direct à la mémoire les données d'émission de liquide compressées pour être aptes à un développement en ligne depuis ladite mémoire principale (22) vers ledit circuit de décodage (28) ; et transférant par accès direct à la mémoire les données d'émission de liquide développées dans ladite mémoire tampon de ligne (281) vers une mémoire locale (29) par unité de mot et transférant par accès direct à la mémoire les données d'émission de liquide développées mémorisées dans ladite mémoire locale (29) séquentiellement vers un registre d'une tête (62) d'émission de liquide, caractérisé en ce que, ladite unité de décodage (41) comprend un moyen (496) de décalage de la position de fin de la mémorisation des données destiné à transférer les données d'émission de liquide développées mémorisées dans ladite mémoire tampon de ligne (281) vers la tête (62) d'émission de liquide chaque fois que des données développées desdits mots prédéterminés à partir desquels un byte a été soustrait sont mémorisées dans ladite mémoire tampon de ligne (281). Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans la revendication 1, dans lequel ladite unité de décodage comprend un moyen (496) de décalage de la position de fin de la mémorisation de données destiné à transférer les données d'émission de liquide développées mémorisées dans ladite mémoire tampon de ligne vers une tête d'émission de liquide chaque fois que des données développées desdits mots prédéterminés à partir desquels un byte a été soustrait sont mémorisées dans ladite mémoire tampon de ligne. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 2 à 3, dans lequel ledit appareil de transfert de données comprend un moyen (492) de traitement par un masque de données non valides destiné à annuler des données venant des données de la tête, telles que plusieurs bytes constituant un reste résultant d'une division d'une valeur d'une adresse de départ de données des données d'émission de liquide compressées par le nombre de bytes de données que ledit bus du système peut transférer par un seul transfert de données, par rapport aux données de mot comprenant les données de la tête des données compressées transférées par accès direct à la mémoire depuis ladite mémoire principale vers ledit circuit de décodage. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 1 à 3, dans lequel ledit appareil de transfert de données comprend un moyen (492) de traitement par un masque de données non valides destiné à annuler des données de la tête d'un seul byte dans le cas où l'adresse de départ de données des données compressées mémorisées dans ladite mémoire principale est une adresse impaire, par rapport aux données de mot comprenant les données de la tête des données compressées transférées par accès direct à la mémoire depuis ladite mémoire principale vers ledit circuit de décodage. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 1 à 5, dans lequel ledit appareil de transfert de données comprend deux bus indépendants qui sont ledit bus du système (SB) et un bus local (LB), ladite mémoire principale étant couplée audit bus du système, apte à transférer des données et ladite mémoire locale étant couplée audit bus local, apte à transférer des données, et ladite unité de décodage est couplée audit bus du système et bus local afin de transférer des données entre eux. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 1 à 6, dans lequel un circuit intégré à application spécifique (ASIC) comprend des registres de ladite mémoire principale, ladite unité de décodage et ladite tête d'émission de liquide formant respectivement un bloc de circuit, et les registres de ladite unité de décodage et ladite tête d'émission de liquide sont couplés par l'intermédiaire d'un bus spécialisé dans ledit circuit intégré à application spécifique. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 1 à 7, dans lequel ladite mémoire tampon de ligne comprend deux faces de zones de la mémoire tampon aptes à mémoriser des données développées de mots prédéterminés, les données d'émission de liquide développées par le circuit de décodage sont mémorisées séquentiellement dans une première face des zones de la mémoire tampon alors que les données d'émission de liquide développées par ledit circuit de décodage sont mémorisées séquentiellement dans une seconde face desdites zones de la mémoire tampon lorsque les données développées des mots prédéterminés ont été accumulées, et les données développées sont transférées par accès direct à la mémoire vers ladite mémoire locale par mots prédéterminés lorsque les données développées des mots prédéterminés ont été accumulées. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 1 à 8, dans lequel les transferts de données par rapport audit bus local depuis ledit circuit de décodage vers ladite mémoire locale et depuis ladite mémoire locale vers un registre de ladite tête d'émission de liquide sont effectués dans un transfert en rafales. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 1 à 9, dans lequel lesdites données d'émission de liquide compressées sont des données compressées par encodage en plage, et ledit circuit de décodage peut effectuer un développement de matériel sur les données compressées par encodage en plage. Appareil de transfert de données pour le transfert de données d'émission de liquide tel que revendiqué dans l'une quelconque des revendications 1 à 10, dans lequel ladite unité de décodage comprend un moyen de traitement sans développement destiné à mémoriser des données d'émission de liquide non compressées transférées par accès direct à la mémoire depuis ladite mémoire principale dans ladite mémoire tampon de ligne sans développement de matériel par ledit circuit de décodage. Appareil (50) d'émission de liquide comprenant un appareil de transfert de données selon l'une quelconque des revendications précédentes.






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